Commit 2740e5de authored by Fabio Estevam's avatar Fabio Estevam Committed by Anatolij Gustschin
Browse files

video: ipu_disp: Fix clock polarity logic

Currently the HDMI splash screen image quality on mx6solo does not show a
very stable image.

By comparing the IPU driver from U-boot with the one from FSL 4.1.0 BSP,
we can see that there is an inverted logic for setting the DI_GEN_POL_CLK bit.

>From FSL BSP [1] we have:

	if (!sig.clk_pol)

Applying the same logic into U-boot fixes the HDMI image stability.


Signed-off-by: default avatarFabio Estevam <>
Tested-by: default avatarEric Nelson <>
Acked-by: default avatarEric Nelson <>
Acked-by: default avatarStefano Babic <>
parent 7e575c46
......@@ -1178,7 +1178,7 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk,
if (sig.Vsync_pol)
di_gen |= DI_GEN_POLARITY_3;
if (sig.clk_pol)
if (!sig.clk_pol)
di_gen |= DI_GEN_POL_CLK;
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