Commit 281e00a3 authored by wdenk's avatar wdenk
Browse files

* Code cleanup

* Patch by Sascha Hauer, 28 Jun:
  - add generic support for Motorola i.MX architecture
  - add support for mx1ads, mx1fs2 and scb9328 boards

* Patches by Marc Leeman, 23 Jul 2004:
  - Add define for the PCI/Memory Buffer Configuration Register
  - corrected comments in cpu/mpc824x/cpu_init.c

* Add support for multiple serial interfaces
  (for example to allow modem dial-in / dial-out)
parent cfca5e60
......@@ -2,12 +2,23 @@
Changes since U-Boot 1.1.1:
======================================================================
* Patch by Sascha Hauer, 28 Jun:
- add generic support for Motorola i.MX architecture
- add support for mx1ads, mx1fs2 and scb9328 boards
* Patches by Marc Leeman, 23 Jul 2004:
- Add define for the PCI/Memory Buffer Configuration Register
- corrected comments in cpu/mpc824x/cpu_init.c
* Add support for multiple serial interfaces
(for example to allow modem dial-in / dial-out)
* Patch by Stefan Roese, 15 Jul 2004:
cpu/ppc4xx/sdram.c rewritten now using get_ram_size()
* Fix NSCU config; add ethernet wakeup code.
* Add link for preloader for Motorola Coldfire to RAEDME.m68k
* Add link for preloader for Motorola Coldfire to README.m68k
* Patch by Michael Bendzick, 12 Jul 2004:
fix output formatting in drivers/cfi_flash.c
......
......@@ -139,11 +139,10 @@ LIST_ARM7="B2 ep7312 evb4510 impa7 modnet50"
#########################################################################
LIST_ARM9=" \
at91rm9200dk integratorcp integratorap \
lpd7a400 mx1ads omap1510inn \
omap1610h2 omap1610inn omap730p2 \
smdk2400 smdk2410 trab \
VCMA9 versatile \
at91rm9200dk integratorcp integratorap lpd7a400 \
mx1ads mx1fs2 omap1510inn omap1610h2 \
omap1610inn omap730p2 scb9328 smdk2400 \
smdk2410 trab VCMA9 versatile \
"
#########################################################################
......
......@@ -757,6 +757,7 @@ PLU405_config: unconfig
PMC405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx pmc405 esd
PPChameleonEVB_config \
PPChameleonEVB_BA_25_config \
PPChameleonEVB_ME_25_config \
PPChameleonEVB_HI_25_config \
......@@ -1154,6 +1155,12 @@ lpd7a400_config \
lpd7a404_config: unconfig
@./mkconfig $(@:_config=) arm lh7a40x lpd7a40x
mx1ads_config : unconfig
@./mkconfig $(@:_config=) arm arm920t mx1ads
mx1fs2_config : unconfig
@./mkconfig $(@:_config=) arm arm920t mx1fs2
omap1510inn_config : unconfig
@./mkconfig $(@:_config=) arm arm925t omap1510inn
......@@ -1192,6 +1199,9 @@ omap730p2_cs3boot_config : unconfig
fi;
@./mkconfig -a $(call xtract_omap730p2,$@) arm arm926ejs omap730p2
scb9328_config : unconfig
@./mkconfig $(@:_config=) arm arm920t scb9328
smdk2400_config : unconfig
@./mkconfig $(@:_config=) arm arm920t smdk2400
......@@ -1239,13 +1249,6 @@ versatile_config : unconfig
B2_config : unconfig
@./mkconfig $(@:_config=) arm s3c44b0 B2 dave
#########################################################################
## MC9328 (Dragonball) Systems
#########################################################################
mx1ads_config : unconfig
@./mkconfig $(@:_config=) arm mc9328 mx1ads
#########################################################################
## ARM720T Systems
#########################################################################
......
......@@ -40,6 +40,7 @@ V* Verification: dzu@denx.de
#include <command.h>
#include <malloc.h>
#include <post.h>
#include <serial.h>
#include <linux/types.h>
#include <linux/string.h> /* for strdup */
......@@ -468,6 +469,13 @@ int board_postclk_init (void)
return (0);
}
struct serial_device * default_serial_console (void)
{
DECLARE_GLOBAL_DATA_PTR;
return gd->do_mdm_init ? &serial_scc_device : &serial_smc_device;
}
static void kbd_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
......
......@@ -23,9 +23,9 @@
* MA 02111-1307 USA
*/
#include <common.h>
#include <mc9328.h>
/*#include <mc9328.h>*/
#include <asm/arch-arm920t/imx-regs.h>
/* ------------------------------------------------------------------------- */
......@@ -67,7 +67,6 @@ static inline void delay (unsigned long loops) {
* Miscellaneous platform dependent initialisations
*/
void SetAsynchMode(void) {
__asm__ (
"mrc p15,0,r0,c1,c0,0 \n"
......@@ -85,42 +84,34 @@ int board_init (void) {
volatile unsigned int tmp;
mc9328sid = MX1_SIDR;
mc9328sid = SIDR;
MX1_GPCR = 0x000003AB; /* I/O pad driving strength */
GPCR = 0x000003AB; /* I/O pad driving strength */
/* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */
/* MX1_CS1L = 0x11110601; */
MX1_MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */
/* MX1_MPCTL0 = 0x003f1437; */ /* setting for 192 MHz MCU PLL CLK */
MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */
/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and
* BCLK divider to 2 (i.e. BCLK to 48 MHz)
*/
MX1_CSCR = 0xAF000403;
CSCR = 0xAF000403;
MX1_CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */
MX1_CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */
CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */
CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */
/* setup cs4 for cs8900 ethernet */
MX1_CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */
MX1_CS4L = 0x00001501;
CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */
CS4L = 0x00001501;
MX1_GIUS_A &= 0xFF3FFFFF;
MX1_GPR_A &= 0xFF3FFFFF;
GIUS(0) &= 0xFF3FFFFF;
GPR(0) &= 0xFF3FFFFF;
tmp = *(unsigned int *)(0x1500000C);
tmp = *(unsigned int *)(0x1500000C);
/* setup timer 1 as system timer */
MX1_TPRER1 = 0x1f; /* divide by 32 */
MX1_TCTL1 = 0x19; /* clock in from 32k Osc. */
SetAsynchMode();
gd->bd->bi_arch_number = 160; /* Arch number of MX1ADS Board */
......@@ -131,19 +122,19 @@ int board_init (void) {
dcache_enable();
/* set PERCLKs */
MX1_PCDR = 0x00000055; /* set PERCLKS */
PCDR = 0x00000055; /* set PERCLKS */
/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
* PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place
* all sources selected as normal interrupt
*/
MX1_INTTYPEH = 0;
MX1_INTTYPEL = 0;
/* MX1_INTTYPEH = 0;
MX1_INTTYPEL = 0;
*/
return 0;
}
int board_late_init(void) {
setenv("stdout", "serial");
......@@ -163,13 +154,10 @@ int board_late_init(void) {
default :
printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",mc9328sid);
break;
}
return 0;
}
int dram_init (void) {
DECLARE_GLOBAL_DATA_PTR;
......
......@@ -24,7 +24,8 @@
*/
#include <common.h>
#include <mc9328.h>
/*#include <mc9328.h>*/
#include <asm/arch/imx-regs.h>
typedef unsigned long * p_u32;
......@@ -33,27 +34,26 @@ typedef unsigned long * p_u32;
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/* Following Setting is for CSD1 */
#define SFCTL 0x00221004
#define reg_SFCTL __REG(SFCTL)
#define SFCTL 0x00221004
#define reg_SFCTL __REG(SFCTL)
#define SYNCFLASH_A10 (0x00100000)
#define SYNCFLASH_A10 (0x00100000)
#define CMD_NORMAL (0x81020300) /* Normal Mode */
#define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */
#define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */
#define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */
#define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */
#define CMD_PROGRAM (CMD_NORMAL + 0x70000000)
#define CMD_NORMAL (0x81020300) /* Normal Mode */
#define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */
#define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */
#define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */
#define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */
#define CMD_PROGRAM (CMD_NORMAL + 0x70000000)
#define MODE_REG_VAL (CFG_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */
#define MODE_REG_VAL (CFG_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */
/* LCR Command */
#define LCR_READSTATUS (0x0001C000) /* 0x70 */
#define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */
#define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */
#define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */
#define LCR_SR_CLEAR (0x00014000) /* 0x50 */
#define LCR_READSTATUS (0x0001C000) /* 0x70 */
#define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */
#define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */
#define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */
#define LCR_SR_CLEAR (0x00014000) /* 0x50 */
/* Get Status register */
u32 SF_SR(void) {
......@@ -82,7 +82,6 @@ u8 SF_Ready(void) {
if ((tmp & 0x00000080) && (tmp & 0x0000001C)) {
printf ("SyncFlash Error code %08x\n",tmp);
};
if (tmp == 0x00800080) /* Test Bit 7 of SR */
......@@ -98,7 +97,6 @@ void SF_PrechargeAll(void) {
reg_SFCTL = CMD_PREC; /* Set Precharge Command */
tmp = __REG(CFG_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */
}
/* set SyncFlash to normal mode */
......@@ -128,7 +126,6 @@ void SF_Erase(u32 RowAddress) {
while(!SF_Ready());
}
void SF_NvmodeErase(void) {
SF_PrechargeAll();
......@@ -149,10 +146,8 @@ void SF_NvmodeWrite(void) {
reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */
__REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; /* Confirm not needed */
}
/****************************************************************************************/
ulong flash_init(void) {
......@@ -195,7 +190,6 @@ ulong flash_init(void) {
return FLASH_BANK_SIZE;
}
void flash_print_info (flash_info_t *info) {
int i;
......@@ -209,7 +203,6 @@ void flash_print_info (flash_info_t *info) {
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case (FLASH_MT28S4M16LC & FLASH_TYPEMASK):
printf("2x FLASH_MT28S4M16LC (16MB Total)\n");
......@@ -236,7 +229,6 @@ void flash_print_info (flash_info_t *info) {
printf ("\n");
}
/*-----------------------------------------------------------------------*/
int flash_erase (flash_info_t *info, int s_first, int s_last) {
......
......@@ -23,7 +23,6 @@
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
......@@ -34,7 +33,7 @@ SECTIONS
. = ALIGN(4);
.text :
{
cpu/mc9328/start.o (.text)
cpu/arm920t/start.o (.text)
*(.text)
}
......
#
# (C) Copyright 2000, 2001, 2002
# (C) Copyright 2000-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
......@@ -23,21 +23,25 @@
include $(TOPDIR)/config.mk
LIB = lib$(CPU).a
LIB = lib$(BOARD).a
START = start.o
OBJS = serial.o interrupts.o cpu.o
OBJS := mx1fs2.o flash.o
SOBJS := memsetup.o
all: .depend $(START) $(LIB)
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
$(LIB): $(OBJS)
$(AR) crv $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
-include .depend
#########################################################################
#
# This config file is used for compilation of IMX sources
#
# You might change location of U-Boot in memory by setting right TEXT_BASE.
# This allows for example having one copy located at the end of ram and stored
# in flash device and later on while developing use other location to test
# the code in RAM device only.
#
TEXT_BASE = 0x08f00000
This diff is collapsed.
/*
* Copyright (C) 2002 ETC s.r.o.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the ETC s.r.o. nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Written by Marcel Telka <marcel@telka.sk>, 2002.
*
* Documentation:
* [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A,
* 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011
* [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18,
* 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005
*
* This file is taken from OpenWinCE project hosted by SourceForge.net
*
*/
#ifndef FLASH_INTEL_H
#define FLASH_INTEL_H
#include <common.h>
/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */
#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */
#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */
/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */
#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */
/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */
#define CFI_CHIP_INTEL_28F320J3A 0x0016
#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A"
#define CFI_CHIP_INTEL_28F640J3A 0x0017
#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A"
#define CFI_CHIP_INTEL_28F128J3A 0x0018
#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A"
/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */
#define CFI_CHIP_INTEL_28F640K3 0x8801
#define CFI_CHIPN_INTEL_28F640K3 "28F640K3"
#define CFI_CHIP_INTEL_28F128K3 0x8802
#define CFI_CHIPN_INTEL_28F128K3 "28F128K3"
#define CFI_CHIP_INTEL_28F256K3 0x8803
#define CFI_CHIPN_INTEL_28F256K3 "28F256K3"
#define CFI_CHIP_INTEL_28F640K18 0x8805
#define CFI_CHIPN_INTEL_28F640K18 "28F640K18"
#define CFI_CHIP_INTEL_28F128K18 0x8806
#define CFI_CHIPN_INTEL_28F128K18 "28F128K18"
#define CFI_CHIP_INTEL_28F256K18 0x8807
#define CFI_CHIPN_INTEL_28F256K18 "28F256K18"
#endif /* FLASH_INTEL_H */
/*
* Copyright (C) 2004 Sascha Hauer, Pengutronix
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
* 02111-1307, USA.
*
*/
#include <config.h>
#include <version.h>
#include <asm/arch/imx-regs.h>
.globl memsetup
memsetup:
mov r10, lr
/* Change PERCLK1DIV to 14 ie 14+1 */
ldr r0, =PCDR
ldr r1, =CFG_PCDR_VAL
str r1, [r0]
/* set MCU PLL Control Register 0 */
ldr r0, =MPCTL0
ldr r1, =CFG_MPCTL0_VAL
str r1, [r0]
/* set MCU PLL Control Register 1 */
ldr r0, =MPCTL1
ldr r1, =CFG_MPCTL1_VAL
str r1, [r0]
/* set mpll restart bit */
ldr r0, =CSCR
ldr r1, [r0]
orr r1,r1,#(1<<21)
str r1, [r0]
mov r2,#0x10
1:
mov r3,#0x2000
2:
subs r3,r3,#1
bne 2b
subs r2,r2,#1
bne 1b
/* set System PLL Control Register 0 */
ldr r0, =SPCTL0
ldr r1, =CFG_SPCTL0_VAL
str r1, [r0]
/* set System PLL Control Register 1 */
ldr r0, =SPCTL1
ldr r1, =CFG_SPCTL1_VAL
str r1, [r0]
/* set spll restart bit */
ldr r0, =CSCR
ldr r1, [r0]
orr r1,r1,#(1<<22)
str r1, [r0]
mov r2,#0x10
1:
mov r3,#0x2000
2:
subs r3,r3,#1
bne 2b
subs r2,r2,#1
bne 1b
ldr r0, =CSCR
ldr r1, =CFG_CSCR_VAL
str r1, [r0]
ldr r0, =GPCR
ldr r1, =CFG_GPCR_VAL
str r1, [r0]
/*
* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
* this.....
*
* It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
* register 1, this stops it using the output of the PLL and thus runs at the
* slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
* use the value set in the CM_OSC registers...regardless of what you set it
* too! Thus, although i thought i was running at 140MHz, i'm actually running
* at 40!..
*
* Slapping this into my bootloader does the trick...
*
* MRC p15,0,r0,c1,c0,0 ; read core configuration register
* ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode
* MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration
* register
*
*/
MRC