Commit 28cd88ba authored by Tom Rini's avatar Tom Rini
Browse files

Merge branch 'master' of git://git.denx.de/u-boot-uniphier

parents 2f1eb66e e8a92932
...@@ -6,6 +6,8 @@ config SYS_CONFIG_NAME ...@@ -6,6 +6,8 @@ config SYS_CONFIG_NAME
config ARCH_UNIPHIER_32BIT config ARCH_UNIPHIER_32BIT
bool bool
select CPU_V7 select CPU_V7
select CPU_V7_HAS_NONSEC
select ARMV7_NONSEC
config ARCH_UNIPHIER_64BIT config ARCH_UNIPHIER_64BIT
bool bool
...@@ -70,6 +72,13 @@ config ARCH_UNIPHIER_LD6B ...@@ -70,6 +72,13 @@ config ARCH_UNIPHIER_LD6B
depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B
default y default y
config CACHE_UNIPHIER
bool "Enable the UniPhier L2 cache controller"
depends on ARCH_UNIPHIER_32BIT
default y
help
This option allows to use the UniPhier System Cache as L2 cache.
config MICRO_SUPPORT_CARD config MICRO_SUPPORT_CARD
bool "Use Micro Support Card" bool "Use Micro Support Card"
help help
......
...@@ -8,6 +8,7 @@ obj-$(CONFIG_DEBUG_LL) += debug_ll.o ...@@ -8,6 +8,7 @@ obj-$(CONFIG_DEBUG_LL) += debug_ll.o
else else
obj-y += late_lowlevel_init.o obj-y += late_lowlevel_init.o
obj-y += cache-uniphier.o obj-y += cache-uniphier.o
obj-$(CONFIG_ARMV7_PSCI) += psci.o psci_smp.o
endif endif
obj-y += timer.o obj-y += timer.o
...@@ -12,6 +12,9 @@ ...@@ -12,6 +12,9 @@
/* SCU Control Register */ /* SCU Control Register */
#define SCU_CTRL 0x00 #define SCU_CTRL 0x00
#define SCU_ENABLE (1 << 0)
#define SCU_STANDBY_ENABLE (1 << 5)
/* SCU Configuration Register */ /* SCU Configuration Register */
#define SCU_CONF 0x04 #define SCU_CONF 0x04
/* SCU CPU Power Status Register */ /* SCU CPU Power Status Register */
......
...@@ -8,11 +8,74 @@ ...@@ -8,11 +8,74 @@
#include <common.h> #include <common.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/kernel.h>
#include <asm/armv7.h> #include <asm/armv7.h>
#include <asm/processor.h>
#include "ssc-regs.h"
#include "cache-uniphier.h"
#ifdef CONFIG_UNIPHIER_L2CACHE_ON
/* control registers */
#define UNIPHIER_SSCC 0x500c0000 /* Control Register */
#define UNIPHIER_SSCC_BST (0x1 << 20) /* UCWG burst read */
#define UNIPHIER_SSCC_ACT (0x1 << 19) /* Inst-Data separate */
#define UNIPHIER_SSCC_WTG (0x1 << 18) /* WT gathering on */
#define UNIPHIER_SSCC_PRD (0x1 << 17) /* enable pre-fetch */
#define UNIPHIER_SSCC_ON (0x1 << 0) /* enable cache */
#define UNIPHIER_SSCLPDAWCR 0x500c0030 /* Unified/Data Active Way Control */
#define UNIPHIER_SSCLPIAWCR 0x500c0034 /* Instruction Active Way Control */
/* revision registers */
#define UNIPHIER_SSCID 0x503c0100 /* ID Register */
/* operation registers */
#define UNIPHIER_SSCOPE 0x506c0244 /* Cache Operation Primitive Entry */
#define UNIPHIER_SSCOPE_CM_INV 0x0 /* invalidate */
#define UNIPHIER_SSCOPE_CM_CLEAN 0x1 /* clean */
#define UNIPHIER_SSCOPE_CM_FLUSH 0x2 /* flush */
#define UNIPHIER_SSCOPE_CM_SYNC 0x8 /* sync (drain bufs) */
#define UNIPHIER_SSCOPE_CM_FLUSH_PREFETCH 0x9 /* flush p-fetch buf */
#define UNIPHIER_SSCOQM 0x506c0248
#define UNIPHIER_SSCOQM_TID_MASK (0x3 << 21)
#define UNIPHIER_SSCOQM_TID_LRU_DATA (0x0 << 21)
#define UNIPHIER_SSCOQM_TID_LRU_INST (0x1 << 21)
#define UNIPHIER_SSCOQM_TID_WAY (0x2 << 21)
#define UNIPHIER_SSCOQM_S_MASK (0x3 << 17)
#define UNIPHIER_SSCOQM_S_RANGE (0x0 << 17)
#define UNIPHIER_SSCOQM_S_ALL (0x1 << 17)
#define UNIPHIER_SSCOQM_S_WAY (0x2 << 17)
#define UNIPHIER_SSCOQM_CE (0x1 << 15) /* notify completion */
#define UNIPHIER_SSCOQM_CW (0x1 << 14)
#define UNIPHIER_SSCOQM_CM_MASK (0x7)
#define UNIPHIER_SSCOQM_CM_INV 0x0 /* invalidate */
#define UNIPHIER_SSCOQM_CM_CLEAN 0x1 /* clean */
#define UNIPHIER_SSCOQM_CM_FLUSH 0x2 /* flush */
#define UNIPHIER_SSCOQM_CM_PREFETCH 0x3 /* prefetch to cache */
#define UNIPHIER_SSCOQM_CM_PREFETCH_BUF 0x4 /* prefetch to pf-buf */
#define UNIPHIER_SSCOQM_CM_TOUCH 0x5 /* touch */
#define UNIPHIER_SSCOQM_CM_TOUCH_ZERO 0x6 /* touch to zero */
#define UNIPHIER_SSCOQM_CM_TOUCH_DIRTY 0x7 /* touch with dirty */
#define UNIPHIER_SSCOQAD 0x506c024c /* Cache Operation Queue Address */
#define UNIPHIER_SSCOQSZ 0x506c0250 /* Cache Operation Queue Size */
#define UNIPHIER_SSCOQMASK 0x506c0254 /* Cache Operation Queue Address Mask */
#define UNIPHIER_SSCOQWN 0x506c0258 /* Cache Operation Queue Way Number */
#define UNIPHIER_SSCOPPQSEF 0x506c025c /* Cache Operation Queue Set Complete */
#define UNIPHIER_SSCOPPQSEF_FE (0x1 << 1)
#define UNIPHIER_SSCOPPQSEF_OE (0x1 << 0)
#define UNIPHIER_SSCOLPQS 0x506c0260 /* Cache Operation Queue Status */
#define UNIPHIER_SSCOLPQS_EF (0x1 << 2)
#define UNIPHIER_SSCOLPQS_EST (0x1 << 1)
#define UNIPHIER_SSCOLPQS_QST (0x1 << 0)
#define UNIPHIER_SSC_LINE_SIZE 128
#define UNIPHIER_SSC_RANGE_OP_MAX_SIZE (0x00400000 - (UNIPHIER_SSC_LINE_SIZE))
#define UNIPHIER_SSCOQAD_IS_NEEDED(op) \
((op & UNIPHIER_SSCOQM_S_MASK) == UNIPHIER_SSCOQM_S_RANGE)
#define UNIPHIER_SSCOQWM_IS_NEEDED(op) \
(((op & UNIPHIER_SSCOQM_S_MASK) == UNIPHIER_SSCOQM_S_WAY) || \
((op & UNIPHIER_SSCOQM_TID_MASK) == UNIPHIER_SSCOQM_TID_WAY))
/* uniphier_cache_sync - perform a sync point for a particular cache level */
static void uniphier_cache_sync(void) static void uniphier_cache_sync(void)
{ {
/* drain internal buffers */ /* drain internal buffers */
...@@ -21,62 +84,56 @@ static void uniphier_cache_sync(void) ...@@ -21,62 +84,56 @@ static void uniphier_cache_sync(void)
readl(UNIPHIER_SSCOPE); readl(UNIPHIER_SSCOPE);
} }
static void uniphier_cache_maint_all(u32 operation) /**
* uniphier_cache_maint_common - run a queue operation
*
* @start: start address of range operation (don't care for "all" operation)
* @size: data size of range operation (don't care for "all" operation)
* @ways: target ways (don't care for operations other than pre-fetch, touch
* @operation: flags to specify the desired cache operation
*/
static void uniphier_cache_maint_common(u32 start, u32 size, u32 ways,
u32 operation)
{ {
/* clear the complete notification flag */ /* clear the complete notification flag */
writel(UNIPHIER_SSCOLPQS_EF, UNIPHIER_SSCOLPQS); writel(UNIPHIER_SSCOLPQS_EF, UNIPHIER_SSCOLPQS);
/* try until the command is successfully set */
do { do {
writel(UNIPHIER_SSCOQM_S_ALL | UNIPHIER_SSCOQM_CE | operation, /* set cache operation */
UNIPHIER_SSCOQM); writel(UNIPHIER_SSCOQM_CE | operation, UNIPHIER_SSCOQM);
} while (readl(UNIPHIER_SSCOPPQSEF) &
(UNIPHIER_SSCOPPQSEF_FE | UNIPHIER_SSCOPPQSEF_OE));
/* wait until the operation is completed */ /* set address range if needed */
while (readl(UNIPHIER_SSCOLPQS) != UNIPHIER_SSCOLPQS_EF) if (likely(UNIPHIER_SSCOQAD_IS_NEEDED(operation))) {
; writel(start, UNIPHIER_SSCOQAD);
writel(size, UNIPHIER_SSCOQSZ);
}
uniphier_cache_sync(); /* set target ways if needed */
} if (unlikely(UNIPHIER_SSCOQWM_IS_NEEDED(operation)))
writel(ways, UNIPHIER_SSCOQWN);
} while (unlikely(readl(UNIPHIER_SSCOPPQSEF) &
(UNIPHIER_SSCOPPQSEF_FE | UNIPHIER_SSCOPPQSEF_OE)));
void v7_outer_cache_flush_all(void) /* wait until the operation is completed */
{ while (likely(readl(UNIPHIER_SSCOLPQS) != UNIPHIER_SSCOLPQS_EF))
uniphier_cache_maint_all(UNIPHIER_SSCOQM_CM_FLUSH); cpu_relax();
}
void v7_outer_cache_inval_all(void)
{
uniphier_cache_maint_all(UNIPHIER_SSCOQM_CM_INV);
} }
static void __uniphier_cache_maint_range(u32 start, u32 size, u32 operation) static void uniphier_cache_maint_all(u32 operation)
{ {
/* clear the complete notification flag */ uniphier_cache_maint_common(0, 0, 0, UNIPHIER_SSCOQM_S_ALL | operation);
writel(UNIPHIER_SSCOLPQS_EF, UNIPHIER_SSCOLPQS);
/* try until the command is successfully set */
do {
writel(UNIPHIER_SSCOQM_S_RANGE | UNIPHIER_SSCOQM_CE | operation,
UNIPHIER_SSCOQM);
writel(start, UNIPHIER_SSCOQAD);
writel(size, UNIPHIER_SSCOQSZ);
} while (readl(UNIPHIER_SSCOPPQSEF) & uniphier_cache_sync();
(UNIPHIER_SSCOPPQSEF_FE | UNIPHIER_SSCOPPQSEF_OE));
/* wait until the operation is completed */
while (readl(UNIPHIER_SSCOLPQS) != UNIPHIER_SSCOLPQS_EF)
;
} }
static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation) static void uniphier_cache_maint_range(u32 start, u32 end, u32 ways,
u32 operation)
{ {
u32 size; u32 size;
/* /*
* If start address is not aligned to cache-line, * If the start address is not aligned,
* do cache operation for the first cache-line * perform a cache operation for the first cache-line
*/ */
start = start & ~(UNIPHIER_SSC_LINE_SIZE - 1); start = start & ~(UNIPHIER_SSC_LINE_SIZE - 1);
...@@ -89,15 +146,16 @@ static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation) ...@@ -89,15 +146,16 @@ static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation)
} }
/* /*
* If end address is not aligned to cache-line, * If the end address is not aligned,
* do cache operation for the last cache-line * perform a cache operation for the last cache-line
*/ */
size = ALIGN(size, UNIPHIER_SSC_LINE_SIZE); size = ALIGN(size, UNIPHIER_SSC_LINE_SIZE);
while (size) { while (size) {
u32 chunk_size = size > UNIPHIER_SSC_RANGE_OP_MAX_SIZE ? u32 chunk_size = min_t(u32, size, UNIPHIER_SSC_RANGE_OP_MAX_SIZE);
UNIPHIER_SSC_RANGE_OP_MAX_SIZE : size;
__uniphier_cache_maint_range(start, chunk_size, operation); uniphier_cache_maint_common(start, chunk_size, ways,
UNIPHIER_SSCOQM_S_RANGE | operation);
start += chunk_size; start += chunk_size;
size -= chunk_size; size -= chunk_size;
...@@ -106,17 +164,98 @@ static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation) ...@@ -106,17 +164,98 @@ static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation)
uniphier_cache_sync(); uniphier_cache_sync();
} }
void uniphier_cache_prefetch_range(u32 start, u32 end, u32 ways)
{
uniphier_cache_maint_range(start, end, ways,
UNIPHIER_SSCOQM_TID_WAY |
UNIPHIER_SSCOQM_CM_PREFETCH);
}
void uniphier_cache_touch_range(u32 start, u32 end, u32 ways)
{
uniphier_cache_maint_range(start, end, ways,
UNIPHIER_SSCOQM_TID_WAY |
UNIPHIER_SSCOQM_CM_TOUCH);
}
void uniphier_cache_touch_zero_range(u32 start, u32 end, u32 ways)
{
uniphier_cache_maint_range(start, end, ways,
UNIPHIER_SSCOQM_TID_WAY |
UNIPHIER_SSCOQM_CM_TOUCH_ZERO);
}
void uniphier_cache_inv_way(u32 ways)
{
uniphier_cache_maint_common(0, 0, ways,
UNIPHIER_SSCOQM_S_WAY |
UNIPHIER_SSCOQM_CM_INV);
}
void uniphier_cache_set_active_ways(int cpu, u32 active_ways)
{
void __iomem *base = (void __iomem *)UNIPHIER_SSCC + 0xc00;
switch (readl(UNIPHIER_SSCID)) { /* revision */
case 0x11: /* sLD3 */
base = (void __iomem *)UNIPHIER_SSCC + 0x870;
break;
case 0x12: /* LD4 */
case 0x16: /* sld8 */
base = (void __iomem *)UNIPHIER_SSCC + 0x840;
break;
default:
base = (void __iomem *)UNIPHIER_SSCC + 0xc00;
break;
}
writel(active_ways, base + 4 * cpu);
}
static void uniphier_cache_endisable(int enable)
{
u32 tmp;
tmp = readl(UNIPHIER_SSCC);
if (enable)
tmp |= UNIPHIER_SSCC_ON;
else
tmp &= ~UNIPHIER_SSCC_ON;
writel(tmp, UNIPHIER_SSCC);
}
void uniphier_cache_enable(void)
{
uniphier_cache_endisable(1);
}
void uniphier_cache_disable(void)
{
uniphier_cache_endisable(0);
}
#ifdef CONFIG_CACHE_UNIPHIER
void v7_outer_cache_flush_all(void)
{
uniphier_cache_maint_all(UNIPHIER_SSCOQM_CM_FLUSH);
}
void v7_outer_cache_inval_all(void)
{
uniphier_cache_maint_all(UNIPHIER_SSCOQM_CM_INV);
}
void v7_outer_cache_flush_range(u32 start, u32 end) void v7_outer_cache_flush_range(u32 start, u32 end)
{ {
uniphier_cache_maint_range(start, end, UNIPHIER_SSCOQM_CM_FLUSH); uniphier_cache_maint_range(start, end, 0, UNIPHIER_SSCOQM_CM_FLUSH);
} }
void v7_outer_cache_inval_range(u32 start, u32 end) void v7_outer_cache_inval_range(u32 start, u32 end)
{ {
if (start & (UNIPHIER_SSC_LINE_SIZE - 1)) { if (start & (UNIPHIER_SSC_LINE_SIZE - 1)) {
start &= ~(UNIPHIER_SSC_LINE_SIZE - 1); start &= ~(UNIPHIER_SSC_LINE_SIZE - 1);
__uniphier_cache_maint_range(start, UNIPHIER_SSC_LINE_SIZE, uniphier_cache_maint_range(start, UNIPHIER_SSC_LINE_SIZE, 0,
UNIPHIER_SSCOQM_CM_FLUSH); UNIPHIER_SSCOQM_CM_FLUSH);
start += UNIPHIER_SSC_LINE_SIZE; start += UNIPHIER_SSC_LINE_SIZE;
} }
...@@ -127,8 +266,8 @@ void v7_outer_cache_inval_range(u32 start, u32 end) ...@@ -127,8 +266,8 @@ void v7_outer_cache_inval_range(u32 start, u32 end)
if (end & (UNIPHIER_SSC_LINE_SIZE - 1)) { if (end & (UNIPHIER_SSC_LINE_SIZE - 1)) {
end &= ~(UNIPHIER_SSC_LINE_SIZE - 1); end &= ~(UNIPHIER_SSC_LINE_SIZE - 1);
__uniphier_cache_maint_range(end, UNIPHIER_SSC_LINE_SIZE, uniphier_cache_maint_range(end, UNIPHIER_SSC_LINE_SIZE, 0,
UNIPHIER_SSCOQM_CM_FLUSH); UNIPHIER_SSCOQM_CM_FLUSH);
} }
if (start >= end) { if (start >= end) {
...@@ -136,28 +275,20 @@ void v7_outer_cache_inval_range(u32 start, u32 end) ...@@ -136,28 +275,20 @@ void v7_outer_cache_inval_range(u32 start, u32 end)
return; return;
} }
uniphier_cache_maint_range(start, end, UNIPHIER_SSCOQM_CM_INV); uniphier_cache_maint_range(start, end, 0, UNIPHIER_SSCOQM_CM_INV);
} }
void v7_outer_cache_enable(void) void v7_outer_cache_enable(void)
{ {
u32 tmp; uniphier_cache_set_active_ways(0, U32_MAX); /* activate all ways */
uniphier_cache_enable();
writel(U32_MAX, UNIPHIER_SSCLPDAWCR); /* activate all ways */
tmp = readl(UNIPHIER_SSCC);
tmp |= UNIPHIER_SSCC_ON;
writel(tmp, UNIPHIER_SSCC);
} }
#endif
void v7_outer_cache_disable(void) void v7_outer_cache_disable(void)
{ {
u32 tmp; uniphier_cache_disable();
tmp = readl(UNIPHIER_SSCC);
tmp &= ~UNIPHIER_SSCC_ON;
writel(tmp, UNIPHIER_SSCC);
} }
#endif
void enable_caches(void) void enable_caches(void)
{ {
......
/*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CACHE_UNIPHIER_H
#define __CACHE_UNIPHIER_H
#include <linux/types.h>
void uniphier_cache_prefetch_range(u32 start, u32 end, u32 ways);
void uniphier_cache_touch_range(u32 start, u32 end, u32 ways);
void uniphier_cache_touch_zero_range(u32 start, u32 end, u32 ways);
void uniphier_cache_inv_way(u32 ways);
void uniphier_cache_set_active_ways(int cpu, u32 active_ways);
void uniphier_cache_enable(void);
void uniphier_cache_disable(void);
#endif /* __CACHE_UNIPHIER_H */
...@@ -5,14 +5,10 @@ ...@@ -5,14 +5,10 @@
* SPDX-License-Identifier: GPL-2.0+ * SPDX-License-Identifier: GPL-2.0+
*/ */
#include <config.h>
#include <linux/linkage.h> #include <linux/linkage.h>
#include "ssc-regs.h"
ENTRY(lowlevel_init) ENTRY(lowlevel_init)
ldr r1, = UNIPHIER_SSCC ldr sp, = CONFIG_SYS_INIT_SP_ADDR
ldr r0, [r1] b uniphier_cache_disable
bic r0, r0, #UNIPHIER_SSCC_ON @ L2 disable
str r0, [r1]
mov pc, lr
ENDPROC(lowlevel_init) ENDPROC(lowlevel_init)
...@@ -11,8 +11,6 @@ ...@@ -11,8 +11,6 @@
#include <linux/sizes.h> #include <linux/sizes.h>
#include <asm/system.h> #include <asm/system.h>
#include "ssc-regs.h"
ENTRY(lowlevel_init) ENTRY(lowlevel_init)
mov r8, lr @ persevere link reg across call mov r8, lr @ persevere link reg across call
...@@ -27,10 +25,6 @@ ENTRY(lowlevel_init) ...@@ -27,10 +25,6 @@ ENTRY(lowlevel_init)
orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache
mcr p15, 0, r0, c1, c0, 0 mcr p15, 0, r0, c1, c0, 0
#ifdef CONFIG_DEBUG_LL
bl debug_ll_init
#endif
bl setup_init_ram @ RAM area for stack and page table bl setup_init_ram @ RAM area for stack and page table
/* /*
...@@ -49,6 +43,10 @@ ENTRY(lowlevel_init) ...@@ -49,6 +43,10 @@ ENTRY(lowlevel_init)
bl enable_mmu bl enable_mmu
#ifdef CONFIG_DEBUG_LL
bl debug_ll_init
#endif
mov lr, r8 @ restore link mov lr, r8 @ restore link
mov pc, lr @ back to my caller mov pc, lr @ back to my caller
ENDPROC(lowlevel_init) ENDPROC(lowlevel_init)
...@@ -88,39 +86,42 @@ ENDPROC(enable_mmu) ...@@ -88,39 +86,42 @@ ENDPROC(enable_mmu)
*/ */
#define BOOT_RAM_SIZE (SZ_32K) #define BOOT_RAM_SIZE (SZ_32K)
#define BOOT_RAM_BASE ((CONFIG_SPL_STACK) - (BOOT_RAM_SIZE)) #define BOOT_RAM_BASE ((CONFIG_SPL_STACK) - (BOOT_RAM_SIZE))
#define BOOT_WAY_BITS (0x00000100) /* way 8 */ #define BOOT_RAM_WAYS (0x00000100) @ way 8
#define SSCO_BASE 0x506c0000
#define SSCOPE 0x244
#define SSCOQM 0x248
#define SSCOQAD 0x24c
#define SSCOQSZ 0x250
#define SSCOQWN 0x258
#define SSCOPPQSEF 0x25c
#define SSCOLPQS 0x260
ENTRY(setup_init_ram) ENTRY(setup_init_ram)
/* ldr r1, = SSCO_BASE
* Touch to zero for the boot way mrc p15, 0, r0, c2, c0, 0 @ TTBR0
*/ ldr r0, [r0, #0x400] @ entry for virtual address 0x100*****
0: bfc r0, #0, #20
/* cmp r0, #0x50000000 @ is sLD3 page table?
* set UNIPHIER_SSCOQM, UNIPHIER_SSCOQAD, UNIPHIER_SSCOQSZ, UNIPHIER_SSCOQWN in this order biceq r1, r1, #0xc0000000 @ sLD3 ROM maps 0x5******* to 0x1*******
*/
ldr r0, = 0x00408006 @ touch to zero with address range /* Touch to zero for the boot way */
ldr r1, = UNIPHIER_SSCOQM 0: ldr r0, = 0x00408006 @ touch to zero with address range
str r0, [r1] str r0, [r1, #SSCOQM]
ldr r0, = BOOT_RAM_BASE ldr r0, = BOOT_RAM_BASE
ldr r1, = UNIPHIER_SSCOQAD str r0, [r1, #SSCOQAD]
str r0, [r1]
ldr r0, = BOOT_RAM_SIZE ldr r0, = BOOT_RAM_SIZE
ldr r1, = UNIPHIER_SSCOQSZ str r0, [r1, #SSCOQSZ]
str r0, [r1] ldr r0, = BOOT_RAM_WAYS
ldr r0, = BOOT_WAY_BITS str r0, [r1, #SSCOQWN]
ldr r1, = UNIPHIER_SSCOQWN ldr r0, [r1, #SSCOPPQSEF]
str r0, [r1]
ldr r1, = UNIPHIER_SSCOPPQSEF
ldr r0, [r1]
cmp r0, #0 @ check if the command is successfully set cmp r0, #0 @ check if the command is successfully set
bne 0b @ try again if an error occurs bne 0b @ try again if an error occurs
ldr r1, = UNIPHIER_SSCOLPQS 1: ldr r0, [r1, #SSCOLPQS]
1: