Commit 29161f47 authored by Michael Schwingen's avatar Michael Schwingen Committed by Albert ARIBAUD

IXP42x PCI rewrite

clean up IXP PCI handling: get rid of IXP-private bus scan, BAR assign etc.
code and use u-boot's PCI infrastructure instead.  Move board-specific PCI
setup code (clock/reset) to board directory.
Signed-off-by: default avatarMichael Schwingen <michael@schwingen.org>
parent 904ec57b
......@@ -22,88 +22,21 @@
* MA 02111-1307 USA
*/
#ifndef _IXP425PCI_H_
#define _IXP425PCI_H_
#ifndef _IXP425PCI_H
#define _IXP425PCI_H
#define TRUE 1
#define FALSE 0
#define OK 0
#define ERROR -1
#define BOOL int
#define IXP425_PCI_MAX_BAR_PER_FUNC 6
#define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC * \
IXP425_PCI_MAX_FUNC_ON_BUS)
enum PciBarId
{
CSR_BAR=0,
IO_BAR,
SD_BAR,
NO_BAR
};
/*Base address register descriptor*/
typedef struct
{
unsigned int size;
unsigned int address;
} PciBar;
typedef struct
{
unsigned int bus;
unsigned int device;
unsigned int func;
unsigned int irq;
BOOL error;
unsigned short vendor_id;
unsigned short device_id;
/*We need an extra entry in this array for dummy placeholder*/
PciBar bar[IXP425_PCI_MAX_BAR_PER_FUNC + 1];
} PciDevice;
struct pci_controller;
extern void pci_ixp_init(struct pci_controller *hose);
/* Mask definitions*/
#define IXP425_PCI_TOP_WORD_OF_LONG_MASK 0xffff0000
#define IXP425_PCI_TOP_BYTE_OF_LONG_MASK 0xff000000
#define IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK 0x0000ffff
#define IXP425_PCI_BOTTOM_TRIBYTES_OF_LONG_MASK 0x00ffffff
#define IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK 0x0000000f
#define IXP425_PCI_MAX_UINT32 0xffffffff
#define IXP425_PCI_BAR_QUERY 0xffffffff
#define IXP425_PCI_BAR_MEM_BASE 0x100000
#define IXP425_PCI_BAR_IO_BASE 0x000000
/*define the maximum number of bus segments - we support a single segment*/
#define IXP425_PCI_MAX_BUS 1
/*define the maximum number of cards per bus segment*/
#define IXP425_PCI_MAX_DEV 4
/*define the maximum number of functions per device*/
#define IXP425_PCI_MAX_FUNC 8
/* define the maximum number of separate functions that we can
potentially have on the bus*/
#define IXP425_PCI_MAX_FUNC_ON_BUS (1+ IXP425_PCI_MAX_FUNC * \
IXP425_PCI_MAX_DEV * \
IXP425_PCI_MAX_BUS)
/*define the maximum number of BARs per function*/
#define IXP425_PCI_MAX_BAR_PER_FUNC 6
#define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC * \
IXP425_PCI_MAX_FUNC_ON_BUS)
#define PCI_NP_CBE_BESL (4)
#define PCI_NP_AD_FUNCSL (8)
#define REG_WRITE(b,o,v) (*(volatile unsigned int*)((b+o))=(v))
#define REG_READ(b,o,v) ((v)=(*(volatile unsigned int*)((b+o))))
#define PCI_DELAY 500
#define USEC_LOOP_COUNT 533
#define PCI_SETTLE_USEC 200
#define PCI_MIN_RESET_ASSERT_USEC 2000
/*Register addressing definitions for PCI controller configuration
and status registers*/
......@@ -150,28 +83,6 @@ typedef struct
#define NP_CMD_CONFIGWRITE (0xb)
*/
/*define the default setting of the AHB memory base reg*/
#define IXP425_PCI_AHBMEMBASE_DEFAULT 0x00010203
#define IXP425_PCI_AHBIOBASE_DEFAULT 0x0
#define IXP425_PCI_PCIMEMBASE_DEFAULT 0x0
/*define the default settings for the controller's BARs*/
#ifdef IXP425_PCI_SIMPLE_MAPPING
#define IXP425_PCI_BAR_0_DEFAULT 0x00000000
#define IXP425_PCI_BAR_1_DEFAULT 0x01000000
#define IXP425_PCI_BAR_2_DEFAULT 0x02000000
#define IXP425_PCI_BAR_3_DEFAULT 0x03000000
#define IXP425_PCI_BAR_4_DEFAULT 0x00000000
#define IXP425_PCI_BAR_5_DEFAULT 0x00000000
#else
#define IXP425_PCI_BAR_0_DEFAULT 0x40000000
#define IXP425_PCI_BAR_1_DEFAULT 0x41000000
#define IXP425_PCI_BAR_2_DEFAULT 0x42000000
#define IXP425_PCI_BAR_3_DEFAULT 0x43000000
#define IXP425_PCI_BAR_4_DEFAULT 0x00000000
#define IXP425_PCI_BAR_5_DEFAULT 0x00000000
#endif
/*Configuration Port register bit definitions*/
#define PCI_CRP_WRITE BIT(16)
......@@ -228,17 +139,6 @@ typedef struct
#define PCI_CFG_SPECIAL_USE 0x41
#define PCI_CFG_MODE 0x43
/*Specify the initial command we send to PCI devices*/
#define INITIAL_PCI_CMD (PCI_CMD_IO_ENABLE \
| PCI_CMD_MEM_ENABLE \
| PCI_CMD_MASTER_ENABLE \
| PCI_CMD_WI_ENABLE)
/*define the sub vendor and subsystem to be used */
#define IXP425_PCI_SUB_VENDOR_SYSTEM 0x00000000
#define PCI_IRQ_LINES 4
#define PCI_CMD_IO_ENABLE 0x0001 /* IO access enable */
#define PCI_CMD_MEM_ENABLE 0x0002 /* memory access enable */
#define PCI_CMD_MASTER_ENABLE 0x0004 /* bus master enable */
......@@ -287,26 +187,4 @@ typedef struct
#define PCI_DMACTRL_PADC1 BIT(14)
#define PCI_DMACTRL_PADE1 BIT(15)
/* GPIO related register */
#undef IXP425_GPIO_GPOUTR
#undef IXP425_GPIO_GPOER
#undef IXP425_GPIO_GPINR
#undef IXP425_GPIO_GPISR
#undef IXP425_GPIO_GPIT1R
#undef IXP425_GPIO_GPIT2R
#undef IXP425_GPIO_GPCLKR
#define IXP425_GPIO_GPOUTR 0xC8004000
#define IXP425_GPIO_GPOER 0xC8004004
#define IXP425_GPIO_GPINR 0xC8004008
#define IXP425_GPIO_GPISR 0xC800400C
#define IXP425_GPIO_GPIT1R 0xC8004010
#define IXP425_GPIO_GPIT2R 0xC8004014
#define IXP425_GPIO_GPCLKR 0xC8004018
#define READ_GPIO_REG(addr,val) \
(val) = *((volatile int *)(addr));
#define WRITE_GPIO_REG(addr,val) \
*((volatile int *)(addr)) = (val);
#endif
......@@ -50,7 +50,6 @@ PCI_HOSE_OP(write, byte, u8)
PCI_HOSE_OP(write, word, u16)
PCI_HOSE_OP(write, dword, u32)
#ifndef CONFIG_IXP425
#define PCI_OP(rw, size, type, error_code) \
int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
{ \
......@@ -71,7 +70,6 @@ PCI_OP(read, dword, u32 *, *value = 0xffffffff)
PCI_OP(write, byte, u8, )
PCI_OP(write, word, u16, )
PCI_OP(write, dword, u32, )
#endif /* CONFIG_IXP425 */
#define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
......@@ -190,7 +188,6 @@ int pci_last_busno(void)
return hose->last_busno;
}
#ifndef CONFIG_IXP425
pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
{
struct pci_controller * hose;
......@@ -246,7 +243,6 @@ pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
return (-1);
}
#endif /* CONFIG_IXP425 */
pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
{
......
......@@ -11,7 +11,7 @@
#include <common.h>
#if (!defined(__I386__) && !defined(CONFIG_IXDP425))
#if !defined(__I386__)
#include <asm/processor.h>
#include <asm/io.h>
......@@ -20,15 +20,6 @@
#define cfg_read(val, addr, type, op) *val = op((type)(addr))
#define cfg_write(val, addr, type, op) op((type *)(addr), (val))
#ifdef CONFIG_IXP425
extern unsigned char in_8 (volatile unsigned *addr);
extern unsigned short in_le16 (volatile unsigned *addr);
extern unsigned in_le32 (volatile unsigned *addr);
extern void out_8 (volatile unsigned *addr, char val);
extern void out_le16 (volatile unsigned *addr, unsigned short val);
extern void out_le32 (volatile unsigned *addr, unsigned int val);
#endif /* CONFIG_IXP425 */
#if defined(CONFIG_MPC8260)
#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
static int \
......@@ -134,4 +125,4 @@ void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
hose->cfg_data = (unsigned char *) cfg_data;
}
#endif /* !__I386__ && !CONFIG_IXDP425 */
#endif /* !__I386__ */
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