Commit 297a6587 authored by Stefan Roese's avatar Stefan Roese Committed by Tom Rix
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ppc4xx: Big cleanup of PPC4xx defines



This patch cleans up multiple issues of the 4xx register (mostly
DCR, SDR, CPR, etc) definitions:

- Change lower case defines to upper case (plb4_acr -> PLB4_ACR)
- Change the defines to better match the names from the
  user's manuals (e.g. cprpllc -> CPR0_PLLC)
- Removal of some unused defines

Please test this patch intensive on your PPC4xx platform. Even though
I tried not to break anything and tested successfully on multiple
4xx AMCC platforms, testing on custom platforms is recommended.
Signed-off-by: default avatarStefan Roese <sr@denx.de>
parent e35c73d7
......@@ -57,7 +57,7 @@ int board_early_init_f(void)
#if !defined(CONFIG_NAND_U_BOOT)
/* don't reinit PLL when booting via I2C bootstrap option */
mfsdr(SDR_PINSTP, reg);
mfsdr(SDR0_PINSTP, reg);
if (reg != 0xf0000000)
board_pll_init_f();
#endif
......@@ -65,18 +65,18 @@ int board_early_init_f(void)
acadia_gpio_init();
/* Configure 405EZ for NAND usage */
mtsdr(sdrnand0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN);
mfsdr(sdrultra0, reg);
mtsdr(SDR0_NAND0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN);
mfsdr(SDR0_ULTRA0, reg);
reg &= ~SDR_ULTRA0_CSN_MASK;
reg |= (SDR_ULTRA0_CSNSEL0 >> CONFIG_SYS_NAND_CS) |
SDR_ULTRA0_NDGPIOBP |
SDR_ULTRA0_EBCRDYEN |
SDR_ULTRA0_NFSRSTEN;
mtsdr(sdrultra0, reg);
mtsdr(SDR0_ULTRA0, reg);
/* USB Host core needs this bit set */
mfsdr(sdrultra1, reg);
mtsdr(sdrultra1, reg | SDR_ULTRA1_LEDNENABLE);
mfsdr(SDR0_ULTRA1, reg);
mtsdr(SDR0_ULTRA1, reg | SDR_ULTRA1_LEDNENABLE);
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
......
......@@ -65,7 +65,7 @@ phys_size_t initdram(int board_type)
u32 reg;
/* don't reinit PLL when booting via I2C bootstrap option */
mfsdr(SDR_PINSTP, reg);
mfsdr(SDR0_PINSTP, reg);
if (reg != 0xf0000000)
board_pll_init_f();
#endif
......@@ -81,25 +81,25 @@ phys_size_t initdram(int board_type)
gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
/* 2. EBC in Async mode */
mtebc(pb1ap, 0x078F1EC0);
mtebc(pb2ap, 0x078F1EC0);
mtebc(pb1cr, 0x000BC000);
mtebc(pb2cr, 0x020BC000);
mtebc(PB1AP, 0x078F1EC0);
mtebc(PB2AP, 0x078F1EC0);
mtebc(PB1CR, 0x000BC000);
mtebc(PB2CR, 0x020BC000);
/* 3. Set CRAM in Sync mode */
cram_bcr_write(0x7012); /* CRAM burst setting */
/* 4. EBC in Sync mode */
mtebc(pb1ap, 0x9C0201C0);
mtebc(pb2ap, 0x9C0201C0);
mtebc(PB1AP, 0x9C0201C0);
mtebc(PB2AP, 0x9C0201C0);
/* Set GPIO pins back to alternate function */
gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
/* Config EBC to use RDY */
mfsdr(sdrultra0, val);
mtsdr(sdrultra0, val | SDR_ULTRA0_EBCRDYEN);
mfsdr(SDR0_ULTRA0, val);
mtsdr(SDR0_ULTRA0, val | SDR_ULTRA0_EBCRDYEN);
/* Wait a short while, since for NAND booting this is too fast */
for (i=0; i<200000; i++)
......
......@@ -51,11 +51,11 @@ void board_pll_init_f(void)
*/
/* Initialize PLL */
mtcpr(cprpllc, 0x0000033c);
mtcpr(cprplld, 0x0c010200);
mtcpr(cprprimad, 0x04060c0c);
mtcpr(cprperd0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */
mtcpr(cprclkupd, 0x40000000);
mtcpr(CPR0_PLLC, 0x0000033c);
mtcpr(CPR0_PLLD, 0x0c010200);
mtcpr(CPC0_PRIMAD, 0x04060c0c);
mtcpr(CPC0_PERD0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */
mtcpr(CPR0_CLKUP, 0x40000000);
}
#elif defined(PLLMR0_266_160_80)
......@@ -83,13 +83,13 @@ void board_pll_init_f(void)
*/
/* Initialize PLL */
mtcpr(cprpllc, 0x20000238);
mtcpr(cprplld, 0x03010400);
mtcpr(cprprimad, 0x03050a0a);
mtcpr(cprperc0, 0x00000000);
mtcpr(cprperd0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */
mtcpr(cprperd1, 0x07323200);
mtcpr(cprclkupd, 0x40000000);
mtcpr(CPR0_PLLC, 0x20000238);
mtcpr(CPR0_PLLD, 0x03010400);
mtcpr(CPC0_PRIMAD, 0x03050a0a);
mtcpr(CPC0_PERC0, 0x00000000);
mtcpr(CPC0_PERD0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */
mtcpr(CPC0_PERD1, 0x07323200);
mtcpr(CPR0_CLKUP, 0x40000000);
}
#elif defined(PLLMR0_333_166_83)
......@@ -117,12 +117,12 @@ void board_pll_init_f(void)
*/
/* Initialize PLL */
mtcpr(cprpllc, 0x0000033C);
mtcpr(cprplld, 0x0a010000);
mtcpr(cprprimad, 0x02040808);
mtcpr(cprperd0, 0x02080505); /* SPI clk div. eq. OPB clk div. */
mtcpr(cprperd1, 0xA6A60300);
mtcpr(cprclkupd, 0x40000000);
mtcpr(CPR0_PLLC, 0x0000033C);
mtcpr(CPR0_PLLD, 0x0a010000);
mtcpr(CPC0_PRIMAD, 0x02040808);
mtcpr(CPC0_PERD0, 0x02080505); /* SPI clk div. eq. OPB clk div. */
mtcpr(CPC0_PERD1, 0xA6A60300);
mtcpr(CPR0_CLKUP, 0x40000000);
}
#elif defined(PLLMR0_100_100_12)
......@@ -143,12 +143,12 @@ void board_pll_init_f(void)
*/
/* Initialize PLL */
mtcpr(cprpllc, 0x000003BC);
mtcpr(cprplld, 0x06060600);
mtcpr(cprprimad, 0x02020004);
mtcpr(cprperd0, 0x04002828); /* SPI clk div. eq. OPB clk div. */
mtcpr(cprperd1, 0xC8C81600);
mtcpr(cprclkupd, 0x40000000);
mtcpr(CPR0_PLLC, 0x000003BC);
mtcpr(CPR0_PLLD, 0x06060600);
mtcpr(CPC0_PRIMAD, 0x02020004);
mtcpr(CPC0_PERD0, 0x04002828); /* SPI clk div. eq. OPB clk div. */
mtcpr(CPC0_PERD1, 0xC8C81600);
mtcpr(CPR0_CLKUP, 0x40000000);
}
#endif /* CPU_<speed>_405EZ */
......@@ -167,12 +167,12 @@ unsigned long get_tbclk(void)
/*
* Read PLL Mode registers
*/
mfcpr(cprplld, cpr_plld);
mfcpr(CPR0_PLLD, cpr_plld);
/*
* Read CPR_PRIMAD register
*/
mfcpr(cprprimad, cpr_primad);
mfcpr(CPC0_PRIMAD, cpr_primad);
/*
* Determine CPU clock frequency
......
......@@ -487,35 +487,35 @@ int pci_pre_init(struct pci_controller *hose)
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
+-------------------------------------------------------------------------*/
mfsdr(sdr_amp1, addr);
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb3_acr);
mtdcr(plb3_acr, addr | 0x80000000);
mfsdr(SD0_AMP1, addr);
mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB3_ACR);
mtdcr(PLB3_ACR, addr | 0x80000000);
/*-------------------------------------------------------------------------+
| Set priority for all PLB4 devices to 0.
+-------------------------------------------------------------------------*/
mfsdr(sdr_amp0, addr);
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
mtdcr(plb4_acr, addr);
mfsdr(SD0_AMP0, addr);
mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */
mtdcr(PLB4_ACR, addr);
/*-------------------------------------------------------------------------+
| Set Nebula PLB4 arbiter to fair mode.
+-------------------------------------------------------------------------*/
/* Segment0 */
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
mtdcr(plb0_acr, addr);
addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR;
addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED;
addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP;
addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP;
mtdcr(PLB0_ACR, addr);
/* Segment1 */
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
mtdcr(plb1_acr, addr);
addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR;
addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED;
addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP;
addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP;
mtdcr(PLB1_ACR, addr);
return 1;
}
......@@ -695,8 +695,8 @@ void ext_bus_cntlr_init(void)
|
+-------------------------------------------------------------------------*/
/* NVRAM - FPGA */
mtebc(pb5ap, EBC0_BNAP_NVRAM_FPGA);
mtebc(pb5cr, EBC0_BNCR_NVRAM_FPGA_CS5);
mtebc(PB5AP, EBC0_BNAP_NVRAM_FPGA);
mtebc(PB5CR, EBC0_BNCR_NVRAM_FPGA_CS5);
/*-------------------------------------------------------------------------+
|
......@@ -749,7 +749,7 @@ void ext_bus_cntlr_init(void)
case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
/* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
/* Read Serial Device Strap Register1 in PPC440EP */
mfsdr(sdr_sdstp1, sdr0_sdstp1);
mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
......@@ -822,7 +822,7 @@ void ext_bus_cntlr_init(void)
/* Default Strap Settings 5-7 */
/* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
/* Read Serial Device Strap Register1 in PPC440EP */
mfsdr(sdr_sdstp1, sdr0_sdstp1);
mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
......@@ -1013,8 +1013,8 @@ void ext_bus_cntlr_init(void)
/*-------------------------------------------------------------------------+
| Initialize EBC CONFIG
+-------------------------------------------------------------------------*/
mtdcr(ebccfga, xbcfg);
mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN |
mtdcr(EBC0_CFGADDR, EBC0_CFG);
mtdcr(EBC0_CFGDATA, EBC0_CFG_EBTC_DRIVEN |
EBC0_CFG_PTD_ENABLED |
EBC0_CFG_RTC_2048PERCLK |
EBC0_CFG_EMPL_LOW |
......@@ -1029,20 +1029,20 @@ void ext_bus_cntlr_init(void)
| Initialize EBC Bank 0-4
+-------------------------------------------------------------------------*/
/* EBC Bank0 */
mtebc(pb0ap, ebc0_cs0_bnap_value);
mtebc(pb0cr, ebc0_cs0_bncr_value);
mtebc(PB0AP, ebc0_cs0_bnap_value);
mtebc(PB0CR, ebc0_cs0_bncr_value);
/* EBC Bank1 */
mtebc(pb1ap, ebc0_cs1_bnap_value);
mtebc(pb1cr, ebc0_cs1_bncr_value);
mtebc(PB1AP, ebc0_cs1_bnap_value);
mtebc(PB1CR, ebc0_cs1_bncr_value);
/* EBC Bank2 */
mtebc(pb2ap, ebc0_cs2_bnap_value);
mtebc(pb2cr, ebc0_cs2_bncr_value);
mtebc(PB2AP, ebc0_cs2_bnap_value);
mtebc(PB2CR, ebc0_cs2_bncr_value);
/* EBC Bank3 */
mtebc(pb3ap, ebc0_cs3_bnap_value);
mtebc(pb3cr, ebc0_cs3_bncr_value);
mtebc(PB3AP, ebc0_cs3_bnap_value);
mtebc(PB3CR, ebc0_cs3_bncr_value);
/* EBC Bank4 */
mtebc(pb4ap, ebc0_cs4_bnap_value);
mtebc(pb4cr, ebc0_cs4_bncr_value);
mtebc(PB4AP, ebc0_cs4_bnap_value);
mtebc(PB4CR, ebc0_cs4_bncr_value);
return;
}
......@@ -1939,10 +1939,10 @@ void configure_ppc440ep_pins(void)
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
mfsdr(sdr_usb0, sdr0_usb0);
mfsdr(SDR0_USB0, sdr0_usb0);
sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
mtsdr(sdr_usb0, sdr0_usb0);
mtsdr(SDR0_USB0, sdr0_usb0);
usb2_device_selection_in_fpga();
}
......@@ -1950,19 +1950,19 @@ void configure_ppc440ep_pins(void)
/* USB1.1 Device Selection */
if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
{
mfsdr(sdr_usb0, sdr0_usb0);
mfsdr(SDR0_USB0, sdr0_usb0);
sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
mtsdr(sdr_usb0, sdr0_usb0);
mtsdr(SDR0_USB0, sdr0_usb0);
}
/* USB1.1 Host Selection */
if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
{
mfsdr(sdr_usb0, sdr0_usb0);
mfsdr(SDR0_USB0, sdr0_usb0);
sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
mtsdr(sdr_usb0, sdr0_usb0);
mtsdr(SDR0_USB0, sdr0_usb0);
}
/* NAND Flash Selection */
......@@ -1971,14 +1971,14 @@ void configure_ppc440ep_pins(void)
update_ndfc_ios(gpio_tab);
#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL |
mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
SDR0_CUST0_NDFC_ENABLE |
SDR0_CUST0_NDFC_BW_8_BIT |
SDR0_CUST0_NDFC_ARE_MASK |
SDR0_CUST0_CHIPSELGAT_EN1 |
SDR0_CUST0_CHIPSELGAT_EN2);
#else
mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL |
mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL |
SDR0_CUST0_NDFC_ENABLE |
SDR0_CUST0_NDFC_BW_8_BIT |
SDR0_CUST0_NDFC_ARE_MASK |
......@@ -1991,16 +1991,16 @@ void configure_ppc440ep_pins(void)
else
{
/* Set Mux on EMAC */
mtsdr(sdr_cust0, SDR0_CUST0_MUX_EMAC_SEL);
mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_EMAC_SEL);
}
/* MII Selection */
if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
{
update_zii_ios(gpio_tab);
mfsdr(sdr_mfr, sdr0_mfr);
mfsdr(SDR0_MFR, sdr0_mfr);
sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
mtsdr(sdr_mfr, sdr0_mfr);
mtsdr(SDR0_MFR, sdr0_mfr);
set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
}
......@@ -2009,9 +2009,9 @@ void configure_ppc440ep_pins(void)
if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
{
update_zii_ios(gpio_tab);
mfsdr(sdr_mfr, sdr0_mfr);
mfsdr(SDR0_MFR, sdr0_mfr);
sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
mtsdr(sdr_mfr, sdr0_mfr);
mtsdr(SDR0_MFR, sdr0_mfr);
set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
}
......@@ -2020,9 +2020,9 @@ void configure_ppc440ep_pins(void)
if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
{
update_zii_ios(gpio_tab);
mfsdr(sdr_mfr, sdr0_mfr);
mfsdr(SDR0_MFR, sdr0_mfr);
sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
mtsdr(sdr_mfr, sdr0_mfr);
mtsdr(SDR0_MFR, sdr0_mfr);
set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
}
......@@ -2071,13 +2071,13 @@ void configure_ppc440ep_pins(void)
/* Packet Reject Function Enable */
if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
{
mfsdr(sdr_mfr, sdr0_mfr);
mfsdr(SDR0_MFR, sdr0_mfr);
sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
mtsdr(sdr_mfr, sdr0_mfr);
mtsdr(SDR0_MFR, sdr0_mfr);
}
/* Perform effective access to hardware */
mtsdr(sdr_pfc1, sdr0_pfc1);
mtsdr(SDR0_PFC1, sdr0_pfc1);
set_chip_gpio_configuration(GPIO0, gpio_tab);
set_chip_gpio_configuration(GPIO1, gpio_tab);
......
......@@ -94,7 +94,7 @@ unsigned long flash_init(void)
* Boot Settings in IIC EEprom address 0xA8 or 0xA4
* Read Serial Device Strap Register1 in PPC440EP
*/
mfsdr(sdr_sdstp1, val);
mfsdr(SDR0_SDSTP1, val);
boot_selection = val & SDR0_SDSTP1_BOOT_SEL_MASK;
ebc_boot_size = val & SDR0_SDSTP1_EBC_ROM_BS_MASK;
......
......@@ -41,9 +41,9 @@ int board_early_init_f(void)
* and enable the internal PCI arbiter if selected
*/
if (in_8((void *)FPGA_REG1) & FPGA_REG1_PCI_INT_ARB)
mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
mtdcr(CPC0_PCI, CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
else
mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN);
mtdcr(CPC0_PCI, CPC0_PCI_HOST_CFG_EN);
return 0;
}
......
......@@ -106,25 +106,25 @@ unsigned long flash_init(void)
/* Re-do sizing to get full correct info */
if (size_b1) {
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
mtdcr(EBC0_CFGADDR, PB0CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB0CR);
base_b1 = -size_b1;
pbcr = (pbcr & 0x0001ffff) | base_b1 |
(((size_b1 / 1024 / 1024) - 1) << 17);
mtdcr(ebccfgd, pbcr);
/* printf("pb1cr = %x\n", pbcr); */
mtdcr(EBC0_CFGDATA, pbcr);
/* printf("PB1CR = %x\n", pbcr); */
}
if (size_b0) {
mtdcr(ebccfga, pb1cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb1cr);
mtdcr(EBC0_CFGADDR, PB1CR);
pbcr = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGADDR, PB1CR);
base_b0 = base_b1 - size_b0;
pbcr = (pbcr & 0x0001ffff) | base_b0 |
(((size_b0 / 1024 / 1024) - 1) << 17);
mtdcr(ebccfgd, pbcr);
/* printf("pb0cr = %x\n", pbcr); */
mtdcr(EBC0_CFGDATA, pbcr);
/* printf("PB0CR = %x\n", pbcr); */
}
size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]);
......
......@@ -475,9 +475,9 @@ int board_early_init_r (void)
/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
mtebc(pb3cr, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
mtebc(PB3CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
#else
mtebc(pb0cr, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
#endif
/* Remove TLB entry of boot EBC mapping */
......
......@@ -41,30 +41,30 @@ int board_early_init_f(void)
/*--------------------------------------------------------------------
* Setup the external bus controller/chip selects
*-------------------------------------------------------------------*/
mtdcr(ebccfga, xbcfg);
reg = mfdcr(ebccfgd);
mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
mtdcr(EBC0_CFGADDR, EBC0_CFG);
reg = mfdcr(EBC0_CFGDATA);
mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */
mtebc(pb1ap, 0x02815480); /* NVRAM/RTC */
mtebc(pb1cr, 0x48018000); /* BA=0x480 1MB R/W 8-bit */
mtebc(pb7ap, 0x01015280); /* FPGA registers */
mtebc(pb7cr, 0x48318000); /* BA=0x483 1MB R/W 8-bit */
mtebc(PB1AP, 0x02815480); /* NVRAM/RTC */
mtebc(PB1CR, 0x48018000); /* BA=0x480 1MB R/W 8-bit */
mtebc(PB7AP, 0x01015280); /* FPGA registers */
mtebc(PB7CR, 0x48318000); /* BA=0x483 1MB R/W 8-bit */
/* read FPGA_REG0 and set the bus controller */
status = *fpga_base;
if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) {
mtebc(pb0ap, 0x9b015480); /* FLASH/SRAM */
mtebc(pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
mtebc(pb2ap, 0x9b015480); /* 4MB FLASH */
mtebc(pb2cr, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */
mtebc(PB0AP, 0x9b015480); /* FLASH/SRAM */
mtebc(PB0CR, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
mtebc(PB2AP, 0x9b015480); /* 4MB FLASH */
mtebc(PB2CR, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */
} else {
mtebc(pb0ap, 0x9b015480); /* 4MB FLASH */
mtebc(pb0cr, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */
mtebc(PB0AP, 0x9b015480); /* 4MB FLASH */
mtebc(PB0CR, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */
/* set CS2 if FLASH_ONBD_N == 0 */
if (!(status & FLASH_ONBD_N)) {
mtebc(pb2ap, 0x9b015480); /* FLASH/SRAM */
mtebc(pb2cr, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */
mtebc(PB2AP, 0x9b015480); /* FLASH/SRAM */
mtebc(PB2CR, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */
}
}
......@@ -186,7 +186,7 @@ int pci_pre_init(struct pci_controller *hose)
* The ebony board is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
strap = mfdcr(cpc0_strp1);
strap = mfdcr(CPC0_STRP1);
if ((strap & 0x00100000) == 0) {
printf("PCI: CPC0_STRP1[PAE] not set.\n");
return 0;
......
......@@ -220,9 +220,9 @@ int board_early_init_f (void)
mtdcr (uic0sr, 0x00000000); /* clear all interrupts*/
mtdcr (uic0sr, 0xffffffff); /* clear all interrupts*/
mfsdr(sdr_mfr, mfr);
mfsdr(SDR0_MFR, mfr);
mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
mtsdr(sdr_mfr, mfr);
mtsdr(SDR0_MFR, mfr);
mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0);
......@@ -280,7 +280,7 @@ int pci_pre_init(struct pci_controller * hose )
* The katmai board is always configured as the host & requires the
* PCI arbiter to be enabled.
*-------------------------------------------------------------------*/
mfsdr(sdr_sdstp1, strap);
mfsdr(SDR0_SDSTP1, strap);
if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
return 0;
......
......@@ -42,12 +42,12 @@ int board_early_init_f(void)
{
u32 mfr;
mtebc( pb0ap, 0x03800000 ); /* set chip selects */
mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
mtebc( pb1ap, 0x03800000 );
mtebc( pb1cr, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */
mtebc( pb2ap, 0x03800000 );
mtebc( pb2cr, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */
mtebc( PB0AP, 0x03800000 ); /* set chip selects */
mtebc( PB0CR, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
mtebc( PB1AP, 0x03800000 );
mtebc( PB1CR, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */
mtebc( PB2AP, 0x03800000 );
mtebc( PB2CR, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */
mtdcr( uic1sr, 0xffffffff ); /* Clear all interrupts */
mtdcr( uic1er, 0x00000000 ); /* disable all interrupts */
......@@ -67,9 +67,9 @@ int board_early_init_f(void)
mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */
mtdcr( uic0sr, 0xffffffff );
mfsdr(sdr_mfr, mfr);
mfsdr(SDR0_MFR, mfr);
mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
mtsdr(sdr_mfr, mfr);
mtsdr(SDR0_MFR, mfr);
return 0;
}
......@@ -147,7 +147,7 @@ int pci_pre_init( struct pci_controller *hose )
* The luan board is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
mfsdr(sdr_sdstp1, strap);