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Commit 2c78febd authored by Wolfgang Denk's avatar Wolfgang Denk
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Merge branch 'master' of git://www.denx.de/git/u-boot-coldfire

parents 34e6cb8d 9b46432f
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CREDITS
View file @ 2c78febd
......@@ -435,6 +435,7 @@ D: Support for EP82xxM
N: Art Shipkowski
E: art@videon-central.com
D: Support for NetSilicon NS7520
D: Support for ColdFire MCF5275
N: Michal Simek
E: monstr@monstr.eu
......
MAINTAINERS
View file @ 2c78febd
......@@ -655,10 +655,6 @@ Matthias Fuchs <matthias.fuchs@esd-electronics.com>
TASREG MCF5249
Zachary P. Landau <zachary.landau@labxtechnologies.com>
r5200 mcf52x2
TsiChung Liew <Tsi-Chung.Liew@freescale.com>
M52277EVB mcf5227x
......
MAKEALL
View file @ 2c78febd
......@@ -665,13 +665,13 @@ LIST_coldfire=" \
M5253EVB \
M5271EVB \
M5272C3 \
M5275EVB \
M5282EVB \
M5329AFEE \
M5373EVB \
M54455EVB \
M5475AFE \
M5485AFE \
r5200 \
TASREG \
"
......
Makefile
View file @ 2c78febd
......@@ -1824,15 +1824,15 @@ M5271EVB_config : unconfig
M5272C3_config : unconfig
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5272c3
M5275EVB_config : unconfig
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5275evb freescale
M5282EVB_config : unconfig
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 m5282evb
TASREG_config : unconfig
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 tasreg esd
r5200_config : unconfig
@$(MKCONFIG) $(@:_config=) m68k mcf52x2 r5200
M5329AFEE_config \
M5329BFEE_config : unconfig
@case "$@" in \
......
board/r5200/Makefile → board/freescale/m5275evb/Makefile
View file @ 2c78febd
#
# (C) Copyright 2000-2006
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
......@@ -23,22 +23,18 @@
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
LIB = lib$(BOARD).a
COBJS = $(BOARD).o mii.o
OBJS = $(BOARD).o mii.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude $(obj).depend
sinclude .depend
#########################################################################
board/r5200/config.mk → board/freescale/m5275evb/config.mk
View file @ 2c78febd
......@@ -22,4 +22,4 @@
# MA 02111-1307 USA
#
TEXT_BASE = 0x10000000
TEXT_BASE = 0xffe00000
board/r5200/r5200.c → board/freescale/m5275evb/m5275evb.c
View file @ 2c78febd
......@@ -2,6 +2,8 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2005-2008 Arthur Shipkowski (art@videon-central.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
......@@ -22,103 +24,89 @@
*/
#include <common.h>
#include <asm/m5271.h>
#include <asm/immap_5271.h>
#include <asm/immap.h>
#define PERIOD 13 /* system bus period in ns */
#define SDRAM_TREFI 7800 /* in ns */
int checkboard (void) {
puts ("Board: R5200 Ethernet Module\n");
int checkboard(void)
{
puts("Board: ");
puts("Freescale MCF5275 EVB\n");
return 0;
};
long int initdram (int board_type) {
int i;
/*
* Set CS2 pin to be SD_CS0
*/
mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS)
| MCF_GPIO_PAR_CS_PAR_CS2);
mbar_writeByte(MCF_GPIO_PAR_SDRAM, mbar_readByte(MCF_GPIO_PAR_SDRAM)
| MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(0x01));
/*
* Check to see if the SDRAM has already been initialized
* by a run control tool
*/
if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) {
/*
* Initialize DRAM Control Register: DCR
*/
mbar_writeShort(MCF_SDRAMC_DCR, MCF_SDRAMC_DCR_RTIM(0x01)
| MCF_SDRAMC_DCR_RC(0x30));
/*
* Initialize DACR0
*/
mbar_writeLong(MCF_SDRAMC_DACR0,
MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18)
| MCF_SDRAMC_DACRn_CASL(0)
| MCF_SDRAMC_DACRn_CBM(3)
| MCF_SDRAMC_DACRn_PS(2));
/*
* Initialize DMR0
*/
mbar_writeLong(MCF_SDRAMC_DMR0,
MCF_SDRAMC_DMRn_BAM_8M
| MCF_SDRAMC_DMRn_V);
/*
* Set IP bit in DACR
*/
mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
| MCF_SDRAMC_DACRn_IP);
/*
* Wait at least 20ns to allow banks to precharge
*/
for (i = 0; i < 5; i++)
asm(" nop");
/*
* Write to this block to initiate precharge
*/
*(u16 *)(CFG_SDRAM_BASE) = 0x9696;
/*
* Set RE bit in DACR
*/
mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
| MCF_SDRAMC_DACRn_RE);
/*
* Wait for at least 8 auto refresh cycles to occur
*/
for (i = 0; i < 2000; i++)
asm(" nop");
/*
* Finish the configuration by issuing the MRS.
*/
mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
| MCF_SDRAMC_DACRn_MRS);
/*
* Write to the SDRAM Mode Register
*/
*(u16 *)(CFG_SDRAM_BASE + 0x1000) = 0x9696;
}
long int initdram(int board_type)
{
volatile sdramctrl_t *sdp = (sdramctrl_t *)(MMAP_SDRAM);
volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
gpio_reg->par_sdram = 0x3FF; /* Enable SDRAM */
/* Set up chip select */
sdp->sdbar0 = CFG_SDRAM_BASE;
sdp->sdbmr0 = MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V;
/* Set up timing */
sdp->sdcfg1 = 0x83711630;
sdp->sdcfg2 = 0x46770000;
/* Enable clock */
sdp->sdcr = MCF_SDRAMC_SDCR_MODE_EN | MCF_SDRAMC_SDCR_CKE;
/* Set precharge */
sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL;
/* Dummy write to start SDRAM */
*((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
/* Send LEMR */
sdp->sdmr = MCF_SDRAMC_SDMR_BNKAD_LEMR
| MCF_SDRAMC_SDMR_AD(0x0)
| MCF_SDRAMC_SDMR_CMD;
*((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
/* Send LMR */
sdp->sdmr = 0x058d0000;
*((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
/* Stop sending commands */
sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD);
/* Set precharge */
sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL;
*((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
/* Stop manual precharge, send 2 IREF */
sdp->sdcr &= ~(MCF_SDRAMC_SDCR_IPALL);
sdp->sdcr |= MCF_SDRAMC_SDCR_IREF;
*((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
*((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
/* Write mode register, clear reset DLL */
sdp->sdmr = 0x018d0000;
*((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
/* Stop sending commands */
sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD);
sdp->sdcr &= ~(MCF_SDRAMC_SDCR_MODE_EN);
/* Turn on auto refresh, lock SDMR */
sdp->sdcr =
MCF_SDRAMC_SDCR_CKE
| MCF_SDRAMC_SDCR_REF
| MCF_SDRAMC_SDCR_MUX(1)
/* 1 added to round up */
| MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
| MCF_SDRAMC_SDCR_DQS_OE(0x3);
return CFG_SDRAM_SIZE * 1024 * 1024;
};
int testdram (void) {
int testdram(void)
{
/* TODO: XXX XXX XXX */
printf ("DRAM test not implemented!\n");
printf("DRAM test not implemented!\n");
return (0);
}
board/r5200/mii.c → board/freescale/m5275evb/mii.c
View file @ 2c78febd
......@@ -36,10 +36,26 @@ DECLARE_GLOBAL_DATA_PTR;
int fecpin_setclear(struct eth_device *dev, int setclear)
{
struct fec_info_s *info = (struct fec_info_s *) dev->priv;
volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
if (setclear) {
/* Enable Ethernet pins */
mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C);
if (info->iobase == CFG_FEC0_IOBASE) {
gpio->par_feci2c |= 0x0F00;
gpio->par_fec0hl |= 0xC0;
} else {
gpio->par_feci2c |= 0x00A0;
gpio->par_fec1hl |= 0xC0;
}
} else {
if (info->iobase == CFG_FEC0_IOBASE) {
gpio->par_feci2c &= ~0x0F00;
gpio->par_fec0hl &= ~0xC0;
} else {
gpio->par_feci2c &= ~0x00A0;
gpio->par_fec1hl &= ~0xC0;
}
}
return 0;
......@@ -131,7 +147,7 @@ uint mii_send(uint mii_cmd)
return (mii_reply & 0xffff); /* data read from phy */
}
#endif /* CFG_DISCOVER_PHY || (CONFIG_CMD_MII) */
#endif /* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
#if defined(CFG_DISCOVER_PHY)
int mii_discover_phy(struct eth_device *dev)
......@@ -200,7 +216,7 @@ int mii_discover_phy(struct eth_device *dev)
}
#endif /* CFG_DISCOVER_PHY */
int mii_init(void) __attribute__((weak,alias("__mii_init")));
void mii_init(void) __attribute__((weak,alias("__mii_init")));
void __mii_init(void)
{
......
board/r5200/u-boot.lds → board/freescale/m5275evb/u-boot.lds
View file @ 2c78febd
/*
* (C) Copyright 2000
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
......@@ -33,37 +33,36 @@ SECTIONS
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mcf52x2/start.o (.text)
lib_m68k/traps.o (.text)
cpu/mcf52x2/interrupts.o (.text)
common/dlmalloc.o (.text)
lib_generic/string.o (.text)
lib_generic/zlib.o (.text)
. = DEFINED(env_offset) ? env_offset : .;
common/environment.o (.text)
common/environment.o(.text)
*(.text)
*(.fixup)
......@@ -84,8 +83,7 @@ SECTIONS
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
.reloc :
{
__got_start = .;
*(.got)
......@@ -115,7 +113,6 @@ SECTIONS
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
......@@ -129,7 +126,7 @@ SECTIONS
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
.bss :
{
_sbss = .;
*(.sbss) *(.scommon)
......
board/freescale/m54455evb/flash.c
View file @ 2c78febd
......@@ -95,6 +95,11 @@ typedef volatile unsigned char FLASH_PORT_WIDTHV;
#define FLASH_28F256P30T 0x00BD /* Intel 28F256P30T ( 256M = 16M x 16 ) */
#define FLASH_28F256P30B 0x00BE /* Intel 28F256P30B ( 256M = 16M x 16 ) */
#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
#define STM_ID_M25P16 0x20152015
#define FLASH_M25P16 0x0055
#endif
#define SYNC __asm__("nop")
/*-----------------------------------------------------------------------
......@@ -111,6 +116,12 @@ void inline spin_wheel(void);
void flash_sync_real_protect(flash_info_t * info);
uchar intel_sector_protected(flash_info_t * info, ushort sector);
#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
int write_ser_data(flash_info_t * info, ulong dest, uchar * data, ulong cnt);
int serial_flash_read_status(int chipsel);
static int ser_flash_cs = 0;
#endif
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
ulong flash_init(void)
......@@ -119,6 +130,10 @@ ulong flash_init(void)
ulong size = 0;
ulong fbase = 0;
#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
dspi_init();
#endif
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
memset(&flash_info[i], 0, sizeof(flash_info_t));
......@@ -129,6 +144,11 @@ ulong flash_init(void)
case 1:
fbase = (ulong) CFG_FLASH1_BASE;
break;
#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
case 2:
fbase = (ulong) CFG_FLASH2_BASE;
break;
#endif
}
flash_get_size((FPWV *) fbase, &flash_info[i]);
......@@ -152,7 +172,6 @@ int flash_get_offsets(ulong base, flash_info_t * info)
{
int i, j, k;
int sectors, bs, banks;
ulong start;
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_ATM) {
int sect[] = CFG_ATMEL_SECT;
......@@ -196,6 +215,15 @@ int flash_get_offsets(ulong base, flash_info_t * info)
*addr16 = (FPW) INTEL_RESET; /* restore read mode */
}
#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_STM) {
info->start[0] = CFG_FLASH2_BASE;
for (k = 0, i = 0; i < CFG_STM_SECT; i++, k++) {
info->start[k + 1] = info->start[k] + CFG_STM_SECTSZ;
info->protect[k] = 0;
}
}
#endif
return ERR_OK;
}
......@@ -211,6 +239,11 @@ void flash_print_info(flash_info_t * info)
case FLASH_MAN_ATM:
printf("ATMEL ");
break;
#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
case FLASH_MAN_STM:
printf("ST ");
break;
#endif
default:
printf("Unknown Vendor ");
break;
......@@ -221,8 +254,13 @@ void flash_print_info(flash_info_t * info)
printf("AT49BV040A\n");
break;
case FLASH_28F128J3A:
printf("Intel 28F128J3A\n");
printf("28F128J3A\n");
break;
#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
case FLASH_M25P16:
printf("M25P16\n");
break;
#endif
default:
printf("Unknown Chip Type\n");
return;
......@@ -267,6 +305,45 @@ ulong flash_get_size(FPWV * addr, flash_info_t * info)
u16 value;
int i;
#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
if ((ulong) addr == CFG_FLASH2_BASE) {
int manufactId = 0;
int deviceId = 0;
ser_flash_cs = 1;
dspi_tx(ser_flash_cs, 0x80, SER_RDID);
dspi_tx(ser_flash_cs, 0x80, 0);
dspi_tx(ser_flash_cs, 0x80, 0);
dspi_tx(ser_flash_cs, 0x80, 0);
dspi_rx();
manufactId = dspi_rx();
deviceId = dspi_rx() << 8;
deviceId |= dspi_rx();
dspi_tx(ser_flash_cs, 0x00, 0);
dspi_rx();
switch (manufactId) {
case (u8) STM_MANUFACT:
info->flash_id = FLASH_MAN_STM;
break;
}
switch (deviceId) {
case (u16) STM_ID_M25P16:
info->flash_id += FLASH_M25P16;
break;
}
info->sector_count = CFG_STM_SECT;
info->size = CFG_STM_SECT * CFG_STM_SECTSZ;
return (info->size);
}
#endif
addr[FLASH_CYCLE1] = (FPWV) 0x00AA00AA; /* for Atmel, Intel ignores this */
addr[FLASH_CYCLE2] = (FPWV) 0x00550055; /* for Atmel, Intel ignores this */
addr[FLASH_CYCLE1] = (FPWV) 0x00900090; /* selects Intel or Atmel */
......@@ -383,6 +460,21 @@ int flash_cmd_rd(volatile u16 * addr, int index)
return (int)addr[index];
}
#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
int serial_flash_read_status(int chipsel)
{
u16 status;
dspi_tx(chipsel, 0x80, SER_RDSR);
dspi_rx();
dspi_tx(chipsel, 0x00, 0);
status = dspi_rx();
return status;
}
#endif
/*
* This function gets the u-boot flash sector protection status
* (flash_info_t.protect[]) in sync with the sector protection
......@@ -462,8 +554,11 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
{
int flag, prot, sect;
ulong type, start, last;
int rcode = 0, intel = 0;
int rcode = 0, flashtype = 0;
#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
int count;
u16 status;
#endif
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN)
printf("- missing\n");
......@@ -474,19 +569,25 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
type = (info->flash_id & FLASH_VENDMASK);
if (type != (FLASH_MAN_INTEL & FLASH_VENDMASK)) {
if (type != (FLASH_MAN_ATM & FLASH_VENDMASK)) {
type = (info->flash_id & FLASH_VENDMASK);
printf
("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
switch (type) {
case FLASH_MAN_ATM:
flashtype = 1;
break;
case FLASH_MAN_INTEL:
flashtype = 2;
break;
#if defined(CONFIG_SERIAL_FLASH) && defined(CONFIG_CF_DSPI)
case FLASH_MAN_STM:
flashtype = 3;
break;
#endif
default:
type = (info->flash_id & FLASH_VENDMASK);
printf("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
if (type == FLASH_MAN_INTEL)
intel = 1;
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
......@@ -503,6 +604,51 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
start = get_timer(0);
last = start;