Commit 2e88bb28 authored by Kun-Hua Huang's avatar Kun-Hua Huang Committed by Tom Rini

NDS32: Generic Board Support and Unsupport

	Add nds32 ag101p generic board support.
Signed-off-by: default avatarKun-Hua Huang <kunhua@andestech.com>
parent 14006a56
......@@ -56,6 +56,8 @@ config MIPS
config NDS32
bool "NDS32 architecture"
select HAVE_GENERIC_BOARD
select SYS_GENERIC_BOARD
config NIOS2
bool "Nios II architecture"
......
......@@ -12,4 +12,3 @@
extra-y = start.o
obj-$(if $(filter ag101,$(SOC)),y) += ag101/
obj-$(if $(filter ag102,$(SOC)),y) += ag102/
......@@ -205,8 +205,8 @@ relo_base:
* Remapping
*/
led 0x1a
write32 SDMC_B0_BSR_A, SDMC_B0_BSR_D ! 0x00001100
write32 SDMC_B1_BSR_A, SDMC_B1_BSR_D ! 0x00001140
write32 SDMC_B0_BSR_A, SDMC_B0_BSR_D ! 0x00001800
write32 SDMC_B1_BSR_A, SDMC_B1_BSR_D ! 0x00001880
/* clear empty BSR registers */
led 0x1b
......@@ -272,7 +272,11 @@ relo_base:
*/
led 0x1c
write32 SDMC_B0_BSR_A, 0x00001000
write32 SDMC_B1_BSR_A, 0x00001040
write32 SDMC_B1_BSR_A, 0x00001200
li $r5, CONFIG_SYS_TEXT_BASE /* flash base address */
add $r11, $r11, $r5 /* add flash address offset for ret */
add $r10, $r10, $r5
move $lp, $r11
setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP ! 0x1
/*
......@@ -282,9 +286,9 @@ relo_base:
li $r5, AHBC_BSR6_A
lwi $r6, [$r5]
li $r4, 0xfff0ffff
and $r6 ,$r4 , $r6
and $r6 ,$r4, $r6
li $r4, 0x000b0000
or $r6, $r4, $r6
or $r6, $r4, $r6
swi $r6, [$r5]
/*
......@@ -299,7 +303,7 @@ relo_base:
or $r5, $r5, $r6
swi $r5, [$r4]
#endif /* #ifdef CONFIG_MEM_REMAP */
move $lp, $r11
move $lp, $r11
2:
ret
......
......@@ -153,8 +153,11 @@ turnoff_wtdog:
* $sp must be 8-byte alignment for ABI compliance.
*/
call_board_init_f:
li $sp, CONFIG_SYS_INIT_SP_ADDR
li $r0, 0x00000000
li $sp, CONFIG_SYS_INIT_SP_ADDR
li $r10, GD_SIZE /* get GD size */
sub $sp, $sp, $r10 /* GD start addr */
move $r10, $sp
li $r0, 0x00000000
#ifdef __PIC__
#ifdef __NDS32_N1213_43U1H__
......
......@@ -30,6 +30,7 @@ typedef struct bd_info {
unsigned long bi_flashstart; /* start of FLASH memory */
unsigned long bi_flashsize; /* size of FLASH memory */
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned char bi_enetaddr[6];
struct /* RAM configuration */
{
......
......@@ -9,7 +9,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += board.o
obj-y += cache.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-y += interrupts.o
This diff is collapsed.
......@@ -35,6 +35,10 @@ int GIE_STATUS(void)
#ifdef CONFIG_USE_INTERRUPT
int interrupt_init(void)
{
return 0;
}
/* enable interrupts */
void enable_interrupts(void)
{
......
......@@ -28,7 +28,6 @@ int board_init(void)
gd->bd->bi_arch_number = MACH_TYPE_ADPAG101P;
gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
ftsmc020_init(); /* initialize Flash */
return 0;
}
......
......@@ -272,6 +272,8 @@ static int setup_mon_len(void)
gd->mon_len = (ulong)&_end - (ulong)_init;
#elif defined(CONFIG_BLACKFIN) || defined(CONFIG_NIOS2)
gd->mon_len = CONFIG_SYS_MONITOR_LEN;
#elif defined(CONFIG_NDS32)
gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
#else
/* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
......@@ -792,7 +794,8 @@ static init_fnc_t init_sequence_f[] = {
/* TODO: can we rename this to timer_init()? */
init_timebase,
#endif
#if defined(CONFIG_ARM) || defined(CONFIG_MIPS) || defined(CONFIG_BLACKFIN)
#if defined(CONFIG_ARM) || defined(CONFIG_MIPS) || \
defined(CONFIG_BLACKFIN) || defined(CONFIG_NDS32)
timer_init, /* initialize timer */
#endif
#ifdef CONFIG_SYS_ALLOC_DPRAM
......@@ -858,7 +861,8 @@ static init_fnc_t init_sequence_f[] = {
#endif
announce_dram_init,
/* TODO: unify all these dram functions? */
#if defined(CONFIG_ARM) || defined(CONFIG_X86) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32)
#if defined(CONFIG_ARM) || defined(CONFIG_X86) || defined(CONFIG_NDS32) || \
defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32)
dram_init, /* configure available RAM banks */
#endif
#if defined(CONFIG_MIPS) || defined(CONFIG_PPC) || defined(CONFIG_M68K)
......
......@@ -132,6 +132,8 @@ static int initr_reloc_global_data(void)
{
#ifdef __ARM__
monitor_flash_len = _end - __image_copy_start;
#elif defined(CONFIG_NDS32)
monitor_flash_len = (ulong)&_end - (ulong)&_start;
#elif !defined(CONFIG_SANDBOX) && !defined(CONFIG_NIOS2)
monitor_flash_len = (ulong)&__init_end - gd->relocaddr;
#endif
......@@ -711,7 +713,7 @@ init_fnc_t init_sequence_r[] = {
#ifdef CONFIG_DM
initr_dm,
#endif
#ifdef CONFIG_ARM
#if defined(CONFIG_ARM) || defined(CONFIG_NDS32)
board_init, /* Setup chipselects */
#endif
/*
......
......@@ -445,7 +445,7 @@ void fixup_cmdtable(cmd_tbl_t *cmdtp, int size)
ulong addr;
addr = (ulong)(cmdtp->cmd) + gd->reloc_off;
#if DEBUG_COMMANDS
#ifdef DEBUG_COMMANDS
printf("Command \"%s\": 0x%08lx => 0x%08lx\n",
cmdtp->name, (ulong)(cmdtp->cmd), addr);
#endif
......
Andes Technology SoC AG101P
===========================
AG101P is the mainline SoC produced by Andes Technology using N1213 CPU core
with FPU and DDR contoller support.
AG101P has integrated both AHB and APB bus and many periphals for application
and product development.
ADP-AG101P
=========
ADP-AG101P is the SoC with AG101 hardcore CPU.
Configurations
==============
CONFIG_MEM_REMAP:
Doing memory remap is essential for preparing some non-OS or RTOS
applications.
CONFIG_SKIP_LOWLEVEL_INIT:
If you want to boot this system from SPI ROM and bypass e-bios (the
other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT
in "include/configs/adp-ag101p.h".
Build and boot steps
====================
build:
1. Prepare the toolchains and make sure the $PATH to toolchains is correct.
2. Use `make adp-ag101p_defconfig` in u-boot root to build the image.
Burn u-boot to SPI ROM:
====================
This section will be added later.
......@@ -20,22 +20,29 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_GENERIC_GLOBAL_DATA
/*
* Definitions related to passing arguments to kernel.
*/
#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
#define CONFIG_INITRD_TAG /* send initrd params */
#define CONFIG_NEEDS_MANUAL_RELOC
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_MEM_REMAP
#endif
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_TEXT_BASE 0x03200000
#define CONFIG_SYS_TEXT_BASE 0x00500000
#else
#ifdef CONFIG_MEM_REMAP
#define CONFIG_SYS_TEXT_BASE 0x80000000
#else
#define CONFIG_SYS_TEXT_BASE 0x00000000
#endif
#endif
/*
* Timer
......@@ -225,20 +232,33 @@
/*
* Physical Memory Map
*/
#if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
#if defined(CONFIG_MEM_REMAP)
#define PHYS_SDRAM_0_AT_INIT 0x10000000 /* SDRAM Bank #1 before remap*/
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
#else
#ifdef CONFIG_MEM_REMAP
#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
#else
#define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */
#endif
#else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
#define PHYS_SDRAM_0 0x10000000 /* SDRAM Bank #1 */
#endif
#define PHYS_SDRAM_1 \
(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */
#define PHYS_SDRAM_0_SIZE 0x04000000 /* 64 MB */
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
#else
#ifdef CONFIG_MEM_REMAP
#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
#else
#define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
#endif
#endif
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
......@@ -318,19 +338,20 @@
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
/* support JEDEC */
/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
#define PHYS_FLASH_1 0x80400000 /* BANK 1 */
#else /* !CONFIG_SKIP_LOWLEVEL_INIT */
#define PHYS_FLASH_1 0x80000000 /* BANK 0 */
#else
#ifdef CONFIG_MEM_REMAP
#define PHYS_FLASH_1 0x80000000 /* BANK 0 */
#else
#define PHYS_FLASH_1 0x00000000 /* BANK 0 */
#endif
#endif /* CONFIG_MEM_REMAP */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
......@@ -345,11 +366,12 @@
* but we have only 1 bank connected to flash on board
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
/* max number of sectors on one chip */
#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2*2)
#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
#define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE
#define CONFIG_SYS_MAX_FLASH_SECT 128
#define CONFIG_SYS_MAX_FLASH_SECT 512
/* environments */
#define CONFIG_ENV_IS_IN_FLASH
......
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