Commit 30025330 authored by Scott Wood's avatar Scott Wood
Browse files

fsl_elbc_nand: Hard-code the FBAR/FPAR split.



The hardware has separate registers for block and page-within-block,
but the division between the two has no apparent relation to the
actual erase block size of the NAND chip.
Signed-off-by: default avatarScott Wood <scottwood@freescale.com>
parent 9c814b0a
......@@ -138,15 +138,14 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
ctrl->page = page_addr;
out_be32(&lbc->fbar,
page_addr >> (chip->phys_erase_shift - chip->page_shift));
if (priv->page_size) {
out_be32(&lbc->fbar, page_addr >> 6);
out_be32(&lbc->fpar,
((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
(oob ? FPAR_LP_MS : 0) | column);
buf_num = (page_addr & 1) << 2;
} else {
out_be32(&lbc->fbar, page_addr >> 5);
out_be32(&lbc->fpar,
((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
(oob ? FPAR_SP_MS : 0) | column);
......
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