Commit 31f57c28 authored by Simon Glass's avatar Simon Glass
Browse files

x86: Add a x86_ prefix to the x86-specific PCI functions



These functions currently use a generic name, but they are for x86 only.
This may introduce confusion and prevents U-Boot from using these names
more widely.

In fact it should be possible to remove these at some point and use
generic functions, but for now, rename them.
Signed-off-by: default avatarSimon Glass <sjg@chromium.org>
Reviewed-by: default avatarBin Meng <bmeng.cn@gmail.com>
parent 5f7bfdd6
......@@ -50,7 +50,7 @@ static void score_select_func(int pad, int func)
writel(reg, pconf0_addr);
}
static void pci_write_config32(int dev, unsigned int where, u32 value)
static void x86_pci_write_config32(int dev, unsigned int where, u32 value)
{
unsigned long addr;
......@@ -62,7 +62,8 @@ static void pci_write_config32(int dev, unsigned int where, u32 value)
int setup_early_uart(void)
{
/* Enable the legacy UART hardware. */
pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT, 1);
x86_pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT,
1);
/*
* Set up the pads to the UART function. This allows the signals to
......
......@@ -22,36 +22,36 @@ void bd82x6x_pci_init(pci_dev_t dev)
debug("bd82x6x PCI init.\n");
/* Enable Bus Master */
reg16 = pci_read_config16(dev, PCI_COMMAND);
reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
reg16 |= PCI_COMMAND_MASTER;
pci_write_config16(dev, PCI_COMMAND, reg16);
x86_pci_write_config16(dev, PCI_COMMAND, reg16);
/* This device has no interrupt */
pci_write_config8(dev, INTR, 0xff);
x86_pci_write_config8(dev, INTR, 0xff);
/* disable parity error response and SERR */
reg16 = pci_read_config16(dev, BCTRL);
reg16 = x86_pci_read_config16(dev, BCTRL);
reg16 &= ~(1 << 0);
reg16 &= ~(1 << 1);
pci_write_config16(dev, BCTRL, reg16);
x86_pci_write_config16(dev, BCTRL, reg16);
/* Master Latency Count must be set to 0x04! */
reg8 = pci_read_config8(dev, SMLT);
reg8 = x86_pci_read_config8(dev, SMLT);
reg8 &= 0x07;
reg8 |= (0x04 << 3);
pci_write_config8(dev, SMLT, reg8);
x86_pci_write_config8(dev, SMLT, reg8);
/* Will this improve throughput of bus masters? */
pci_write_config8(dev, PCI_MIN_GNT, 0x06);
x86_pci_write_config8(dev, PCI_MIN_GNT, 0x06);
/* Clear errors in status registers */
reg16 = pci_read_config16(dev, PSTS);
reg16 = x86_pci_read_config16(dev, PSTS);
/* reg16 |= 0xf900; */
pci_write_config16(dev, PSTS, reg16);
x86_pci_write_config16(dev, PSTS, reg16);
reg16 = pci_read_config16(dev, SECSTS);
reg16 = x86_pci_read_config16(dev, SECSTS);
/* reg16 |= 0xf900; */
pci_write_config16(dev, SECSTS, reg16);
x86_pci_write_config16(dev, SECSTS, reg16);
}
#define PCI_BRIDGE_UPDATE_COMMAND
......@@ -59,7 +59,7 @@ void bd82x6x_pci_dev_enable_resources(pci_dev_t dev)
{
uint16_t command;
command = pci_read_config16(dev, PCI_COMMAND);
command = x86_pci_read_config16(dev, PCI_COMMAND);
command |= PCI_COMMAND_IO;
#ifdef PCI_BRIDGE_UPDATE_COMMAND
/*
......@@ -67,7 +67,7 @@ void bd82x6x_pci_dev_enable_resources(pci_dev_t dev)
* ROM and APICs to become invisible.
*/
debug("%x cmd <- %02x\n", dev, command);
pci_write_config16(dev, PCI_COMMAND, command);
x86_pci_write_config16(dev, PCI_COMMAND, command);
#else
printf("%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command);
#endif
......@@ -77,11 +77,11 @@ void bd82x6x_pci_bus_enable_resources(pci_dev_t dev)
{
uint16_t ctrl;
ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
ctrl = x86_pci_read_config16(dev, PCI_BRIDGE_CONTROL);
ctrl |= PCI_COMMAND_IO;
ctrl |= PCI_BRIDGE_CTL_VGA;
debug("%x bridge ctrl <- %04x\n", dev, ctrl);
pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
x86_pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
bd82x6x_pci_dev_enable_resources(dev);
}
......
......@@ -167,21 +167,21 @@ static int enable_smbus(void)
dev = PCI_BDF(0x0, 0x1f, 0x3);
/* Check to make sure we've got the right device. */
value = pci_read_config16(dev, 0x0);
value = x86_pci_read_config16(dev, 0x0);
if (value != 0x8086) {
printf("SMBus controller not found\n");
return -ENOSYS;
}
/* Set SMBus I/O base. */
pci_write_config32(dev, SMB_BASE,
SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
x86_pci_write_config32(dev, SMB_BASE,
SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
/* Set SMBus enable. */
pci_write_config8(dev, HOSTC, HST_EN);
x86_pci_write_config8(dev, HOSTC, HST_EN);
/* Set SMBus I/O space enable. */
pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
x86_pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
/* Disable interrupt generation. */
outb(0, SMBUS_IO_BASE + SMBHSTCTL);
......@@ -214,25 +214,25 @@ static void enable_usb_bar(void)
u32 cmd;
/* USB Controller 1 */
pci_write_config32(usb0, PCI_BASE_ADDRESS_0,
PCH_EHCI0_TEMP_BAR0);
cmd = pci_read_config32(usb0, PCI_COMMAND);
x86_pci_write_config32(usb0, PCI_BASE_ADDRESS_0,
PCH_EHCI0_TEMP_BAR0);
cmd = x86_pci_read_config32(usb0, PCI_COMMAND);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config32(usb0, PCI_COMMAND, cmd);
x86_pci_write_config32(usb0, PCI_COMMAND, cmd);
/* USB Controller 1 */
pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
PCH_EHCI1_TEMP_BAR0);
cmd = pci_read_config32(usb1, PCI_COMMAND);
x86_pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
PCH_EHCI1_TEMP_BAR0);
cmd = x86_pci_read_config32(usb1, PCI_COMMAND);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config32(usb1, PCI_COMMAND, cmd);
x86_pci_write_config32(usb1, PCI_COMMAND, cmd);
/* USB3 Controller */
pci_write_config32(usb3, PCI_BASE_ADDRESS_0,
PCH_XHCI_TEMP_BAR0);
cmd = pci_read_config32(usb3, PCI_COMMAND);
x86_pci_write_config32(usb3, PCI_BASE_ADDRESS_0,
PCH_XHCI_TEMP_BAR0);
cmd = x86_pci_read_config32(usb3, PCI_COMMAND);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config32(usb3, PCI_COMMAND, cmd);
x86_pci_write_config32(usb3, PCI_COMMAND, cmd);
}
static int report_bist_failure(void)
......@@ -320,8 +320,8 @@ int print_cpuinfo(void)
gd->arch.pei_boot_mode = boot_mode;
/* TODO: Move this to the board or driver */
pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
pci_write_config32(PCH_LPC_DEV, GPIO_CNTL, 0x10);
x86_pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
x86_pci_write_config32(PCH_LPC_DEV, GPIO_CNTL, 0x10);
/* Print processor name */
name = cpu_get_name(processor_name);
......
......@@ -17,10 +17,10 @@ static void sandybridge_setup_bars(pci_dev_t pch_dev, pci_dev_t lpc_dev)
{
/* Setting up Southbridge. In the northbridge code. */
debug("Setting up static southbridge registers\n");
pci_write_config32(lpc_dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
x86_pci_write_config32(lpc_dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
pci_write_config32(lpc_dev, PMBASE, DEFAULT_PMBASE | 1);
pci_write_config8(lpc_dev, ACPI_CNTL, 0x80); /* Enable ACPI BAR */
x86_pci_write_config32(lpc_dev, PMBASE, DEFAULT_PMBASE | 1);
x86_pci_write_config8(lpc_dev, ACPI_CNTL, 0x80); /* Enable ACPI BAR */
debug("Disabling watchdog reboot\n");
setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */
......@@ -28,25 +28,27 @@ static void sandybridge_setup_bars(pci_dev_t pch_dev, pci_dev_t lpc_dev)
/* Set up all hardcoded northbridge BARs */
debug("Setting up static registers\n");
pci_write_config32(pch_dev, EPBAR, DEFAULT_EPBAR | 1);
pci_write_config32(pch_dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32);
pci_write_config32(pch_dev, MCHBAR, DEFAULT_MCHBAR | 1);
pci_write_config32(pch_dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32);
x86_pci_write_config32(pch_dev, EPBAR, DEFAULT_EPBAR | 1);
x86_pci_write_config32(pch_dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32);
x86_pci_write_config32(pch_dev, MCHBAR, DEFAULT_MCHBAR | 1);
x86_pci_write_config32(pch_dev, MCHBAR + 4,
(0LL + DEFAULT_MCHBAR) >> 32);
/* 64MB - busses 0-63 */
pci_write_config32(pch_dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5);
pci_write_config32(pch_dev, PCIEXBAR + 4,
(0LL + DEFAULT_PCIEXBAR) >> 32);
pci_write_config32(pch_dev, DMIBAR, DEFAULT_DMIBAR | 1);
pci_write_config32(pch_dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32);
x86_pci_write_config32(pch_dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5);
x86_pci_write_config32(pch_dev, PCIEXBAR + 4,
(0LL + DEFAULT_PCIEXBAR) >> 32);
x86_pci_write_config32(pch_dev, DMIBAR, DEFAULT_DMIBAR | 1);
x86_pci_write_config32(pch_dev, DMIBAR + 4,
(0LL + DEFAULT_DMIBAR) >> 32);
/* Set C0000-FFFFF to access RAM on both reads and writes */
pci_write_config8(pch_dev, PAM0, 0x30);
pci_write_config8(pch_dev, PAM1, 0x33);
pci_write_config8(pch_dev, PAM2, 0x33);
pci_write_config8(pch_dev, PAM3, 0x33);
pci_write_config8(pch_dev, PAM4, 0x33);
pci_write_config8(pch_dev, PAM5, 0x33);
pci_write_config8(pch_dev, PAM6, 0x33);
x86_pci_write_config8(pch_dev, PAM0, 0x30);
x86_pci_write_config8(pch_dev, PAM1, 0x33);
x86_pci_write_config8(pch_dev, PAM2, 0x33);
x86_pci_write_config8(pch_dev, PAM3, 0x33);
x86_pci_write_config8(pch_dev, PAM4, 0x33);
x86_pci_write_config8(pch_dev, PAM5, 0x33);
x86_pci_write_config8(pch_dev, PAM6, 0x33);
}
static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev)
......@@ -55,7 +57,7 @@ static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev)
u16 reg16;
u8 reg8;
reg16 = pci_read_config16(video_dev, PCI_DEVICE_ID);
reg16 = x86_pci_read_config16(video_dev, PCI_DEVICE_ID);
switch (reg16) {
case 0x0102: /* GT1 Desktop */
case 0x0106: /* GT1 Mobile */
......@@ -75,7 +77,7 @@ static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev)
debug("Initialising Graphics\n");
/* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
reg16 = pci_read_config16(pch_dev, GGC);
reg16 = x86_pci_read_config16(pch_dev, GGC);
reg16 &= ~0x00f8;
reg16 |= 1 << 3;
/* Program GTT memory by setting GGC[9:8] = 2MB */
......@@ -83,13 +85,13 @@ static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev)
reg16 |= 2 << 8;
/* Enable VGA decode */
reg16 &= ~0x0002;
pci_write_config16(pch_dev, GGC, reg16);
x86_pci_write_config16(pch_dev, GGC, reg16);
/* Enable 256MB aperture */
reg8 = pci_read_config8(video_dev, MSAC);
reg8 = x86_pci_read_config8(video_dev, MSAC);
reg8 &= ~0x06;
reg8 |= 0x02;
pci_write_config8(video_dev, MSAC, reg8);
x86_pci_write_config8(video_dev, MSAC, reg8);
/* Erratum workarounds */
reg32 = readl(MCHBAR_REG(0x5f00));
......@@ -124,22 +126,22 @@ void sandybridge_early_init(int chipset_type)
u8 reg8;
/* Device ID Override Enable should be done very early */
capid0_a = pci_read_config32(pch_dev, 0xe4);
capid0_a = x86_pci_read_config32(pch_dev, 0xe4);
if (capid0_a & (1 << 10)) {
reg8 = pci_read_config8(pch_dev, 0xf3);
reg8 = x86_pci_read_config8(pch_dev, 0xf3);
reg8 &= ~7; /* Clear 2:0 */
if (chipset_type == SANDYBRIDGE_MOBILE)
reg8 |= 1; /* Set bit 0 */
pci_write_config8(pch_dev, 0xf3, reg8);
x86_pci_write_config8(pch_dev, 0xf3, reg8);
}
/* Setup all BARs required for early PCIe and raminit */
sandybridge_setup_bars(pch_dev, lpc_dev);
/* Device Enable */
pci_write_config32(pch_dev, DEVEN, DEVEN_HOST | DEVEN_IGD);
x86_pci_write_config32(pch_dev, DEVEN, DEVEN_HOST | DEVEN_IGD);
sandybridge_setup_graphics(pch_dev, video_dev);
}
......@@ -29,7 +29,7 @@ static inline void pci_read_dword_ptr(void *ptr, int offset)
{
u32 dword;
dword = pci_read_config32(PCH_ME_DEV, offset);
dword = x86_pci_read_config32(PCH_ME_DEV, offset);
memcpy(ptr, &dword, sizeof(dword));
}
......@@ -37,7 +37,7 @@ static inline void pci_write_dword_ptr(void *ptr, int offset)
{
u32 dword = 0;
memcpy(&dword, ptr, sizeof(dword));
pci_write_config32(PCH_ME_DEV, offset, dword);
x86_pci_write_config32(PCH_ME_DEV, offset, dword);
}
void intel_early_me_status(void)
......@@ -101,7 +101,7 @@ static inline void set_global_reset(int enable)
{
u32 etr3;
etr3 = pci_read_config32(PCH_LPC_DEV, ETR3);
etr3 = x86_pci_read_config32(PCH_LPC_DEV, ETR3);
/* Clear CF9 Without Resume Well Reset Enable */
etr3 &= ~ETR3_CWORWRE;
......@@ -112,7 +112,7 @@ static inline void set_global_reset(int enable)
else
etr3 &= ~ETR3_CF9GR;
pci_write_config32(PCH_LPC_DEV, ETR3, etr3);
x86_pci_write_config32(PCH_LPC_DEV, ETR3, etr3);
}
int intel_early_me_init_done(u8 status)
......@@ -127,8 +127,8 @@ int intel_early_me_init_done(u8 status)
};
/* MEBASE from MESEG_BASE[35:20] */
mebase_l = pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_L);
mebase_h = pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_H);
mebase_l = x86_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_L);
mebase_h = x86_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_H);
mebase_h &= 0xf;
did.uma_base = (mebase_l >> 20) | (mebase_h << 12);
......
......@@ -741,9 +741,9 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
int ret;
/* IGD needs to be Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 = x86_pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
pci_write_config32(dev, PCI_COMMAND, reg32);
x86_pci_write_config32(dev, PCI_COMMAND, reg32);
/* Use write-combining for the graphics memory, 256MB */
base = pci_read_bar32(hose, dev, 2);
......
......@@ -29,7 +29,7 @@ static int pch_enable_apic(pci_dev_t dev)
int i;
/* Enable ACPI I/O and power management. Set SCI IRQ to IRQ9 */
pci_write_config8(dev, ACPI_CNTL, 0x80);
x86_pci_write_config8(dev, ACPI_CNTL, 0x80);
writel(0, IO_APIC_INDEX);
writel(1 << 25, IO_APIC_DATA);
......@@ -72,9 +72,9 @@ static void pch_enable_serial_irqs(pci_dev_t dev)
/* Set packet length and toggle silent mode bit for one frame. */
value = (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0);
#ifdef CONFIG_SERIRQ_CONTINUOUS_MODE
pci_write_config8(dev, SERIRQ_CNTL, value);
x86_pci_write_config8(dev, SERIRQ_CNTL, value);
#else
pci_write_config8(dev, SERIRQ_CNTL, value | (1 << 6));
x86_pci_write_config8(dev, SERIRQ_CNTL, value | (1 << 6));
#endif
}
......@@ -86,15 +86,15 @@ static int pch_pirq_init(const void *blob, int node, pci_dev_t dev)
sizeof(route)))
return -EINVAL;
ptr = route;
pci_write_config8(dev, PIRQA_ROUT, *ptr++);
pci_write_config8(dev, PIRQB_ROUT, *ptr++);
pci_write_config8(dev, PIRQC_ROUT, *ptr++);
pci_write_config8(dev, PIRQD_ROUT, *ptr++);
x86_pci_write_config8(dev, PIRQA_ROUT, *ptr++);
x86_pci_write_config8(dev, PIRQB_ROUT, *ptr++);
x86_pci_write_config8(dev, PIRQC_ROUT, *ptr++);
x86_pci_write_config8(dev, PIRQD_ROUT, *ptr++);
pci_write_config8(dev, PIRQE_ROUT, *ptr++);
pci_write_config8(dev, PIRQF_ROUT, *ptr++);
pci_write_config8(dev, PIRQG_ROUT, *ptr++);
pci_write_config8(dev, PIRQH_ROUT, *ptr++);
x86_pci_write_config8(dev, PIRQE_ROUT, *ptr++);
x86_pci_write_config8(dev, PIRQF_ROUT, *ptr++);
x86_pci_write_config8(dev, PIRQG_ROUT, *ptr++);
x86_pci_write_config8(dev, PIRQH_ROUT, *ptr++);
/*
* TODO(sjg@chromium.org): U-Boot does not set up the interrupts
......@@ -116,7 +116,7 @@ static int pch_gpi_routing(const void *blob, int node, pci_dev_t dev)
for (reg = 0, gpi = 0; gpi < ARRAY_SIZE(route); gpi++)
reg |= route[gpi] << (gpi * 2);
pci_write_config32(dev, 0xb8, reg);
x86_pci_write_config32(dev, 0xb8, reg);
return 0;
}
......@@ -141,7 +141,7 @@ static int pch_power_options(const void *blob, int node, pci_dev_t dev)
*/
pwr_on = MAINBOARD_POWER_ON;
reg16 = pci_read_config16(dev, GEN_PMCON_3);
reg16 = x86_pci_read_config16(dev, GEN_PMCON_3);
reg16 &= 0xfffe;
switch (pwr_on) {
case MAINBOARD_POWER_OFF:
......@@ -168,7 +168,7 @@ static int pch_power_options(const void *blob, int node, pci_dev_t dev)
reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */
pci_write_config16(dev, GEN_PMCON_3, reg16);
x86_pci_write_config16(dev, GEN_PMCON_3, reg16);
debug("Set power %s after power failure.\n", state);
/* Set up NMI on errors. */
......@@ -192,21 +192,21 @@ static int pch_power_options(const void *blob, int node, pci_dev_t dev)
outb(reg8, 0x70);
/* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
reg16 = pci_read_config16(dev, GEN_PMCON_1);
reg16 = x86_pci_read_config16(dev, GEN_PMCON_1);
reg16 &= ~(3 << 0); /* SMI# rate 1 minute */
reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */
#if DEBUG_PERIODIC_SMIS
/* Set DEBUG_PERIODIC_SMIS in pch.h to debug using periodic SMIs */
reg16 |= (3 << 0); /* Periodic SMI every 8s */
#endif
pci_write_config16(dev, GEN_PMCON_1, reg16);
x86_pci_write_config16(dev, GEN_PMCON_1, reg16);
/* Set the board's GPI routing. */
ret = pch_gpi_routing(blob, node, dev);
if (ret)
return ret;
pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
pmbase = x86_pci_read_config16(dev, 0x40) & 0xfffe;
writel(pmbase + GPE0_EN, fdtdec_get_int(blob, node,
"intel,gpe0-enable", 0));
......@@ -231,11 +231,11 @@ static void pch_rtc_init(pci_dev_t dev)
int rtc_failed;
u8 reg8;
reg8 = pci_read_config8(dev, GEN_PMCON_3);
reg8 = x86_pci_read_config8(dev, GEN_PMCON_3);
rtc_failed = reg8 & RTC_BATTERY_DEAD;
if (rtc_failed) {
reg8 &= ~RTC_BATTERY_DEAD;
pci_write_config8(dev, GEN_PMCON_3, reg8);
x86_pci_write_config8(dev, GEN_PMCON_3, reg8);
}
debug("rtc_failed = 0x%x\n", rtc_failed);
......@@ -258,7 +258,7 @@ static void pch_rtc_init(pci_dev_t dev)
static void cpt_pm_init(pci_dev_t dev)
{
debug("CougarPoint PM init\n");
pci_write_config8(dev, 0xa9, 0x47);
x86_pci_write_config8(dev, 0xa9, 0x47);
setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0));
setbits_le32(RCB_REG(0x228c), 1 << 0);
......@@ -302,7 +302,7 @@ static void cpt_pm_init(pci_dev_t dev)
static void ppt_pm_init(pci_dev_t dev)
{
debug("PantherPoint PM init\n");
pci_write_config8(dev, 0xa9, 0x47);
x86_pci_write_config8(dev, 0xa9, 0x47);
setbits_le32(RCB_REG(0x2238), 1 << 0);
setbits_le32(RCB_REG(0x228c), 1 << 0);
setbits_le16(RCB_REG(0x1100), (1 << 13) | (1 << 14));
......@@ -356,9 +356,9 @@ static void enable_clock_gating(pci_dev_t dev)
setbits_le32(RCB_REG(0x2234), 0xf);
reg16 = pci_read_config16(dev, GEN_PMCON_1);
reg16 = x86_pci_read_config16(dev, GEN_PMCON_1);
reg16 |= (1 << 2) | (1 << 11);
pci_write_config16(dev, GEN_PMCON_1, reg16);
x86_pci_write_config16(dev, GEN_PMCON_1, reg16);
pch_iobp_update(0xEB007F07, ~0UL, (1 << 31));
pch_iobp_update(0xEB004000, ~0UL, (1 << 7));
......@@ -412,15 +412,15 @@ static void pch_lock_smm(pci_dev_t dev)
#if TEST_SMM_FLASH_LOCKDOWN
/* Now try this: */
debug("Locking BIOS to RO... ");
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
(reg8 & 1) ? "rw" : "ro");
reg8 &= ~(1 << 0); /* clear BIOSWE */
pci_write_config8(dev, 0xdc, reg8);
x86_pci_write_config8(dev, 0xdc, reg8);
reg8 |= (1 << 1); /* set BLE */
pci_write_config8(dev, 0xdc, reg8);
x86_pci_write_config8(dev, 0xdc, reg8);
debug("ok.\n");
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
(reg8 & 1) ? "rw" : "ro");
......@@ -428,9 +428,9 @@ static void pch_lock_smm(pci_dev_t dev)
writeb(0, 0xfff00000);
debug("Testing:\n");
reg8 |= (1 << 0); /* set BIOSWE */
pci_write_config8(dev, 0xdc, reg8);
x86_pci_write_config8(dev, 0xdc, reg8);
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
(reg8 & 1) ? "rw" : "ro");
debug("Done.\n");
......@@ -443,9 +443,9 @@ static void pch_disable_smm_only_flashing(pci_dev_t dev)
u8 reg8;
debug("Enabling BIOS updates outside of SMM... ");
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
reg8 &= ~(1 << 5);
pci_write_config8(dev, 0xdc, reg8);
x86_pci_write_config8(dev, 0xdc, reg8);
}
static void pch_fixups(pci_dev_t dev)
......@@ -453,9 +453,9 @@ static void pch_fixups(pci_dev_t dev)
u8 gen_pmcon_2;
/* Indicate DRAM init done for MRC S3 to know it can resume */
gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2);
gen_pmcon_2 = x86_pci_read_config8(dev, GEN_PMCON_2);
gen_pmcon_2 |= (1 << 7);
pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2);
x86_pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2);
/* Enable DMI ASPM in the PCH */
clrbits_le32(RCB_REG(0x2304), 1 << 10);
......@@ -478,10 +478,10 @@ int lpc_early_init(const void *blob, int node, pci_dev_t dev)
return -EINVAL;
/* Set COM1/COM2 decode range */
pci_write_config16(dev, LPC_IO_DEC, 0x0010);
x86_pci_write_config16(dev, LPC_IO_DEC, 0x0010);
/* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
pci_write_config16(dev, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
x86_pci_write_config16(dev, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
GAMEL_LPC_EN | COMA_LPC_EN);
/* Write all registers but use 0 if we run out of data */
......@@ -491,7 +491,7 @@ int lpc_early_init(const void *blob, int node, pci_dev_t dev)
if (i < count)
reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16);
pci_write_config32(dev, LPC_GENX_DEC(i), reg);
x86_pci_write_config32(dev, LPC_GENX_DEC(i), reg);
}
return 0;
......@@ -514,7 +514,7 @@ int lpc_init(struct pci_controller *hose, pci_dev_t dev)
return -ENOENT;
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND, 0x000f);
x86_pci_write_config16(dev, PCI_COMMAND, 0x000f);
/* IO APIC initialization. */
pch_enable_apic(dev);
......
......@@ -30,7 +30,7 @@ int bridge_silicon_revision(void)
result = cpuid(1);
stepping = result.eax & 0xf;
dev = PCI_BDF(0, 0, 0);
bridge_id = pci_read_config16(dev, PCI_DEVICE_ID) & 0xf0;
bridge_id = x86_pci_read_config16(dev, PCI_DEVICE_ID) & 0xf0;
bridge_revision_id = bridge_id | stepping;
}
......@@ -55,7 +55,7 @@ static int get_pcie_bar(u32 *base, u32 *len)
*base = 0;
*len = 0;
pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
pciexbar_reg = x86_pci_read_config32(dev, PCIEXBAR);
if (!(pciexbar_reg & (1 << 0)))
return 0;
......@@ -170,7 +170,7 @@ void northbridge_init(pci_dev_t dev)
void northbridge_enable(pci_dev_t dev)
{
#if CONFIG_HAVE_ACPI_RESUME
switch (pci_read_config32(dev, SKPAD)) {
switch (x86_pci_read_config32(dev, SKPAD)) {
case 0xcafebabe:
debug("Normal boot.\n");
apci_set_slp_type(0);
......
......@@ -21,7 +21,7 @@ int pch_silicon_revision(void)
dev = PCH_LPC_DEV;
if (pch_revision_id < 0)
pch_revision_id = pci_read_config8(dev, PCI_REVISION_ID);
pch_revision_id = x86_pci_read_config8(dev, PCI_REVISION_ID);
return pch_revision_id;
}
......@@ -32,7 +32,7 @@ int pch_silicon_type(void)
dev = PCH_LPC_DEV;