Commit 34059d8f authored by Tom Rini's avatar Tom Rini
Browse files

Merge branch 'master' of git://www.denx.de/git/u-boot-socfpga

parents 1c0e84ca 48275c96
......@@ -25,6 +25,7 @@
* to be added to the gmac1 device tree blob.
*/
ethernet0 = &gmac1;
udc0 = &usb1;
};
regulator_3_3v: 3-3-v-regulator {
......
......@@ -16,6 +16,7 @@
aliases {
ethernet0 = &gmac1;
udc0 = &usb1;
};
memory {
......@@ -59,3 +60,7 @@
status = "okay";
u-boot,dm-pre-reloc;
};
&usb1 {
status = "okay";
};
......@@ -16,6 +16,7 @@
aliases {
ethernet0 = &gmac0;
udc0 = &usb1;
};
memory {
......@@ -51,3 +52,7 @@
bus-width = <8>;
u-boot,dm-pre-reloc;
};
&usb1 {
status = "okay";
};
......@@ -25,6 +25,7 @@
* to be added to the gmac1 device tree blob.
*/
ethernet0 = &gmac1;
udc0 = &usb1;
};
regulator_3_3v: 3-3-v-regulator {
......@@ -77,10 +78,6 @@
vqmmc-supply = <&regulator_3_3v>;
};
&usb1 {
status = "okay";
};
&qspi {
status = "okay";
......@@ -100,3 +97,7 @@
tslch-ns = <4>;
};
};
&usb1 {
status = "okay";
};
......@@ -14,9 +14,10 @@
bootargs = "console=ttyS0,115200";
};
aliases {
aliases {
ethernet0 = &gmac1;
};
udc0 = &usb1;
};
memory {
name = "memory";
......@@ -90,3 +91,7 @@
tslch-ns = <4>;
};
};
&usb1 {
status = "okay";
};
......@@ -14,6 +14,10 @@
bootargs = "console=ttyS0,115200";
};
aliases {
udc0 = &usb1;
};
memory {
name = "memory";
device_type = "memory";
......@@ -28,6 +32,15 @@
&gmac1 {
status = "okay";
phy-mode = "rgmii";
rxd0-skew-ps = <0>;
rxd1-skew-ps = <0>;
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txen-skew-ps = <0>;
txc-skew-ps = <2600>;
rxdv-skew-ps = <0>;
rxc-skew-ps = <2000>;
};
&i2c0 {
......@@ -63,3 +76,7 @@
tslch-ns = <4>;
};
};
&usb1 {
status = "okay";
};
......@@ -2,9 +2,14 @@ if ARCH_SOCFPGA
config TARGET_SOCFPGA_ARRIA5
bool
select TARGET_SOCFPGA_GEN5
config TARGET_SOCFPGA_CYCLONE5
bool
select TARGET_SOCFPGA_GEN5
config TARGET_SOCFPGA_GEN5
bool
choice
prompt "Altera SOCFPGA board select"
......
......@@ -8,11 +8,12 @@
#
obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
fpga_manager.o scan_manager.o
fpga_manager.o board.o
obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
# QTS-generated config file wrappers
obj-y += wrap_pll_config.o
obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o
obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \
wrap_sdram_config.o
CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
......
/*
* Altera SoCFPGA common board code
*
* Copyright (C) 2015 Marek Vasut <marex@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <errno.h>
#include <asm/arch/reset_manager.h>
#include <asm/io.h>
#include <usb.h>
#include <usb/dwc2_udc.h>
DECLARE_GLOBAL_DATA_PTR;
void s_init(void) {}
/*
* Miscellaneous platform dependent initialisations
*/
int board_init(void)
{
/* Address of boot parameters for ATAG (if ATAG is used) */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}
#ifdef CONFIG_USB_GADGET
struct dwc2_plat_otg_data socfpga_otg_data = {
.usb_gusbcfg = 0x1417,
};
int board_usb_init(int index, enum usb_init_type init)
{
int node[2], count;
fdt_addr_t addr;
count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc",
COMPAT_ALTERA_SOCFPGA_DWC2USB,
node, 2);
if (count <= 0) /* No controller found. */
return 0;
addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg");
if (addr == FDT_ADDR_T_NONE) {
printf("UDC Controller has no 'reg' property!\n");
return -EINVAL;
}
/* Patch the address from OF into the controller pdata. */
socfpga_otg_data.regs_otg = addr;
return dwc2_udc_probe(&socfpga_otg_data);
}
int g_dnl_board_usb_cable_connected(void)
{
return 1;
}
#endif
......@@ -129,9 +129,13 @@ struct socfpga_system_manager {
#define SYSMGR_FPGAINTF_NAND (1 << 4)
#define SYSMGR_FPGAINTF_SDMMC (1 << 5)
/* FIXME: This is questionable macro. */
#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \
((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38))
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#define SYSMGR_SDMMC_SMPLSEL_SHIFT 3
#else
#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
#endif
#define SYSMGR_SDMMC_DRVSEL_SHIFT 0
/* EMAC Group Bit definitions */
#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
......
......@@ -3,83 +3,4 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/reset_manager.h>
#include <asm/io.h>
#include <usb.h>
#include <usb/dwc2_udc.h>
#include <usb_mass_storage.h>
#include <micrel.h>
#include <netdev.h>
#include <phy.h>
DECLARE_GLOBAL_DATA_PTR;
void s_init(void) {}
/*
* Miscellaneous platform dependent initialisations
*/
int board_init(void)
{
/* Address of boot parameters for ATAG (if ATAG is used) */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}
/*
* PHY configuration
*/
#ifdef CONFIG_PHY_MICREL_KSZ9021
int board_phy_config(struct phy_device *phydev)
{
int ret;
/*
* These skew settings for the KSZ9021 ethernet phy is required for ethernet
* to work reliably on most flavors of cyclone5 boards.
*/
ret = ksz9021_phy_extended_write(phydev,
MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
0x0);
if (ret)
return ret;
ret = ksz9021_phy_extended_write(phydev,
MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
0x0);
if (ret)
return ret;
ret = ksz9021_phy_extended_write(phydev,
MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
0xf0f0);
if (ret)
return ret;
if (phydev->drv->config)
return phydev->drv->config(phydev);
return 0;
}
#endif
#ifdef CONFIG_USB_GADGET
struct dwc2_plat_otg_data socfpga_otg_data = {
.regs_otg = CONFIG_USB_DWC2_REG_ADDR,
.usb_gusbcfg = 0x1417,
};
int board_usb_init(int index, enum usb_init_type init)
{
return dwc2_udc_probe(&socfpga_otg_data);
}
int g_dnl_board_usb_cable_connected(void)
{
return 1;
}
#endif
......@@ -3,83 +3,4 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/reset_manager.h>
#include <asm/io.h>
#include <usb.h>
#include <usb/dwc2_udc.h>
#include <usb_mass_storage.h>
#include <micrel.h>
#include <netdev.h>
#include <phy.h>
DECLARE_GLOBAL_DATA_PTR;
void s_init(void) {}
/*
* Miscellaneous platform dependent initialisations
*/
int board_init(void)
{
/* Address of boot parameters for ATAG (if ATAG is used) */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}
/*
* PHY configuration
*/
#ifdef CONFIG_PHY_MICREL_KSZ9021
int board_phy_config(struct phy_device *phydev)
{
int ret;
/*
* These skew settings for the KSZ9021 ethernet phy is required for ethernet
* to work reliably on most flavors of cyclone5 boards.
*/
ret = ksz9021_phy_extended_write(phydev,
MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
0x0);
if (ret)
return ret;
ret = ksz9021_phy_extended_write(phydev,
MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
0x0);
if (ret)
return ret;
ret = ksz9021_phy_extended_write(phydev,
MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
0xf0f0);
if (ret)
return ret;
if (phydev->drv->config)
return phydev->drv->config(phydev);
return 0;
}
#endif
#ifdef CONFIG_USB_GADGET
struct dwc2_plat_otg_data socfpga_otg_data = {
.regs_otg = CONFIG_USB_DWC2_REG_ADDR,
.usb_gusbcfg = 0x1417,
};
int board_usb_init(int index, enum usb_init_type init)
{
return dwc2_udc_probe(&socfpga_otg_data);
}
int g_dnl_board_usb_cable_connected(void)
{
return 1;
}
#endif
......@@ -3,43 +3,4 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/reset_manager.h>
#include <asm/io.h>
#include <usb.h>
#include <usb/dwc2_udc.h>
#include <usb_mass_storage.h>
DECLARE_GLOBAL_DATA_PTR;
void s_init(void) {}
/*
* Miscellaneous platform dependent initialisations
*/
int board_init(void)
{
/* Address of boot parameters for ATAG (if ATAG is used) */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}
#ifdef CONFIG_USB_GADGET
struct dwc2_plat_otg_data socfpga_otg_data = {
.regs_otg = CONFIG_USB_DWC2_REG_ADDR,
.usb_gusbcfg = 0x1417,
};
int board_usb_init(int index, enum usb_init_type init)
{
return dwc2_udc_probe(&socfpga_otg_data);
}
int g_dnl_board_usb_cable_connected(void)
{
return 1;
}
#endif
......@@ -3,83 +3,4 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/reset_manager.h>
#include <asm/io.h>
#include <usb.h>
#include <usb/dwc2_udc.h>
#include <usb_mass_storage.h>
#include <micrel.h>
#include <netdev.h>
#include <phy.h>
DECLARE_GLOBAL_DATA_PTR;
void s_init(void) {}
/*
* Miscellaneous platform dependent initialisations
*/
int board_init(void)
{
/* Address of boot parameters for ATAG (if ATAG is used) */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}
/*
* PHY configuration
*/
#ifdef CONFIG_PHY_MICREL_KSZ9021
int board_phy_config(struct phy_device *phydev)
{
int ret;
/*
* These skew settings for the KSZ9021 ethernet phy is required for ethernet
* to work reliably on most flavors of cyclone5 boards.
*/
ret = ksz9021_phy_extended_write(phydev,
MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
0x0);
if (ret)
return ret;
ret = ksz9021_phy_extended_write(phydev,
MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
0x0);
if (ret)
return ret;
ret = ksz9021_phy_extended_write(phydev,
MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
0xf0f0);
if (ret)
return ret;
if (phydev->drv->config)
return phydev->drv->config(phydev);
return 0;
}
#endif
#ifdef CONFIG_USB_GADGET
struct dwc2_plat_otg_data socfpga_otg_data = {
.regs_otg = CONFIG_USB_DWC2_REG_ADDR,
.usb_gusbcfg = 0x1417,
};
int board_usb_init(int index, enum usb_init_type init)
{
return dwc2_udc_probe(&socfpga_otg_data);
}
int g_dnl_board_usb_cable_connected(void)
{
return 1;
}
#endif
......@@ -5,27 +5,10 @@
*/
#include <common.h>
#include <i2c.h>
#include <miiphy.h>
#include <asm/arch/reset_manager.h>
#include <asm/gpio.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
void s_init(void) {}
/*
* Miscellaneous platform dependent initialisations
*/
int board_init(void)
{
/* Address of boot parameters for ATAG (if ATAG is used) */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}
int board_early_init_f(void)
{
int ret;
......
......@@ -3,70 +3,4 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <micrel.h>
#include <netdev.h>
#include <phy.h>
DECLARE_GLOBAL_DATA_PTR;
void s_init(void) {}
/*
* Miscellaneous platform dependent initialisations
*/
int board_init(void)
{
/* Address of boot parameters for ATAG (if ATAG is used) */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}
/*
* PHY configuration
*/
#ifdef CONFIG_PHY_MICREL_KSZ9031
int board_phy_config(struct phy_device *phydev)
{
int ret;
/*
* These skew settings for the KSZ9021 ethernet phy is required for ethernet
* to work reliably on most flavors of cyclone5 boards.
*/
ret = ksz9031_phy_extended_write(phydev, 0x2,
MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC,
0x70);
if (ret)
return ret;
ret = ksz9031_phy_extended_write(phydev, 0x2,
MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC,
0x7777);
if (ret)
return ret;
ret = ksz9031_phy_extended_write(phydev, 0x2,
MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC,
0);
if (ret)
return ret;
ret = ksz9031_phy_extended_write(phydev, 0x2,
MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
MII_KSZ9031_MOD_DATA_NO_POST_INC,
0x03FC);
if (ret)
return ret;