Commit 393cb361 authored by Chander Kashyap's avatar Chander Kashyap Committed by Albert ARIBAUD
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S5PC2XX: Rename S5pc2XX to exynos



As per new naming convention for Samsung SoC's, all Cortex-A9 and Cortex-A15
based SoC's will be classified under the name Exynos. Cortex-A9 and Cortex-A15
based SoC's will be sub-classified as Exynos4 and Exynos5 respectively.

In order to better adapt and reuse code across various upcoming Samsung Exynos
based boards, all uses of s5pc210 prefix/suffix/directory-names are renamed in
this patch. s5pc210 is renamed as exynos4210 and S5PC210/s5pc210 suffix/prefix
are renamed as exynos4/EXYNOS4.
Signed-off-by: default avatarChander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: default avatarMinkyu Kang <mk7.kang@samsung.com>
parent 7f8c070f
......@@ -693,12 +693,12 @@ Minkyu Kang <mk7.kang@samsung.com>
SMDKC100 ARM ARMV7 (S5PC100 SoC)
s5p_goni ARM ARMV7 (S5PC110 SoC)
s5pc210_universal ARM ARMV7 (S5PC210 SoC)
s5pc210_universal ARM ARMV7 (EXYNOS4210 SoC)
Chander Kashyap <k.chander@samsung.com>
origen ARM ARMV7 (S5PC210 SoC)
SMDKV310 ARM ARMV7 (S5PC210 SoC)
origen ARM ARMV7 (EXYNOS4210 SoC)
SMDKV310 ARM ARMV7 (EXYNOS4210 SoC)
Torsten Koschorrek <koschorrek@synertronixx.de>
scb9328 ARM920T (i.MXL)
......
......@@ -299,7 +299,7 @@ endif
ifeq ($(SOC),s5pc1xx)
LIBS += $(CPUDIR)/s5p-common/libs5p-common.o
endif
ifeq ($(SOC),s5pc2xx)
ifeq ($(SOC),exynos)
LIBS += $(CPUDIR)/s5p-common/libs5p-common.o
endif
......
......@@ -30,11 +30,11 @@
#define CONFIG_SYS_CLK_FREQ_C210 24000000
#endif
/* s5pc210: return pll clock frequency */
static unsigned long s5pc210_get_pll_clk(int pllreg)
/* exynos4: return pll clock frequency */
static unsigned long exynos4_get_pll_clk(int pllreg)
{
struct s5pc210_clock *clk =
(struct s5pc210_clock *)samsung_get_base_clock();
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
unsigned long r, m, p, s, k = 0, mask, fout;
unsigned int freq;
......@@ -96,11 +96,11 @@ static unsigned long s5pc210_get_pll_clk(int pllreg)
return fout;
}
/* s5pc210: return ARM clock frequency */
static unsigned long s5pc210_get_arm_clk(void)
/* exynos4: return ARM clock frequency */
static unsigned long exynos4_get_arm_clk(void)
{
struct s5pc210_clock *clk =
(struct s5pc210_clock *)samsung_get_base_clock();
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
unsigned long div;
unsigned long dout_apll;
unsigned int apll_ratio;
......@@ -115,11 +115,11 @@ static unsigned long s5pc210_get_arm_clk(void)
return dout_apll;
}
/* s5pc210: return pwm clock frequency */
static unsigned long s5pc210_get_pwm_clk(void)
/* exynos4: return pwm clock frequency */
static unsigned long exynos4_get_pwm_clk(void)
{
struct s5pc210_clock *clk =
(struct s5pc210_clock *)samsung_get_base_clock();
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
unsigned long pclk, sclk;
unsigned int sel;
unsigned int ratio;
......@@ -158,11 +158,11 @@ static unsigned long s5pc210_get_pwm_clk(void)
return pclk;
}
/* s5pc210: return uart clock frequency */
static unsigned long s5pc210_get_uart_clk(int dev_index)
/* exynos4: return uart clock frequency */
static unsigned long exynos4_get_uart_clk(int dev_index)
{
struct s5pc210_clock *clk =
(struct s5pc210_clock *)samsung_get_base_clock();
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
unsigned long uclk, sclk;
unsigned int sel;
unsigned int ratio;
......@@ -205,11 +205,11 @@ static unsigned long s5pc210_get_uart_clk(int dev_index)
return uclk;
}
/* s5pc210: set the mmc clock */
static void s5pc210_set_mmc_clk(int dev_index, unsigned int div)
/* exynos4: set the mmc clock */
static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
{
struct s5pc210_clock *clk =
(struct s5pc210_clock *)samsung_get_base_clock();
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
unsigned int addr;
unsigned int val;
......@@ -234,25 +234,25 @@ static void s5pc210_set_mmc_clk(int dev_index, unsigned int div)
unsigned long get_pll_clk(int pllreg)
{
return s5pc210_get_pll_clk(pllreg);
return exynos4_get_pll_clk(pllreg);
}
unsigned long get_arm_clk(void)
{
return s5pc210_get_arm_clk();
return exynos4_get_arm_clk();
}
unsigned long get_pwm_clk(void)
{
return s5pc210_get_pwm_clk();
return exynos4_get_pwm_clk();
}
unsigned long get_uart_clk(int dev_index)
{
return s5pc210_get_uart_clk(dev_index);
return exynos4_get_uart_clk(dev_index);
}
void set_mmc_clk(int dev_index, unsigned int div)
{
s5pc210_set_mmc_clk(dev_index, div);
exynos4_set_mmc_clk(dev_index, div);
}
......@@ -23,7 +23,7 @@
#define __ASM_ARM_ARCH_CLOCK_H_
#ifndef __ASSEMBLY__
struct s5pc210_clock {
struct exynos4_clock {
unsigned char res1[0x4200];
unsigned int src_leftbus;
unsigned char res2[0x1fc];
......
......@@ -19,33 +19,33 @@
*
*/
#ifndef _S5PC2XX_CPU_H
#define _S5PC2XX_CPU_H
#ifndef _EXYNOS4_CPU_H
#define _EXYNOS4_CPU_H
#define S5PC2XX_ADDR_BASE 0x10000000
#define EXYNOS4_ADDR_BASE 0x10000000
/* S5PC210 */
#define S5PC210_GPIO_PART3_BASE 0x03860000
#define S5PC210_PRO_ID 0x10000000
#define S5PC210_POWER_BASE 0x10020000
#define S5PC210_SWRESET 0x10020400
#define S5PC210_CLOCK_BASE 0x10030000
#define S5PC210_SYSTIMER_BASE 0x10050000
#define S5PC210_WATCHDOG_BASE 0x10060000
#define S5PC210_MIU_BASE 0x10600000
#define S5PC210_DMC0_BASE 0x10400000
#define S5PC210_DMC1_BASE 0x10410000
#define S5PC210_GPIO_PART2_BASE 0x11000000
#define S5PC210_GPIO_PART1_BASE 0x11400000
#define S5PC210_FIMD_BASE 0x11C00000
#define S5PC210_USBOTG_BASE 0x12480000
#define S5PC210_MMC_BASE 0x12510000
#define S5PC210_SROMC_BASE 0x12570000
#define S5PC210_USBPHY_BASE 0x125B0000
#define S5PC210_UART_BASE 0x13800000
#define S5PC210_ADC_BASE 0x13910000
#define S5PC210_PWMTIMER_BASE 0x139D0000
#define S5PC210_MODEM_BASE 0x13A00000
/* EXYNOS4 */
#define EXYNOS4_GPIO_PART3_BASE 0x03860000
#define EXYNOS4_PRO_ID 0x10000000
#define EXYNOS4_POWER_BASE 0x10020000
#define EXYNOS4_SWRESET 0x10020400
#define EXYNOS4_CLOCK_BASE 0x10030000
#define EXYNOS4_SYSTIMER_BASE 0x10050000
#define EXYNOS4_WATCHDOG_BASE 0x10060000
#define EXYNOS4_MIU_BASE 0x10600000
#define EXYNOS4_DMC0_BASE 0x10400000
#define EXYNOS4_DMC1_BASE 0x10410000
#define EXYNOS4_GPIO_PART2_BASE 0x11000000
#define EXYNOS4_GPIO_PART1_BASE 0x11400000
#define EXYNOS4_FIMD_BASE 0x11C00000
#define EXYNOS4_USBOTG_BASE 0x12480000
#define EXYNOS4_MMC_BASE 0x12510000
#define EXYNOS4_SROMC_BASE 0x12570000
#define EXYNOS4_USBPHY_BASE 0x125B0000
#define EXYNOS4_UART_BASE 0x13800000
#define EXYNOS4_ADC_BASE 0x13910000
#define EXYNOS4_PWMTIMER_BASE 0x139D0000
#define EXYNOS4_MODEM_BASE 0x13A00000
#ifndef __ASSEMBLY__
#include <asm/io.h>
......@@ -60,12 +60,12 @@ static inline int s5p_get_cpu_rev(void)
static inline void s5p_set_cpu_id(void)
{
s5p_cpu_id = readl(S5PC210_PRO_ID);
s5p_cpu_id = readl(EXYNOS4_PRO_ID);
s5p_cpu_id = (0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12));
/*
* 0xC200: S5PC210 EVT0
* 0xC210: S5PC210 EVT1
* 0xC200: EXYNOS4210 EVT0
* 0xC210: EXYNOS4210 EVT1
*/
if (s5p_cpu_id == 0xC200) {
s5p_cpu_id |= 0x10;
......@@ -81,13 +81,13 @@ static inline int cpu_is_##type(void) \
return s5p_cpu_id == id ? 1 : 0; \
}
IS_SAMSUNG_TYPE(s5pc210, 0xc210)
IS_SAMSUNG_TYPE(exynos4, 0xc210)
#define SAMSUNG_BASE(device, base) \
static inline unsigned int samsung_get_base_##device(void) \
{ \
if (cpu_is_s5pc210()) \
return S5PC210_##base; \
if (cpu_is_exynos4()) \
return EXYNOS4_##base; \
else \
return 0; \
}
......@@ -110,4 +110,4 @@ SAMSUNG_BASE(usb_otg, USBOTG_BASE)
SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
#endif
#endif /* _S5PC2XX_CPU_H */
#endif /* _EXYNOS4_CPU_H */
......@@ -32,7 +32,7 @@ struct s5p_gpio_bank {
unsigned char res1[8];
};
struct s5pc210_gpio_part1 {
struct exynos4_gpio_part1 {
struct s5p_gpio_bank a0;
struct s5p_gpio_bank a1;
struct s5p_gpio_bank b;
......@@ -51,7 +51,7 @@ struct s5pc210_gpio_part1 {
struct s5p_gpio_bank f3;
};
struct s5pc210_gpio_part2 {
struct exynos4_gpio_part2 {
struct s5p_gpio_bank j0;
struct s5p_gpio_bank j1;
struct s5p_gpio_bank k0;
......@@ -75,7 +75,7 @@ struct s5pc210_gpio_part2 {
struct s5p_gpio_bank x3;
};
struct s5pc210_gpio_part3 {
struct exynos4_gpio_part3 {
struct s5p_gpio_bank z;
};
......@@ -92,27 +92,27 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
/* GPIO pins per bank */
#define GPIO_PER_BANK 8
#define s5pc210_gpio_part1_get_nr(bank, pin) \
((((((unsigned int) &(((struct s5pc210_gpio_part1 *) \
S5PC210_GPIO_PART1_BASE)->bank)) \
- S5PC210_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
#define exynos4_gpio_part1_get_nr(bank, pin) \
((((((unsigned int) &(((struct exynos4_gpio_part1 *) \
EXYNOS4_GPIO_PART1_BASE)->bank)) \
- EXYNOS4_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin)
#define GPIO_PART1_MAX ((sizeof(struct s5pc210_gpio_part1) \
#define GPIO_PART1_MAX ((sizeof(struct exynos4_gpio_part1) \
/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
#define s5pc210_gpio_part2_get_nr(bank, pin) \
(((((((unsigned int) &(((struct s5pc210_gpio_part2 *) \
S5PC210_GPIO_PART2_BASE)->bank)) \
- S5PC210_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
#define exynos4_gpio_part2_get_nr(bank, pin) \
(((((((unsigned int) &(((struct exynos4_gpio_part2 *) \
EXYNOS4_GPIO_PART2_BASE)->bank)) \
- EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin) + GPIO_PART1_MAX)
static inline unsigned int s5p_gpio_base(int nr)
{
if (nr < GPIO_PART1_MAX)
return S5PC210_GPIO_PART1_BASE;
return EXYNOS4_GPIO_PART1_BASE;
else
return S5PC210_GPIO_PART2_BASE;
return EXYNOS4_GPIO_PART2_BASE;
return 0;
}
......
/*
* Lowlevel setup for ORIGEN board based on S5PV310
* Lowlevel setup for ORIGEN board based on EXYNOS4210
*
* Copyright (C) 2011 Samsung Electronics
*
......@@ -43,11 +43,11 @@ lowlevel_init:
/* r5 has always zero */
mov r5, #0
ldr r7, =S5PC210_GPIO_PART1_BASE
ldr r6, =S5PC210_GPIO_PART2_BASE
ldr r7, =EXYNOS4_GPIO_PART1_BASE
ldr r6, =EXYNOS4_GPIO_PART2_BASE
/* check reset status */
ldr r0, =(S5PC210_POWER_BASE + INFORM1_OFFSET)
ldr r0, =(EXYNOS4_POWER_BASE + INFORM1_OFFSET)
ldr r1, [r0]
/* AFTR wakeup reset */
......@@ -97,9 +97,9 @@ wakeup_reset:
exit_wakeup:
/* Load return address and jump to kernel */
ldr r0, =(S5PC210_POWER_BASE + INFORM0_OFFSET)
ldr r0, =(EXYNOS4_POWER_BASE + INFORM0_OFFSET)
/* r1 = physical address of s5pc210_cpu_resume function */
/* r1 = physical address of exynos4210_cpu_resume function */
ldr r1, [r0]
/* Jump to kernel*/
......@@ -113,7 +113,7 @@ exit_wakeup:
*/
system_clock_init:
push {lr}
ldr r0, =S5PC210_CLOCK_BASE
ldr r0, =EXYNOS4_CLOCK_BASE
/* APLL(1), MPLL(1), CORE(0), HPM(0) */
ldr r1, =CLK_SRC_CPU_VAL
......@@ -290,13 +290,13 @@ uart_asm_init:
/* setup UART0-UART3 GPIOs (part1) */
mov r0, r7
ldr r1, =S5PC210_GPIO_A0_CON_VAL
str r1, [r0, #S5PC210_GPIO_A0_CON_OFFSET]
ldr r1, =S5PC210_GPIO_A1_CON_VAL
str r1, [r0, #S5PC210_GPIO_A1_CON_OFFSET]
ldr r1, =EXYNOS4_GPIO_A0_CON_VAL
str r1, [r0, #EXYNOS4_GPIO_A0_CON_OFFSET]
ldr r1, =EXYNOS4_GPIO_A1_CON_VAL
str r1, [r0, #EXYNOS4_GPIO_A1_CON_OFFSET]
ldr r0, =S5PC210_UART_BASE
add r0, r0, #S5PC210_DEFAULT_UART_OFFSET
ldr r0, =EXYNOS4_UART_BASE
add r0, r0, #EXYNOS4_DEFAULT_UART_OFFSET
ldr r1, =ULCON_VAL
str r1, [r0, #ULCON_OFFSET]
......
/*
* Memory setup for ORIGEN board based on S5PV310
* Memory setup for ORIGEN board based on EXYNOS4210
*
* Copyright (C) 2011 Samsung Electronics
*
......@@ -38,7 +38,7 @@ mem_ctrl_asm_init:
str r1, [r0]
#ifdef SET_MIU
ldr r0, =S5PC210_MIU_BASE
ldr r0, =EXYNOS4_MIU_BASE
/* Interleave: 2Bit, Interleave_bit1: 0x21, Interleave_bit2: 0x7 */
ldr r1, =0x20001507
str r1, [r0, #APB_SFR_INTERLEAVE_CONF_OFFSET]
......@@ -48,7 +48,7 @@ mem_ctrl_asm_init:
str r1, [r0, #APB_SFR_ARBRITATION_CONF_OFFSET]
#endif
/* DREX0 */
ldr r0, =S5PC210_DMC0_BASE
ldr r0, =EXYNOS4_DMC0_BASE
/*
* DLL Parameter Setting:
......@@ -229,7 +229,7 @@ mem_ctrl_asm_init:
bne 8b
/* DREX1 */
ldr r0, =S5PC210_DMC1_BASE @0x10410000
ldr r0, =EXYNOS4_DMC1_BASE @0x10410000
/*
* DLL Parameter Setting:
......@@ -410,11 +410,11 @@ mem_ctrl_asm_init:
bne 8b
/* turn on DREX0, DREX1 */
ldr r0, =S5PC210_DMC0_BASE
ldr r0, =EXYNOS4_DMC0_BASE
ldr r1, =0x0FFF303a
str r1, [r0, #DMC_CONCONTROL]
ldr r0, =S5PC210_DMC1_BASE
ldr r0, =EXYNOS4_DMC1_BASE
ldr r1, =0x0FFF303a
str r1, [r0, #DMC_CONCONTROL]
......
......@@ -27,13 +27,13 @@
#include <asm/arch/mmc.h>
DECLARE_GLOBAL_DATA_PTR;
struct s5pc210_gpio_part1 *gpio1;
struct s5pc210_gpio_part2 *gpio2;
struct exynos4_gpio_part1 *gpio1;
struct exynos4_gpio_part2 *gpio2;
int board_init(void)
{
gpio1 = (struct s5pc210_gpio_part1 *) S5PC210_GPIO_PART1_BASE;
gpio2 = (struct s5pc210_gpio_part2 *) S5PC210_GPIO_PART2_BASE;
gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
return 0;
......
......@@ -98,8 +98,8 @@
#define INFORM1_OFFSET 0x804
/* GPIO Offsets for UART: GPIO Contol Register */
#define S5PC210_GPIO_A0_CON_OFFSET 0x00
#define S5PC210_GPIO_A1_CON_OFFSET 0x20
#define EXYNOS4_GPIO_A0_CON_OFFSET 0x00
#define EXYNOS4_GPIO_A1_CON_OFFSET 0x20
/* UART Register offsets */
#define ULCON_OFFSET 0x00
......@@ -416,8 +416,8 @@
* UART GPIO_A0/GPIO_A1 Control Register Value
* 0x2: UART Function
*/
#define S5PC210_GPIO_A0_CON_VAL 0x22222222
#define S5PC210_GPIO_A1_CON_VAL 0x222222
#define EXYNOS4_GPIO_A0_CON_VAL 0x22222222
#define EXYNOS4_GPIO_A1_CON_VAL 0x222222
/* ULCON: UART Line Control Value 8N1 */
#define WORD_LEN_5_BIT 0x00
......
/*
* Lowlevel setup for SMDKV310 board based on S5PC210
* Lowlevel setup for SMDKV310 board based on EXYNOS4210
*
* Copyright (C) 2011 Samsung Electronics
*
......@@ -45,11 +45,11 @@ lowlevel_init:
/* r5 has always zero */
mov r5, #0
ldr r7, =S5PC210_GPIO_PART1_BASE
ldr r6, =S5PC210_GPIO_PART2_BASE
ldr r7, =EXYNOS4_GPIO_PART1_BASE
ldr r6, =EXYNOS4_GPIO_PART2_BASE
/* check reset status */
ldr r0, =(S5PC210_POWER_BASE + 0x81C) @ INFORM7
ldr r0, =(EXYNOS4_POWER_BASE + 0x81C) @ INFORM7
ldr r1, [r0]
/* AFTR wakeup reset */
......@@ -95,9 +95,9 @@ wakeup_reset:
exit_wakeup:
/* Load return address and jump to kernel */
ldr r0, =(S5PC210_POWER_BASE + 0x800) @ INFORM0
ldr r0, =(EXYNOS4_POWER_BASE + 0x800) @ INFORM0
/* r1 = physical address of s5pc210_cpu_resume function */
/* r1 = physical address of exynos4210_cpu_resume function */
ldr r1, [r0]
/* Jump to kernel*/
......@@ -111,7 +111,7 @@ exit_wakeup:
*/
system_clock_init:
push {lr}
ldr r0, =S5PC210_CLOCK_BASE
ldr r0, =EXYNOS4_CLOCK_BASE
/* APLL(1), MPLL(1), CORE(0), HPM(0) */
ldr r1, =0x0101
......@@ -388,12 +388,12 @@ uart_asm_init:
/* setup UART0-UART3 GPIOs (part1) */
mov r0, r7
ldr r1, =0x22222222
str r1, [r0, #0x00] @ S5PC210_GPIO_A0_OFFSET
str r1, [r0, #0x00] @ EXYNOS4_GPIO_A0_OFFSET
ldr r1, =0x00222222
str r1, [r0, #0x20] @ S5PC210_GPIO_A1_OFFSET
str r1, [r0, #0x20] @ EXYNOS4_GPIO_A1_OFFSET
ldr r0, =S5PC210_UART_BASE
add r0, r0, #S5PC210_DEFAULT_UART_OFFSET
ldr r0, =EXYNOS4_UART_BASE
add r0, r0, #EXYNOS4_DEFAULT_UART_OFFSET
ldr r1, =0x3C5
str r1, [r0, #0x4]
......
/*
* Memory setup for SMDKV310 board based on S5PC210
* Memory setup for SMDKV310 board based on EXYNOS4210
*
* Copyright (C) 2011 Samsung Electronics
*
......@@ -54,7 +54,7 @@ mem_ctrl_asm_init:
str r1, [r0]
#ifdef SET_MIU
ldr r0, =S5PC210_MIU_BASE @0x10600000
ldr r0, =EXYNOS4_MIU_BASE @0x10600000
#ifdef CONFIG_MIU_1BIT_INTERLEAVED
ldr r1, =0x0000000c
str r1, [r0, #0x400] @MIU_INTLV_CONFIG
......@@ -89,7 +89,7 @@ mem_ctrl_asm_init:
#endif
#endif
/* DREX0 */
ldr r0, =S5PC210_DMC0_BASE @0x10400000
ldr r0, =EXYNOS4_DMC0_BASE @0x10400000
ldr r1, =0xe0000086
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
......@@ -221,7 +221,7 @@ mem_ctrl_asm_init:
bne 8b
/* DREX1 */
ldr r0, =S5PC210_DMC1_BASE @0x10410000
ldr r0, =EXYNOS4_DMC1_BASE @0x10410000
ldr r1, =0xe0000086
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
......
......@@ -29,8 +29,8 @@
#include <asm/arch/sromc.h>
DECLARE_GLOBAL_DATA_PTR;
struct s5pc210_gpio_part1 *gpio1;
struct s5pc210_gpio_part2 *gpio2;
struct exynos4_gpio_part1 *gpio1;
struct exynos4_gpio_part2 *gpio2;
static void smc9115_pre_init(void)
{
......@@ -52,8 +52,8 @@ static void smc9115_pre_init(void)
int board_init(void)
{
gpio1 = (struct s5pc210_gpio_part1 *) S5PC210_GPIO_PART1_BASE;
gpio2 = (struct s5pc210_gpio_part2 *) S5PC210_GPIO_PART2_BASE;
gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
smc9115_pre_init();
......
/*
* Lowlevel setup for universal board based on S5PC210
* Lowlevel setup for universal board based on EXYNOS4210
*
* Copyright (C) 2010 Samsung Electronics
* Kyungmin Park <kyungmin.park@samsung.com>
......@@ -43,11 +43,11 @@ lowlevel_init:
/* r5 has always zero */
mov r5, #0
ldr r7, =S5PC210_GPIO_PART1_BASE
ldr r6, =S5PC210_GPIO_PART2_BASE
ldr r7, =EXYNOS4_GPIO_PART1_BASE
ldr r6, =EXYNOS4_GPIO_PART2_BASE
/* System Timer */
ldr r0, =S5PC210_SYSTIMER_BASE
ldr r0, =EXYNOS4_SYSTIMER_BASE
ldr r1, =0x5000
str r1, [r0, #0x0]
ldr r1, =0xffffffff
......@@ -57,7 +57,7 @@ lowlevel_init:
/* PMIC manual reset */
/* nPOWER: XEINT_23: GPX2[7] */