Commit 39f0023e authored by Matthias Weisser's avatar Matthias Weisser Committed by Albert ARIBAUD
Browse files

imx: Add support for zmx25 board



zmx25 is a board based on imx25 SoC, 64 Megs of LPDDR, 32 Megs of NOR flash, an
optional NAND flash.
Signed-off-by: default avatarMatthias Weisser <weisserm@arcor.de>
parent 95d18589
......@@ -904,6 +904,7 @@ Lei Wen <leiwen@marvell.com>
Matthias Weisser <weisserm@arcor.de>
jadecpu ARM926EJS (MB86R01 SoC)
zmx25 ARM926EJS (imx25 SoC)
Richard Woodruff <r-woodruff2@ti.com>
......
/*
* (C) Copyright 2011
* Matthias Weisser <weisserm@arcor.de>
*
* (C) Copyright 2009 DENX Software Engineering
* Author: John Rigby <jrigby@gmail.com>
*
* Common asm macros for imx25
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_ARM_ARCH_MACRO_H__
#define __ASM_ARM_ARCH_MACRO_H__
#ifdef __ASSEMBLY__
#include <asm/arch/imx-regs.h>
#include <asm/arch/asm-offsets.h>
.macro init_aips
write32 IMX_AIPS1_BASE + AIPS_MPR_0_7, 0x77777777
write32 IMX_AIPS1_BASE + AIPS_MPR_8_15, 0x77777777
write32 IMX_AIPS2_BASE + AIPS_MPR_0_7, 0x77777777
write32 IMX_AIPS2_BASE + AIPS_MPR_8_15, 0x77777777
.endm
.macro init_max
write32 IMX_MAX_BASE + MAX_MPR0, 0x43210
write32 IMX_MAX_BASE + MAX_MPR1, 0x43210
write32 IMX_MAX_BASE + MAX_MPR2, 0x43210
write32 IMX_MAX_BASE + MAX_MPR3, 0x43210
write32 IMX_MAX_BASE + MAX_MPR4, 0x43210
write32 IMX_MAX_BASE + MAX_SGPCR0, 0x10
write32 IMX_MAX_BASE + MAX_SGPCR1, 0x10
write32 IMX_MAX_BASE + MAX_SGPCR2, 0x10
write32 IMX_MAX_BASE + MAX_SGPCR3, 0x10
write32 IMX_MAX_BASE + MAX_SGPCR4, 0x10
write32 IMX_MAX_BASE + MAX_MGPCR0, 0x0
write32 IMX_MAX_BASE + MAX_MGPCR1, 0x0
write32 IMX_MAX_BASE + MAX_MGPCR2, 0x0
write32 IMX_MAX_BASE + MAX_MGPCR3, 0x0
write32 IMX_MAX_BASE + MAX_MGPCR4, 0x0
.endm
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARM_ARCH_MACRO_H__ */
#
# (c) 2010 Graf-Syteco, Matthias Weisser
# <weisserm@arcor.de>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS-y += zmx25.o
SOBJS := lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
/*
* (C) Copyright 2011
* Matthias Weisser <weisserm@arcor.de>
*
* (C) Copyright 2009 DENX Software Engineering
* Author: John Rigby <jrigby@gmail.com>
*
* Based on U-Boot and RedBoot sources for several different i.mx
* platforms.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <asm/macro.h>
#include <asm/arch/macro.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/asm-offsets.h>
/*
* clocks
*/
.macro init_clocks
/* disable clock output */
write32 IMX_CCM_BASE + CCM_MCR, 0x00000000
write32 IMX_CCM_BASE + CCM_CCTL, 0x50030000
/*
* enable all implemented clocks in all three
* clock control registers
*/
write32 IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff
write32 IMX_CCM_BASE + CCM_CGCR1, 0xffffffff
write32 IMX_CCM_BASE + CCM_CGCR2, 0xfffff
/* Devide NAND clock by 32 */
write32 IMX_CCM_BASE + CCM_PCDR2, 0x0101011F
.endm
/*
* sdram controller init
*/
.macro init_lpddr
ldr r0, =IMX_ESDRAMC_BASE
ldr r2, =IMX_SDRAM_BANK0_BASE
/*
* reset SDRAM controller
* then wait for initialization to complete
*/
ldr r1, =(1 << 1) | (1 << 2)
str r1, [r0, #ESDRAMC_ESDMISC]
1: ldr r3, [r0, #ESDRAMC_ESDMISC]
tst r3, #(1 << 31)
beq 1b
ldr r1, =(1 << 2)
str r1, [r0, #ESDRAMC_ESDMISC]
ldr r1, =0x002a7420
str r1, [r0, #ESDRAMC_ESDCFG0]
/* control | precharge */
ldr r1, =0x92216008
str r1, [r0, #ESDRAMC_ESDCTL0]
/* dram command encoded in address */
str r1, [r2, #0x400]
/* auto refresh */
ldr r1, =0xa2216008
str r1, [r0, #ESDRAMC_ESDCTL0]
/* read dram twice to auto refresh */
ldr r3, [r2]
ldr r3, [r2]
/* control | load mode */
ldr r1, =0xb2216008
str r1, [r0, #ESDRAMC_ESDCTL0]
/* mode register of lpddram */
strb r1, [r2, #0x33]
/* extended mode register of lpddrram */
ldr r2, =0x81000000
strb r1, [r2]
/* control | normal */
ldr r1, =0x82216008
str r1, [r0, #ESDRAMC_ESDCTL0]
.endm
.globl lowlevel_init
lowlevel_init:
init_aips
init_max
init_clocks
init_lpddr
mov pc, lr
/*
* (c) 2011 Graf-Syteco, Matthias Weisser
* <weisserm@arcor.de>
*
* Based on tx25.c:
* (C) Copyright 2009 DENX Software Engineering
* Author: John Rigby <jrigby@gmail.com>
*
* Based on imx27lite.c:
* Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
* Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
* And:
* RedBoot tx25_misc.c Copyright (C) 2009 Red Hat
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <mxc_gpio.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/imx25-pinmux.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init()
{
struct iomuxc_mux_ctl *muxctl;
struct iomuxc_pad_ctl *padctl;
struct iomuxc_pad_input_select *inputselect;
u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION;
u32 gpio_mux_mode1 = MX25_PIN_MUX_MODE(1);
u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5);
u32 gpio_mux_mode6 = MX25_PIN_MUX_MODE(6);
u32 input_select1 = MX25_PAD_INPUT_SELECT_DAISY(1);
u32 input_select2 = MX25_PAD_INPUT_SELECT_DAISY(2);
icache_enable();
muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
inputselect = (struct iomuxc_pad_input_select *)IMX_IOPADINPUTSEL_BASE;
/* Setup of core volatage selection pin to run at 1.4V */
writel(gpio_mux_mode5, &muxctl->pad_ext_armclk); /* VCORE GPIO3[15] */
mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(3, 15), MXC_GPIO_DIRECTION_OUT);
mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(3, 15), 1);
/* Setup of input daisy chains for SD card pins*/
writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_cmd);
writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_clk);
writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data0);
writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data1);
writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data2);
writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data3);
/* Setup of digital output for USB power and OC */
writel(gpio_mux_mode5, &muxctl->pad_csi_d3); /* USB Power GPIO1[28] */
mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 28), MXC_GPIO_DIRECTION_OUT);
mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 28), 1);
writel(gpio_mux_mode5, &muxctl->pad_csi_d2); /* USB OC GPIO1[27] */
mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 18), MXC_GPIO_DIRECTION_IN);
/* Setup of digital output control pins */
writel(gpio_mux_mode5, &muxctl->pad_csi_d8); /* Ouput 1 Ctrl GPIO1[7] */
writel(gpio_mux_mode5, &muxctl->pad_csi_d7); /* Ouput 2 Ctrl GPIO1[6] */
writel(gpio_mux_mode5, &muxctl->pad_csi_d6); /* Ouput 1 Stat GPIO1[31]*/
writel(gpio_mux_mode5, &muxctl->pad_csi_d5); /* Ouput 2 Stat GPIO1[30]*/
writel(0, &padctl->pad_csi_d6); /* Ouput 1 Stat pull up off */
writel(0, &padctl->pad_csi_d5); /* Ouput 2 Stat pull up off */
/* Switch both output drivers off */
mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 7), 0);
mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 7), MXC_GPIO_DIRECTION_OUT);
mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 6), 0);
mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 6), MXC_GPIO_DIRECTION_OUT);
/* Setup of key input pin GPIO2[29]*/
writel(gpio_mux_mode5 | MX25_PIN_MUX_SION, &muxctl->pad_kpp_row0);
writel(0, &padctl->pad_kpp_row0); /* Key pull up off */
mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(2, 29), MXC_GPIO_DIRECTION_IN);
/* Setup of status LED outputs */
writel(gpio_mux_mode5, &muxctl->pad_csi_d9); /* GPIO4[21] */
writel(gpio_mux_mode5, &muxctl->pad_csi_d4); /* GPIO1[29] */
/* Switch both LEDs off */
mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(4, 21), 0);
mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(4, 21), MXC_GPIO_DIRECTION_OUT);
mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 29), 0);
mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 29), MXC_GPIO_DIRECTION_OUT);
/* Setup of CAN1 and CAN2 signals */
writel(gpio_mux_mode6, &muxctl->pad_gpio_a); /* CAN1 TX */
writel(gpio_mux_mode6, &muxctl->pad_gpio_b); /* CAN1 RX */
writel(gpio_mux_mode6, &muxctl->pad_gpio_c); /* CAN2 TX */
writel(gpio_mux_mode6, &muxctl->pad_gpio_d); /* CAN2 RX */
/* Setup of input daisy chains for CAN signals*/
writel(input_select1, &inputselect->can1_ipp_ind_canrx); /* CAN1 RX */
writel(input_select1, &inputselect->can2_ipp_ind_canrx); /* CAN2 RX */
/* Setup of I2C3 signals */
writel(gpio_mux_mode1, &muxctl->pad_cspi1_ss1); /* I2C3 SDA */
writel(gpio_mux_mode1, &muxctl->pad_gpio_e); /* I2C3 SCL */
/* Setup of input daisy chains for I2C3 signals*/
writel(input_select1, &inputselect->i2c3_ipp_sda_in); /* I2C3 SDA */
writel(input_select2, &inputselect->i2c3_ipp_scl_in); /* I2C3 SCL */
/* board id for linux */
gd->bd->bi_arch_number = MACH_TYPE_ZMX25;
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
return 0;
}
int board_late_init(void)
{
const char *e;
#ifdef CONFIG_FEC_MXC
struct iomuxc_mux_ctl *muxctl;
struct iomuxc_pad_ctl *padctl;
u32 gpio_mux_mode2 = MX25_PIN_MUX_MODE(2);
u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5);
/*
* fec pin init is generic
*/
mx25_fec_init_pins();
/*
* Set up LAN-RESET and FEC_RX_ERR
*
* LAN-RESET: GPIO3[16] is ALT 5 mode of pin U20
* FEC_RX_ERR: FEC_RX_ERR is ALT 2 mode of pin R2
*/
muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
writel(gpio_mux_mode5, &muxctl->pad_upll_bypclk);
writel(gpio_mux_mode2, &muxctl->pad_uart2_cts);
/* assert PHY reset (low) */
mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(3, 16), 0);
mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(3, 16), MXC_GPIO_DIRECTION_OUT);
udelay(5000);
/* deassert PHY reset */
mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(3, 16), 1);
udelay(5000);
#endif
e = getenv("gs_base_board");
if (e != NULL) {
if (strcmp(e, "G283") == 0) {
int key = mxc_gpio_get(MXC_GPIO_PORT_TO_NUM(2, 29));
if (key) {
/* Switch on both LEDs to inidcate boot mode */
mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 29), 0);
mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(4, 21), 0);
setenv("preboot", "run gs_slow_boot");
} else
setenv("preboot", "run gs_fast_boot");
}
}
return 0;
}
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
PHYS_SDRAM_SIZE);
return 0;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = gd->ram_size;
}
......@@ -131,6 +131,7 @@ rd6281a arm arm926ejs - Marvell
sheevaplug arm arm926ejs - Marvell kirkwood
dockstar arm arm926ejs - Seagate kirkwood
jadecpu arm arm926ejs jadecpu syteco mb86r0x
zmx25 arm arm926ejs zmx25 syteco mx25
imx27lite arm arm926ejs imx27lite logicpd mx27
magnesium arm arm926ejs imx27lite logicpd mx27
nhk8815 arm arm926ejs nhk8815 st nomadik
......
/*
* (c) 2011 Graf-Syteco, Matthias Weisser
* <weisserm@arcor.de>
*
* Configuation settings for the zmx25 board
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_ARM926EJS /* arm926ejs CPU core */
#define CONFIG_MX25
#define CONFIG_MX25_CLK32 32768 /* OSC32K frequency */
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_TEXT_BASE 0xA0000000
/*
* Environment settings
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"gs_fast_boot=setenv bootdelay 5\0" \
"gs_slow_boot=setenv bootdelay 10\0" \
"bootcmd=dcache off; mw.l 0x81000000 0 1024; usb start;" \
"fatls usb 0; fatload usb 0 0x81000000 zmx25-init.bin;" \
"bootm 0x81000000; bootelf 0x81000000\0"
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define BOARD_LATE_INIT
/*
* Compressions
*/
#define CONFIG_LZO
/*
* Hardware drivers
*/
/*
* GPIO
*/
#define CONFIG_MXC_GPIO
/*
* Serial
*/
#define CONFIG_MXC_UART
#define CONFIG_SYS_MX25_UART2
#define CONFIG_CONS_INDEX 1 /* use UART2 for console */
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Ethernet
*/
#define CONFIG_FEC_MXC
#define CONFIG_FEC_MXC_PHYADDR 0x00
#define CONFIG_MII
#define CONFIG_NET_MULTI
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_NET
#define CONFIG_CMD_CACHE
#define CONFIG_SYS_64BIT_VSPRINTF
/*
* Additional command
*/
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
#define CONFIG_CMD_USB
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/*
* USB
*/
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI /* Enable EHCI USB support */
#define CONFIG_USB_EHCI_MXC
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORT 2
#define CONFIG_MXC_USB_PORTSC 0xC0000000
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
#endif /* CONFIG_CMD_USB */
/* SDRAM */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM 0x80000000 /* start address of LPDDRRAM */
#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_SP_ADDR 0x78020000 /* end of internal SRAM */
/*
* FLASH and environment organization
*/
#define CONFIG_SYS_FLASH_BASE 0xA0000000
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 256
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
#define CONFIG_ENV_SIZE (128 * 1024)
/*
* CFI FLASH driver setup
*/
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* ~10x faster */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024))
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE)
#define CONFIG_SYS_PROMPT "zmx25> "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
#define CONFIG_PREBOOT ""
#define CONFIG_BOOTDELAY 5
#define CONFIG_AUTOBOOT_KEYED
#define CONFIG_AUTOBOOT_PROMPT "boot in %d s\n", bootdelay
#define CONFIG_AUTOBOOT_DELAY_STR "delaygs"
#define CONFIG_AUTOBOOT_STOP_STR "stopgs"
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (0x400000 - 0x8000)