Commit 3a1a18ff authored by Simon Glass's avatar Simon Glass
Browse files

x86: Add support for Intel Minnowboard Max



This is a relatively low-cost x86 board in a small form factor. The main
peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800
series CPU. So far only the dual core 2GB variant is supported.

This uses the existing FSP support. Binary blobs are required to make this
board work. The microcode update is included as a patch (all 3000 lines of
it).

Change-Id: I0088c47fe87cf08ae635b343d32c332269062156
Signed-off-by: default avatarSimon Glass <sjg@chromium.org>
Reviewed-by: default avatarBin Meng <bmeng.cn@gmail.com>
parent 00bdd952
......@@ -41,6 +41,17 @@ config TARGET_CROWNBAY
Intel Platform Controller Hub EG20T, other system components and
peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
config TARGET_MINNOWMAX
bool "Support Intel Minnowboard MAX"
help
This is the Intel Minnowboard MAX. It contains an Atom E3800
processor in a small form factor with Ethernet, micro-SD, USB 2,
USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out.
It requires some binary blobs - see README.x86 for details.
Note that PCIE_ECAM_BASE is set up by the FSP so the value used
by U-Boot matches that value.
endchoice
config RAMBASE
......@@ -382,6 +393,8 @@ config FSP_TEMP_RAM_ADDR
Stack top address which is used in FspInit after DRAM is ready and
CAR is disabled.
source "arch/x86/cpu/baytrail/Kconfig"
source "arch/x86/cpu/coreboot/Kconfig"
source "arch/x86/cpu/ivybridge/Kconfig"
......@@ -394,6 +407,8 @@ source "board/google/chromebook_link/Kconfig"
source "board/intel/crownbay/Kconfig"
source "board/intel/minnowmax/Kconfig"
config PCIE_ECAM_BASE
hex
default 0xe0000000
......
......@@ -12,6 +12,7 @@ extra-y = start.o
obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o
obj-y += interrupts.o cpu.o call64.o
obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/
obj-$(CONFIG_SYS_COREBOOT) += coreboot/
obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/
obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/
......
#
# Copyright (C) 2015 Google, Inc
#
# SPDX-License-Identifier: GPL-2.0+
#
config INTEL_BAYTRAIL
bool
select HAVE_FSP
#
# Copyright (C) 2015 Google, Inc
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += early_uart.o
obj-y += fsp_configs.o
obj-y += pci.o
obj-y += valleyview.o
/*
* Copyright (C) 2015 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <errno.h>
#include <asm/io.h>
#define PCI_DEV_CONFIG(segbus, dev, fn) ( \
(((segbus) & 0xfff) << 20) | \
(((dev) & 0x1f) << 15) | \
(((fn) & 0x07) << 12))
/* Platform Controller Unit */
#define LPC_DEV 0x1f
#define LPC_FUNC 0
/* Enable UART */
#define UART_CONT 0x80
/* SCORE Pad definitions */
#define UART_RXD_PAD 82
#define UART_TXD_PAD 83
/* Pad base: PAD_CONF0[n]= PAD_BASE + 16 * n */
#define GPSCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE)
/* IO Memory */
#define IO_BASE_ADDRESS 0xfed0c000
#define IO_BASE_OFFSET_GPSCORE 0x0000
#define IO_BASE_OFFSET_GPNCORE 0x1000
#define IO_BASE_OFFSET_GPSSUS 0x2000
#define IO_BASE_SIZE 0x4000
static inline unsigned int score_pconf0(int pad_num)
{
return GPSCORE_PAD_BASE + pad_num * 16;
}
static void score_select_func(int pad, int func)
{
uint32_t reg;
uint32_t pconf0_addr = score_pconf0(pad);
reg = readl(pconf0_addr);
reg &= ~0x7;
reg |= func & 0x7;
writel(reg, pconf0_addr);
}
static void pci_write_config32(int dev, unsigned int where, u32 value)
{
unsigned long addr;
addr = CONFIG_PCIE_ECAM_BASE | dev | (where & ~3);
writel(value, addr);
}
/* This can be called after memory-mapped PCI is working */
int setup_early_uart(void)
{
/* Enable the legacy UART hardware. */
pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT, 1);
/*
* Set up the pads to the UART function. This allows the signals to
* leave the chip
*/
score_select_func(UART_RXD_PAD, 1);
score_select_func(UART_TXD_PAD, 1);
/* TODO(sjg@chromium.org): Call debug_uart_init() */
return 0;
}
/*
* Copyright (C) 2013, Intel Corporation
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: Intel
*/
#include <common.h>
#include <asm/arch/fsp/azalia.h>
#include <asm/fsp/fsp_support.h>
/* ALC262 Verb Table - 10EC0262 */
static const uint32_t verb_table_data13[] = {
/* Pin Complex (NID 0x11) */
0x01171cf0,
0x01171d11,
0x01171e11,
0x01171f41,
/* Pin Complex (NID 0x12) */
0x01271cf0,
0x01271d11,
0x01271e11,
0x01271f41,
/* Pin Complex (NID 0x14) */
0x01471c10,
0x01471d40,
0x01471e01,
0x01471f01,
/* Pin Complex (NID 0x15) */
0x01571cf0,
0x01571d11,
0x01571e11,
0x01571f41,
/* Pin Complex (NID 0x16) */
0x01671cf0,
0x01671d11,
0x01671e11,
0x01671f41,
/* Pin Complex (NID 0x18) */
0x01871c20,
0x01871d98,
0x01871ea1,
0x01871f01,
/* Pin Complex (NID 0x19) */
0x01971c21,
0x01971d98,
0x01971ea1,
0x01971f02,
/* Pin Complex (NID 0x1A) */
0x01a71c2f,
0x01a71d30,
0x01a71e81,
0x01a71f01,
/* Pin Complex */
0x01b71c1f,
0x01b71d40,
0x01b71e21,
0x01b71f02,
/* Pin Complex */
0x01c71cf0,
0x01c71d11,
0x01c71e11,
0x01c71f41,
/* Pin Complex */
0x01d71c01,
0x01d71dc6,
0x01d71e14,
0x01d71f40,
/* Pin Complex */
0x01e71cf0,
0x01e71d11,
0x01e71e11,
0x01e71f41,
/* Pin Complex */
0x01f71cf0,
0x01f71d11,
0x01f71e11,
0x01f71f41,
};
/*
* This needs to be in ROM since if we put it in CAR, FSP init loses it when
* it drops CAR.
*
* TODO(sjg@chromium.org): Move to device tree when FSP allows it
*
* VerbTable: (RealTek ALC262)
* Revision ID = 0xFF, support all steps
* Codec Verb Table For AZALIA
* Codec Address: CAd value (0/1/2)
* Codec Vendor: 0x10EC0262
*/
static const struct pch_azalia_verb_table azalia_verb_table[] = {
{
{
0x10ec0262,
0x0000,
0xff,
0x01,
0x000b,
0x0002,
},
verb_table_data13
}
};
const struct pch_azalia_config azalia_config = {
.pme_enable = 1,
.docking_supported = 1,
.docking_attached = 0,
.hdmi_codec_enable = 1,
.azalia_v_ci_enable = 1,
.rsvdbits = 0,
.azalia_verb_table_num = 1,
.azalia_verb_table = azalia_verb_table,
.reset_wait_timer_us = 300
};
void update_fsp_upd(struct upd_region *fsp_upd)
{
struct memory_down_data *mem;
/*
* Configure everything here to avoid the poor hard-pressed user
* needing to run Intel's binary configuration tool. It may also allow
* us to support the 1GB single core variant easily.
*
* TODO(sjg@chromium.org): Move to device tree
*/
fsp_upd->mrc_init_tseg_size = 8;
fsp_upd->mrc_init_mmio_size = 0x800;
fsp_upd->emmc_boot_mode = 0xff;
fsp_upd->enable_sdio = 1;
fsp_upd->enable_sdcard = 1;
fsp_upd->enable_hsuart0 = 1;
fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
fsp_upd->enable_i2_c0 = 0;
fsp_upd->enable_i2_c2 = 0;
fsp_upd->enable_i2_c3 = 0;
fsp_upd->enable_i2_c4 = 0;
fsp_upd->enable_xhci = 0;
fsp_upd->igd_render_standby = 1;
mem = &fsp_upd->memory_params;
mem->enable_memory_down = 1;
mem->dram_speed = 1;
mem->dimm_width = 1;
mem->dimm_density = 2;
mem->dimm_tcl = 0xb;
mem->dimm_trpt_rcd = 0xb;
mem->dimm_twr = 0xc;
mem->dimm_twtr = 6;
mem->dimm_trrd = 6;
mem->dimm_trtp = 6;
mem->dimm_tfaw = 0x14;
}
/*
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <pci.h>
#include <asm/pci.h>
#include <asm/fsp/fsp_support.h>
DECLARE_GLOBAL_DATA_PTR;
void board_pci_setup_hose(struct pci_controller *hose)
{
hose->first_busno = 0;
hose->last_busno = 0;
/* PCI memory space */
pci_set_region(hose->regions + 0,
CONFIG_PCI_MEM_BUS,
CONFIG_PCI_MEM_PHYS,
CONFIG_PCI_MEM_SIZE,
PCI_REGION_MEM);
/* PCI IO space */
pci_set_region(hose->regions + 1,
CONFIG_PCI_IO_BUS,
CONFIG_PCI_IO_PHYS,
CONFIG_PCI_IO_SIZE,
PCI_REGION_IO);
pci_set_region(hose->regions + 2,
CONFIG_PCI_PREF_BUS,
CONFIG_PCI_PREF_PHYS,
CONFIG_PCI_PREF_SIZE,
PCI_REGION_PREFETCH);
pci_set_region(hose->regions + 3,
0,
0,
gd->ram_size,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose->region_count = 4;
}
/*
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mmc.h>
#include <pci_ids.h>
#include <asm/post.h>
static struct pci_device_id mmc_supported[] = {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD },
};
int cpu_mmc_init(bd_t *bis)
{
printf("mmc init\n");
return pci_mmc_init("ValleyView SDHCI", mmc_supported,
ARRAY_SIZE(mmc_supported));
}
int arch_cpu_init(void)
{
int ret;
post_code(POST_CPU_INIT);
#ifdef CONFIG_SYS_X86_TSC_TIMER
timer_set_base(rdtsc());
#endif
ret = x86_cpu_init_f();
if (ret)
return ret;
return 0;
}
dtb-y += chromebook_link.dtb \
crownbay.dtb
crownbay.dtb \
minnowmax.dtb
targets += $(dtb-y)
......
This diff is collapsed.
/*
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/ {
model = "Intel Minnowboard Max";
compatible = "intel,minnowmax", "intel,baytrail";
aliases {
serial0 = &serial;
};
config {
silent_console = <0>;
};
chosen {
stdout-path = "/serial";
};
spi {
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ich";
spi-flash@0 {
reg = <0>;
compatible = "sst,25vf016b", "spi-flash";
memory-map = <0xff800000 0x00800000>;
};
};
microcode {
update@0 {
#include "microcode/m0130673322.dtsi"
};
};
};
/ {
serial {
serial: serial {
compatible = "x86-uart";
reg = <0x3f8 8>;
reg-shift = <0>;
......
/*
* Copyright (C) 2013, Intel Corporation
* Copyright (C) 2015 Google, Inc
*
* SPDX-License-Identifier: Intel
*/
#ifndef _FSP_AZALIA_H_
#define _FSP_AZALIA_H_
struct __packed pch_azalia_verb_table_header {
uint32_t vendor_device_id;
uint16_t sub_system_id;
uint8_t revision_id; /* 0xff applies to all steppings */
uint8_t front_panel_support;
uint16_t number_of_rear_jacks;
uint16_t number_of_front_jacks;
};
struct __packed pch_azalia_verb_table {
struct pch_azalia_verb_table_header verb_table_header;
const uint32_t *verb_table_data;
};
struct __packed pch_azalia_config {
uint8_t pme_enable:1;
uint8_t docking_supported:1;
uint8_t docking_attached:1;
uint8_t hdmi_codec_enable:1;
uint8_t azalia_v_ci_enable:1;
uint8_t rsvdbits:3;
/* number of verb tables provided by platform */
uint8_t azalia_verb_table_num;
const struct pch_azalia_verb_table *azalia_verb_table;
/* delay timer after azalia reset */
uint16_t reset_wait_timer_us;
};
#endif
/*
* Copyright (C) 2013, Intel Corporation
* Copyright (C) 2015 Google, Inc
*
* SPDX-License-Identifier: Intel
*/
#ifndef __FSP_VPD_H
#define __FSP_VPD_H
struct memory_down_data {
uint8_t enable_memory_down;
uint8_t dram_speed;
uint8_t dram_type;
uint8_t dimm_0_enable;
uint8_t dimm_1_enable;
uint8_t dimm_width;
uint8_t dimm_density;
uint8_t dimm_bus_width;
uint8_t dimm_sides; /* Ranks Per dimm_ */
uint8_t dimm_tcl; /* tCL */
/* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */
uint8_t dimm_trpt_rcd;
uint8_t dimm_twr; /* tWR in DRAM clk */
uint8_t dimm_twtr; /* tWTR in DRAM clk */
uint8_t dimm_trrd; /* tRRD in DRAM clk */
uint8_t dimm_trtp; /* tRTP in DRAM clk */
uint8_t dimm_tfaw; /* tFAW in DRAM clk */
};
struct __packed upd_region {
uint64_t signature; /* Offset 0x0000 */
uint8_t reserved0[24]; /* Offset 0x0008 */
uint16_t mrc_init_tseg_size; /* Offset 0x0020 */
uint16_t mrc_init_mmio_size; /* Offset 0x0022 */
uint8_t mrc_init_spd_addr1; /* Offset 0x0024 */
uint8_t mrc_init_spd_addr2; /* Offset 0x0025 */
uint8_t emmc_boot_mode; /* Offset 0x0026 */
uint8_t enable_sdio; /* Offset 0x0027 */
uint8_t enable_sdcard; /* Offset 0x0028 */
uint8_t enable_hsuart0; /* Offset 0x0029 */
uint8_t enable_hsuart1; /* Offset 0x002a */
uint8_t enable_spi; /* Offset 0x002b */
uint8_t reserved1; /* Offset 0x002c */
uint8_t enable_sata; /* Offset 0x002d */
uint8_t sata_mode; /* Offset 0x002e */
uint8_t enable_azalia; /* Offset 0x002f */
uint32_t azalia_config_ptr; /* Offset 0x0030 */
uint8_t enable_xhci; /* Offset 0x0034 */
uint8_t enable_lpe; /* Offset 0x0035 */
uint8_t lpss_sio_enable_pci_mode; /* Offset 0x0036 */
uint8_t enable_dma0; /* Offset 0x0037 */
uint8_t enable_dma1; /* Offset 0x0038 */
uint8_t enable_i2_c0; /* Offset 0x0039 */
uint8_t enable_i2_c1; /* Offset 0x003a */
uint8_t enable_i2_c2; /* Offset 0x003b */
uint8_t enable_i2_c3; /* Offset 0x003c */
uint8_t enable_i2_c4; /* Offset 0x003d */
uint8_t enable_i2_c5; /* Offset 0x003e */
uint8_t enable_i2_c6; /* Offset 0x003f */
uint8_t enable_pwm0; /* Offset 0x0040 */
uint8_t enable_pwm1; /* Offset 0x0041 */
uint8_t enable_hsi; /* Offset 0x0042 */
uint8_t igd_dvmt50_pre_alloc; /* Offset 0x0043 */
uint8_t aperture_size; /* Offset 0x0044 */
uint8_t gtt_size; /* Offset 0x0045 */
uint32_t serial_debug_port_address; /* Offset 0x0046 */
uint8_t serial_debug_port_type; /* Offset 0x004a */
uint8_t mrc_debug_msg; /* Offset 0x004b */
uint8_t isp_enable; /* Offset 0x004c */
uint8_t scc_enable_pci_mode; /* Offset 0x004d */
uint8_t igd_render_standby; /* Offset 0x004e */
uint8_t txe_uma_enable; /* Offset 0x004f */
uint8_t os_selection; /* Offset 0x0050 */
uint8_t emmc45_ddr50_enabled; /* Offset 0x0051 */
uint8_t emmc45_hs200_enabled; /* Offset 0x0052 */
uint8_t emmc45_retune_timer_value; /* Offset 0x0053 */
uint8_t unused_upd_space1[156]; /* Offset 0x0054 */
struct memory_down_data memory_params; /* Offset 0x00f0 */
uint16_t terminator; /* Offset 0x0100 */
};
#define VPD_IMAGE_ID 0x3157454956594C56 /* 'VLYVIEW1' */
#define VPD_IMAGE_REV 0x00000303
struct __packed vpd_region {
uint64_t sign; /* Offset 0x0000 */
uint32_t img_rev; /* Offset 0x0008 */
uint32_t upd_offset; /* Offset 0x000c */
uint8_t unused[16]; /* Offset 0x0010 */
uint32_t fsp_res_memlen; /* Offset 0x0020 */
uint8_t platform_type; /* Offset 0x0024 */
uint8_t enable_secure_boot; /* Offset 0x0025 */
};
#endif
/*
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _X86_ARCH_GPIO_H_
#define _X86_ARCH_GPIO_H_
/* Where in config space is the register that points to the GPIO registers? */
#define PCI_CFG_GPIOBASE 0x44
#endif /* _X86_ARCH_GPIO_H_ */
if TARGET_MINNOWMAX
config SYS_BOARD
default "minnowmax"
config SYS_VENDOR
default "intel"
config SYS_SOC
default "baytrail"
config SYS_CONFIG_NAME
default "minnowmax"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select X86_RESET_VECTOR