Commit 3b95288a authored by Tom Rini's avatar Tom Rini

Merge branch 'master' of http://git.denx.de/u-boot-sunxi

parents ec0cc98f 4e7c892d
......@@ -22,6 +22,7 @@ obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o
obj-$(CONFIG_MACH_SUN7I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o
obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o
ifndef CONFIG_SPL_BUILD
ifdef CONFIG_ARMV7_PSCI
......
......@@ -45,10 +45,10 @@ void clock_init_safe(void)
void clock_init_uart(void)
{
#if CONFIG_CONS_INDEX < 5
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
#if CONFIG_CONS_INDEX < 5
/* uart clock source is apb2 */
writel(APB2_CLK_SRC_OSC24M|
APB2_CLK_RATE_N_1|
......@@ -68,9 +68,6 @@ void clock_init_uart(void)
/* enable R_PIO and R_UART clocks, and de-assert resets */
prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
#endif
/* Dup with clock_init_safe(), drop once sun6i SPL support lands */
writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
}
int clock_twi_onoff(int port, int state)
......
/*
* sun9i specific clock code
*
* (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/prcm.h>
#include <asm/arch/sys_proto.h>
void clock_init_uart(void)
{
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
/* open the clock for uart */
setbits_le32(&ccm->apb1_gate,
CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT +
CONFIG_CONS_INDEX - 1));
/* deassert uart reset */
setbits_le32(&ccm->apb1_reset_cfg,
1 << (APB1_RESET_UART_SHIFT +
CONFIG_CONS_INDEX - 1));
/* Dup with clock_init_safe(), drop once sun9i SPL support lands */
writel(PLL4_CFG_DEFAULT, &ccm->pll4_periph0_cfg);
}
int clock_twi_onoff(int port, int state)
{
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
if (port > 4)
return -1;
/* set the apb reset and clock gate for twi */
if (state) {
setbits_le32(&ccm->apb1_gate,
CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
setbits_le32(&ccm->apb1_reset_cfg,
1 << (APB1_RESET_UART_SHIFT + port));
} else {
clrbits_le32(&ccm->apb1_reset_cfg,
1 << (APB1_RESET_UART_SHIFT + port));
clrbits_le32(&ccm->apb1_gate,
CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
}
return 0;
}
unsigned int clock_get_pll4_periph0(void)
{
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
uint32_t rval = readl(&ccm->pll4_periph0_cfg);
int n = ((rval & CCM_PLL4_CTRL_N_MASK) >> CCM_PLL4_CTRL_N_SHIFT);
int p = ((rval & CCM_PLL4_CTRL_P_MASK) >> CCM_PLL4_CTRL_P_SHIFT);
int m = ((rval & CCM_PLL4_CTRL_M_MASK) >> CCM_PLL4_CTRL_M_SHIFT) + 1;
const int k = 1;
return ((24000000 * n * k) >> p) / m;
}
......@@ -17,6 +17,8 @@
/* clock control module regs definition */
#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
#include <asm/arch/clock_sun6i.h>
#elif defined(CONFIG_MACH_SUN9I)
#include <asm/arch/clock_sun9i.h>
#else
#include <asm/arch/clock_sun4i.h>
#endif
......@@ -24,10 +26,6 @@
#ifndef __ASSEMBLY__
int clock_init(void);
int clock_twi_onoff(int port, int state);
void clock_set_pll1(unsigned int hz);
void clock_set_pll3(unsigned int hz);
unsigned int clock_get_pll5p(void);
unsigned int clock_get_pll6(void);
void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz);
void clock_init_safe(void);
void clock_init_uart(void);
......
......@@ -186,6 +186,7 @@ struct sunxi_ccm_reg {
/* ahb clock gate bit offset (second register) */
#define AHB_GATE_OFFSET_GMAC 17
#define AHB_GATE_OFFSET_DE_FE0 14
#define AHB_GATE_OFFSET_DE_BE0 12
#define AHB_GATE_OFFSET_HDMI 11
#define AHB_GATE_OFFSET_LCD1 5
......@@ -266,7 +267,10 @@ struct sunxi_ccm_reg {
#define CCM_MMC_CTRL_PLL5 (0x2 << 24)
#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
#define CCM_DRAM_GATE_OFFSET_DE_FE1 24 /* Note the order of FE1 and */
#define CCM_DRAM_GATE_OFFSET_DE_FE0 25 /* FE0 is swapped ! */
#define CCM_DRAM_GATE_OFFSET_DE_BE0 26
#define CCM_DRAM_GATE_OFFSET_DE_BE1 27
#define CCM_LCD_CH0_CTRL_PLL3 (0 << 24)
#define CCM_LCD_CH0_CTRL_PLL7 (1 << 24)
......@@ -320,4 +324,11 @@ struct sunxi_ccm_reg {
#define CCM_DE_CTRL_RST (1 << 30)
#define CCM_DE_CTRL_GATE (1 << 31)
#ifndef __ASSEMBLY__
void clock_set_pll1(unsigned int hz);
void clock_set_pll3(unsigned int hz);
unsigned int clock_get_pll5p(void);
unsigned int clock_get_pll6(void);
#endif
#endif /* _SUNXI_CLOCK_SUN4I_H */
......@@ -320,6 +320,11 @@ struct sunxi_ccm_reg {
#define CCM_DE_CTRL_PLL10 (5 << 24)
#define CCM_DE_CTRL_GATE (1 << 31)
#ifndef __ASSEMBLY__
void clock_set_pll1(unsigned int hz);
void clock_set_pll3(unsigned int hz);
void clock_set_pll5(unsigned int clk, bool sigma_delta_enable);
unsigned int clock_get_pll6(void);
#endif
#endif /* _SUNXI_CLOCK_SUN6I_H */
/*
* sun9i clock register definitions
*
* (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _SUNXI_CLOCK_SUN9I_H
#define _SUNXI_CLOCK_SUN9I_H
struct sunxi_ccm_reg {
u32 pll1_c0_cfg; /* 0x00 c0cpu# pll configuration */
u32 pll2_c1_cfg; /* 0x04 c1cpu# pll configuration */
u32 pll3_audio_cfg; /* 0x08 audio pll configuration */
u32 pll4_periph0_cfg; /* 0x0c peripheral0 pll configuration */
u32 pll5_ve_cfg; /* 0x10 videoengine pll configuration */
u32 pll6_ddr_cfg; /* 0x14 ddr pll configuration */
u32 pll7_video0_cfg; /* 0x18 video0 pll configuration */
u32 pll8_video1_cfg; /* 0x1c video1 pll configuration */
u32 pll9_gpu_cfg; /* 0x20 gpu pll configuration */
u32 pll10_de_cfg; /* 0x24 displayengine pll configuration */
u32 pll11_isp_cfg; /* 0x28 isp pll6 ontrol */
u32 pll12_periph1_cfg; /* 0x2c peripheral1 pll configuration */
u8 reserved1[0x20]; /* 0x30 */
u32 cpu_clk_source; /* 0x50 cpu clk source configuration */
u32 c0_cfg; /* 0x54 cpu cluster 0 clock configuration */
u32 c1_cfg; /* 0x58 cpu cluster 1 clock configuration */
u32 gtbus_cfg; /* 0x5c gtbus clock configuration */
u32 ahb0_cfg; /* 0x60 ahb0 clock configuration */
u32 ahb1_cfg; /* 0x64 ahb1 clock configuration */
u32 ahb2_cfg; /* 0x68 ahb2 clock configuration */
u8 reserved2[0x04]; /* 0x6c */
u32 apb0_cfg; /* 0x70 apb0 clock configuration */
u32 apb1_cfg; /* 0x74 apb1 clock configuration */
u32 cci400_cfg; /* 0x78 cci400 clock configuration */
u8 reserved3[0x04]; /* 0x7c */
u32 ats_cfg; /* 0x80 ats clock configuration */
u32 trace_cfg; /* 0x84 trace clock configuration */
u8 reserved4[0xf8]; /* 0x88 */
u32 clk_output_a; /* 0x180 clk_output_a */
u32 clk_output_b; /* 0x184 clk_output_a */
u8 reserved5[0x278]; /* 0x188 */
u32 nand0_clk_cfg0; /* 0x400 nand0 clock configuration0 */
u32 nand0_clk_cfg1; /* 0x404 nand1 clock configuration */
u8 reserved6[0x08]; /* 0x408 */
u32 sd0_clk_cfg; /* 0x410 sd0 clock configuration */
u32 sd1_clk_cfg; /* 0x414 sd1 clock configuration */
u32 sd2_clk_cfg; /* 0x418 sd2 clock configuration */
u32 sd3_clk_cfg; /* 0x41c sd3 clock configuration */
u8 reserved7[0x08]; /* 0x420 */
u32 ts_clk_cfg; /* 0x428 transport stream clock cfg */
u32 ss_clk_cfg; /* 0x42c security system clock cfg */
u32 spi0_clk_cfg; /* 0x430 spi0 clock configuration */
u32 spi1_clk_cfg; /* 0x434 spi1 clock configuration */
u32 spi2_clk_cfg; /* 0x438 spi2 clock configuration */
u32 spi3_clk_cfg; /* 0x43c spi3 clock configuration */
u8 reserved8[0x50]; /* 0x440 */
u32 de_clk_cfg; /* 0x490 display engine clock configuration */
u8 reserved9[0x04]; /* 0x494 */
u32 mp_clk_cfg; /* 0x498 mp clock configuration */
u32 lcd0_clk_cfg; /* 0x49c LCD0 module clock */
u32 lcd1_clk_cfg; /* 0x4a0 LCD1 module clock */
u8 reserved10[0x1c]; /* 0x4a4 */
u32 csi_isp_clk_cfg; /* 0x4c0 CSI ISP module clock */
u32 csi0_clk_cfg; /* 0x4c4 CSI0 module clock */
u32 csi1_clk_cfg; /* 0x4c8 CSI1 module clock */
u32 fd_clk_cfg; /* 0x4cc FD module clock */
u32 ve_clk_cfg; /* 0x4d0 VE module clock */
u32 avs_clk_cfg; /* 0x4d4 AVS module clock */
u8 reserved11[0x18]; /* 0x4d8 */
u32 gpu_core_clk_cfg; /* 0x4f0 GPU core clock config */
u32 gpu_mem_clk_cfg; /* 0x4f4 GPU memory clock config */
u32 gpu_axi_clk_cfg; /* 0x4f8 GPU AXI clock config */
u8 reserved12[0x10]; /* 0x4fc */
u32 gp_adc_clk_cfg; /* 0x50c General Purpose ADC clk config */
u8 reserved13[0x70]; /* 0x510 */
u32 ahb_gate0; /* 0x580 AHB0 Gating Register */
u32 ahb_gate1; /* 0x584 AHB1 Gating Register */
u32 ahb_gate2; /* 0x588 AHB2 Gating Register */
u8 reserved14[0x04]; /* 0x58c */
u32 apb0_gate; /* 0x590 APB0 Clock Gating Register */
u32 apb1_gate; /* 0x594 APB1 Clock Gating Register */
u8 reserved15[0x08]; /* 0x598 */
u32 ahb_reset0_cfg; /* 0x5a0 AHB0 Software Reset Register */
u32 ahb_reset1_cfg; /* 0x5a4 AHB1 Software Reset Register */
u32 ahb_reset2_cfg; /* 0x5a8 AHB2 Software Reset Register */
u8 reserved16[0x04]; /* 0x5ac */
u32 apb0_reset_cfg; /* 0x5b0 Bus Software Reset Register 3 */
u32 apb1_reset_cfg; /* 0x5b4 Bus Software Reset Register 4 */
};
/* pll4_periph0_cfg */
#define PLL4_CFG_DEFAULT 0x90002800 /* 960 MHz */
#define CCM_PLL4_CTRL_N_SHIFT 8
#define CCM_PLL4_CTRL_N_MASK (0xff << CCM_PLL4_CTRL_N_SHIFT)
#define CCM_PLL4_CTRL_P_SHIFT 16
#define CCM_PLL4_CTRL_P_MASK (0x1 << CCM_PLL4_CTRL_P_SHIFT)
#define CCM_PLL4_CTRL_M_SHIFT 18
#define CCM_PLL4_CTRL_M_MASK (0x1 << CCM_PLL4_CTRL_M_SHIFT)
/* sd#_clk_cfg fields */
#define CCM_MMC_CTRL_M(x) ((x) - 1)
#define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8)
#define CCM_MMC_CTRL_N(x) ((x) << 16)
#define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20)
#define CCM_MMC_CTRL_OSCM24 (0 << 24)
#define CCM_MMC_CTRL_PLL_PERIPH0 (1 << 24)
#define CCM_MMC_CTRL_ENABLE (1 << 31)
/* ahb_gate0 fields */
/* On sun9i all sdc-s share their ahb gate, so ignore (x) */
#define AHB_GATE_OFFSET_MMC(x) 8
/* apb1_gate fields */
#define APB1_GATE_UART_SHIFT 16
#define APB1_GATE_UART_MASK (0xff << APB1_GATE_UART_SHIFT)
#define APB1_GATE_TWI_SHIFT 0
#define APB1_GATE_TWI_MASK (0xf << APB1_GATE_TWI_SHIFT)
/* ahb_reset0_cfg fields */
/* On sun9i all sdc-s share their ahb reset, so ignore (x) */
#define AHB_RESET_OFFSET_MMC(x) 8
/* apb1_reset_cfg fields */
#define APB1_RESET_UART_SHIFT 16
#define APB1_RESET_UART_MASK (0xff << APB1_RESET_UART_SHIFT)
#define APB1_RESET_TWI_SHIFT 0
#define APB1_RESET_TWI_MASK (0xf << APB1_RESET_TWI_SHIFT)
#ifndef __ASSEMBLY__
unsigned int clock_get_pll4_periph0(void);
#endif
#endif /* _SUNXI_CLOCK_SUN9I_H */
/*
* (C) Copyright 2007-2011
* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
* Tom Cubie <tangliang@allwinnertech.com>
* (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
......@@ -9,146 +7,10 @@
#ifndef _SUNXI_CPU_H
#define _SUNXI_CPU_H
#define SUNXI_SRAM_A1_BASE 0x00000000
#define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */
#define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */
#define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */
#define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */
#define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
#define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */
#define SUNXI_SRAMC_BASE 0x01c00000
#define SUNXI_DRAMC_BASE 0x01c01000
#define SUNXI_DMA_BASE 0x01c02000
#define SUNXI_NFC_BASE 0x01c03000
#define SUNXI_TS_BASE 0x01c04000
#define SUNXI_SPI0_BASE 0x01c05000
#define SUNXI_SPI1_BASE 0x01c06000
#define SUNXI_MS_BASE 0x01c07000
#define SUNXI_TVD_BASE 0x01c08000
#define SUNXI_CSI0_BASE 0x01c09000
#define SUNXI_TVE0_BASE 0x01c0a000
#define SUNXI_EMAC_BASE 0x01c0b000
#define SUNXI_LCD0_BASE 0x01c0C000
#define SUNXI_LCD1_BASE 0x01c0d000
#define SUNXI_VE_BASE 0x01c0e000
#define SUNXI_MMC0_BASE 0x01c0f000
#define SUNXI_MMC1_BASE 0x01c10000
#define SUNXI_MMC2_BASE 0x01c11000
#define SUNXI_MMC3_BASE 0x01c12000
#if !defined CONFIG_MACH_SUN6I && !defined CONFIG_MACH_SUN8I
#define SUNXI_USB0_BASE 0x01c13000
#define SUNXI_USB1_BASE 0x01c14000
#endif
#define SUNXI_SS_BASE 0x01c15000
#define SUNXI_HDMI_BASE 0x01c16000
#define SUNXI_SPI2_BASE 0x01c17000
#define SUNXI_SATA_BASE 0x01c18000
#if !defined CONFIG_MACH_SUN6I && !defined CONFIG_MACH_SUN8I
#define SUNXI_PATA_BASE 0x01c19000
#define SUNXI_ACE_BASE 0x01c1a000
#define SUNXI_TVE1_BASE 0x01c1b000
#define SUNXI_USB2_BASE 0x01c1c000
#if defined(CONFIG_MACH_SUN9I)
#include <asm/arch/cpu_sun9i.h>
#else
#define SUNXI_USB0_BASE 0x01c19000
#define SUNXI_USB1_BASE 0x01c1a000
#define SUNXI_USB2_BASE 0x01c1b000
#include <asm/arch/cpu_sun4i.h>
#endif
#define SUNXI_CSI1_BASE 0x01c1d000
#define SUNXI_TZASC_BASE 0x01c1e000
#define SUNXI_SPI3_BASE 0x01c1f000
#define SUNXI_CCM_BASE 0x01c20000
#define SUNXI_INTC_BASE 0x01c20400
#define SUNXI_PIO_BASE 0x01c20800
#define SUNXI_TIMER_BASE 0x01c20c00
#define SUNXI_SPDIF_BASE 0x01c21000
#define SUNXI_AC97_BASE 0x01c21400
#define SUNXI_IR0_BASE 0x01c21800
#define SUNXI_IR1_BASE 0x01c21c00
#define SUNXI_IIS_BASE 0x01c22400
#define SUNXI_LRADC_BASE 0x01c22800
#define SUNXI_AD_DA_BASE 0x01c22c00
#define SUNXI_KEYPAD_BASE 0x01c23000
#define SUNXI_TZPC_BASE 0x01c23400
#define SUNXI_SID_BASE 0x01c23800
#define SUNXI_SJTAG_BASE 0x01c23c00
#define SUNXI_TP_BASE 0x01c25000
#define SUNXI_PMU_BASE 0x01c25400
#define SUN7I_CPUCFG_BASE 0x01c25c00
#define SUNXI_UART0_BASE 0x01c28000
#define SUNXI_UART1_BASE 0x01c28400
#define SUNXI_UART2_BASE 0x01c28800
#define SUNXI_UART3_BASE 0x01c28c00
#define SUNXI_UART4_BASE 0x01c29000
#define SUNXI_UART5_BASE 0x01c29400
#define SUNXI_UART6_BASE 0x01c29800
#define SUNXI_UART7_BASE 0x01c29c00
#define SUNXI_PS2_0_BASE 0x01c2a000
#define SUNXI_PS2_1_BASE 0x01c2a400
#define SUNXI_TWI0_BASE 0x01c2ac00
#define SUNXI_TWI1_BASE 0x01c2b000
#define SUNXI_TWI2_BASE 0x01c2b400
#define SUNXI_CAN_BASE 0x01c2bc00
#define SUNXI_SCR_BASE 0x01c2c400
#ifndef CONFIG_MACH_SUN6I
#define SUNXI_GPS_BASE 0x01c30000
#define SUNXI_MALI400_BASE 0x01c40000
#define SUNXI_GMAC_BASE 0x01c50000
#else
#define SUNXI_GMAC_BASE 0x01c30000
#endif
#define SUNXI_DRAM_COM_BASE 0x01c62000
#define SUNXI_DRAM_CTL0_BASE 0x01c63000
#define SUNXI_DRAM_CTL1_BASE 0x01c64000
#define SUNXI_DRAM_PHY0_BASE 0x01c65000
#define SUNXI_DRAM_PHY1_BASE 0x01c66000
/* module sram */
#define SUNXI_SRAM_C_BASE 0x01d00000
#define SUNXI_DE_FE0_BASE 0x01e00000
#define SUNXI_DE_FE1_BASE 0x01e20000
#define SUNXI_DE_BE0_BASE 0x01e60000
#define SUNXI_DE_BE1_BASE 0x01e40000
#define SUNXI_MP_BASE 0x01e80000
#define SUNXI_AVG_BASE 0x01ea0000
#define SUNXI_RTC_BASE 0x01f00000
#define SUNXI_PRCM_BASE 0x01f01400
#define SUN6I_CPUCFG_BASE 0x01f01c00
#define SUNXI_R_UART_BASE 0x01f02800
#define SUNXI_R_PIO_BASE 0x01f02c00
#define SUN6I_P2WI_BASE 0x01f03400
#define SUNXI_RSB_BASE 0x01f03400
/* CoreSight Debug Module */
#define SUNXI_CSDM_BASE 0x3f500000
#define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2 GiB */
#define SUNXI_BROM_BASE 0xffff0000 /* 32 kiB */
#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c)
/* SS bonding ids used for cpu identification */
#define SUNXI_SS_BOND_ID_A31 4
#define SUNXI_SS_BOND_ID_A31S 5
#ifndef __ASSEMBLY__
void sunxi_board_init(void);
void sunxi_reset(void);
int sunxi_get_ss_bonding_id(void);
int sunxi_get_sid(unsigned int *sid);
#endif /* __ASSEMBLY__ */
#endif /* _CPU_H */
#endif /* _SUNXI_CPU_H */
/*
* (C) Copyright 2007-2011
* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
* Tom Cubie <tangliang@allwinnertech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _SUNXI_CPU_SUN4I_H
#define _SUNXI_CPU_SUN4I_H
#define SUNXI_SRAM_A1_BASE 0x00000000
#define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */
#define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */
#define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */
#define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */
#define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
#define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */
#define SUNXI_SRAMC_BASE 0x01c00000
#define SUNXI_DRAMC_BASE 0x01c01000
#define SUNXI_DMA_BASE 0x01c02000
#define SUNXI_NFC_BASE 0x01c03000
#define SUNXI_TS_BASE 0x01c04000
#define SUNXI_SPI0_BASE 0x01c05000
#define SUNXI_SPI1_BASE 0x01c06000
#define SUNXI_MS_BASE 0x01c07000
#define SUNXI_TVD_BASE 0x01c08000
#define SUNXI_CSI0_BASE 0x01c09000
#define SUNXI_TVE0_BASE 0x01c0a000
#define SUNXI_EMAC_BASE 0x01c0b000
#define SUNXI_LCD0_BASE 0x01c0C000
#define SUNXI_LCD1_BASE 0x01c0d000
#define SUNXI_VE_BASE 0x01c0e000
#define SUNXI_MMC0_BASE 0x01c0f000
#define SUNXI_MMC1_BASE 0x01c10000
#define SUNXI_MMC2_BASE 0x01c11000
#define SUNXI_MMC3_BASE 0x01c12000
#if !defined CONFIG_MACH_SUN6I && !defined CONFIG_MACH_SUN8I
#define SUNXI_USB0_BASE 0x01c13000
#define SUNXI_USB1_BASE 0x01c14000
#endif
#define SUNXI_SS_BASE 0x01c15000
#define SUNXI_HDMI_BASE 0x01c16000
#define SUNXI_SPI2_BASE 0x01c17000
#define SUNXI_SATA_BASE 0x01c18000
#if !defined CONFIG_MACH_SUN6I && !defined CONFIG_MACH_SUN8I
#define SUNXI_PATA_BASE 0x01c19000
#define SUNXI_ACE_BASE 0x01c1a000
#define SUNXI_TVE1_BASE 0x01c1b000
#define SUNXI_USB2_BASE 0x01c1c000
#else
#define SUNXI_USB0_BASE 0x01c19000
#define SUNXI_USB1_BASE 0x01c1a000
#define SUNXI_USB2_BASE 0x01c1b000
#endif
#define SUNXI_CSI1_BASE 0x01c1d000
#define SUNXI_TZASC_BASE 0x01c1e000
#define SUNXI_SPI3_BASE 0x01c1f000
#define SUNXI_CCM_BASE 0x01c20000
#define SUNXI_INTC_BASE 0x01c20400
#define SUNXI_PIO_BASE 0x01c20800
#define SUNXI_TIMER_BASE 0x01c20c00
#define SUNXI_SPDIF_BASE 0x01c21000
#define SUNXI_AC97_BASE 0x01c21400
#define SUNXI_IR0_BASE 0x01c21800
#define SUNXI_IR1_BASE 0x01c21c00
#define SUNXI_IIS_BASE 0x01c22400
#define SUNXI_LRADC_BASE 0x01c22800
#define SUNXI_AD_DA_BASE 0x01c22c00
#define SUNXI_KEYPAD_BASE 0x01c23000
#define SUNXI_TZPC_BASE 0x01c23400
#define SUNXI_SID_BASE 0x01c23800
#define SUNXI_SJTAG_BASE 0x01c23c00
#define SUNXI_TP_BASE 0x01c25000
#define SUNXI_PMU_BASE 0x01c25400
#define SUN7I_CPUCFG_BASE 0x01c25c00
#define SUNXI_UART0_BASE 0x01c28000
#define SUNXI_UART1_BASE 0x01c28400
#define SUNXI_UART2_BASE 0x01c28800
#define SUNXI_UART3_BASE 0x01c28c00
#define SUNXI_UART4_BASE 0x01c29000
#define SUNXI_UART5_BASE 0x01c29400
#define SUNXI_UART6_BASE 0x01c29800
#define SUNXI_UART7_BASE 0x01c29c00
#define SUNXI_PS2_0_BASE 0x01c2a000
#define SUNXI_PS2_1_BASE 0x01c2a400
#define SUNXI_TWI0_BASE 0x01c2ac00
#define SUNXI_TWI1_BASE 0x01c2b000
#define SUNXI_TWI2_BASE 0x01c2b400
#define SUNXI_CAN_BASE 0x01c2bc00
#define SUNXI_SCR_BASE 0x01c2c400
#ifndef CONFIG_MACH_SUN6I
#define SUNXI_GPS_BASE 0x01c30000
#define SUNXI_MALI400_BASE 0x01c40000
#define SUNXI_GMAC_BASE 0x01c50000
#else
#define SUNXI_GMAC_BASE 0x01c30000
#endif
#define SUNXI_DRAM_COM_BASE 0x01c62000
#define SUNXI_DRAM_CTL0_BASE 0x01c63000
#define SUNXI_DRAM_CTL1_BASE 0x01c64000
#define SUNXI_DRAM_PHY0_BASE 0x01c65000
#define SUNXI_DRAM_PHY1_BASE 0x01c66000
/* module sram */
#define SUNXI_SRAM_C_BASE 0x01d00000
#define SUNXI_DE_FE0_BASE 0x01e00000
#define SUNXI_DE_FE1_BASE 0x01e20000
#define SUNXI_DE_BE0_BASE 0x01e60000
#define SUNXI_DE_BE1_BASE 0x01e40000
#define SUNXI_MP_BASE 0x01e80000
#define SUNXI_AVG_BASE 0x01ea0000
#define SUNXI_RTC_BASE 0x01f00000
#define SUNXI_PRCM_BASE 0x01f01400
#define SUN6I_CPUCFG_BASE 0x01f01c00
#define SUNXI_R_UART_BASE 0x01f02800
#define SUNXI_R_PIO_BASE 0x01f02c00
#define SUN6I_P2WI_BASE 0x01f03400
#define SUNXI_RSB_BASE 0x01f03400
/* CoreSight Debug Module */
#define SUNXI_CSDM_BASE 0x3f500000
#define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2 GiB */
#define SUNXI_BROM_BASE 0xffff0000 /* 32 kiB */
#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c)
/* SS bonding ids used for cpu identification */
#define SUNXI_SS_BOND_ID_A31 4
#define SUNXI_SS_BOND_ID_A31S 5
#ifndef __ASSEMBLY__
void sunxi_board_init(void);
void sunxi_reset(void);
int sunxi_get_ss_bonding_id(void);
int sunxi_get_sid(unsigned int *sid);
#endif /* __ASSEMBLY__ */
#endif /* _SUNXI_CPU_SUN4I_H */
/*
* (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
* (C) Copyright 2007-2013
* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
* Jerry Wang <wangflord@allwinnertech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _SUNXI_CPU_SUN9I_H
#define _SUNXI_CPU_SUN9I_H
#define REGS_AHB0_BASE 0x01C00000
#define REGS_AHB1_BASE 0x00800000
#define REGS_AHB2_BASE 0x03000000
#define REGS_APB0_BASE 0x06000000
#define REGS_APB1_BASE 0x07000000
#define REGS_RCPUS_BASE 0x08000000
#define SUNXI_SRAM_D_BASE 0x08100000
/* AHB0 Module */
#define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
#define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)
#define SUNXI_MMC0_BASE (REGS_AHB0_BASE + 0x0f000)
#define SUNXI_MMC1_BASE (REGS_AHB0_BASE + 0x10000)
#define SUNXI_MMC2_BASE (REGS_AHB0_BASE + 0x11000)
#define SUNXI_MMC3_BASE (REGS_AHB0_BASE + 0x12000)
#define SUNXI_MMC_COMMON_BASE (REGS_AHB0_BASE + 0x13000)
#define SUNXI_SPI0_BASE (REGS_AHB0_BASE + 0x1A000)
#define SUNXI_SPI1_BASE (REGS_AHB0_BASE + 0x1B000)
#define SUNXI_SPI2_BASE (REGS_AHB0_BASE + 0x1C000)
#define SUNXI_SPI3_BASE (REGS_AHB0_BASE + 0x1D000)
#define SUNXI_GIC400_BASE (REGS_AHB0_BASE + 0x40000)
#define SUNXI_ARMA9_GIC_BASE (REGS_AHB0_BASE + 0x41000)
#define SUNXI_ARMA9_CPUIF_BASE (REGS_AHB0_BASE + 0x42000)
/* AHB1 Module */
#define SUNXI_DMA_BASE (REGS_AHB1_BASE + 0x002000)
#define SUNXI_USBOTG_BASE (REGS_AHB1_BASE + 0x100000)
#define SUNXI_USBEHCI0_BASE (REGS_AHB1_BASE + 0x200000)
#define SUNXI_USBEHCI1_BASE (REGS_AHB1_BASE + 0x201000)
#define SUNXI_USBEHCI2_BASE (REGS_AHB1_BASE + 0x202000)
/* AHB2 Module */
#define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000)
#define SUNXI_DISP_SYS_BASE (REGS_AHB2_BASE + 0x010000)
#define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000)
#define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000)
#define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000)
#define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000)
#define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000)
#define SUNXI_DE_BE2_BASE (REGS_AHB2_BASE + 0x280000)
#define SUNXI_DE_DEU0_BASE (REGS_AHB2_BASE + 0x300000)
#define SUNXI_DE_DEU1_BASE (REGS_AHB2_BASE + 0x340000)
#define SUNXI_DE_DRC0_BASE (REGS_AHB2_BASE + 0x400000)
#define SUNXI_DE_DRC1_BASE (REGS_AHB2_BASE + 0x440000)
#define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000)
#define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000)
#define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000)
#define SUNXI_MIPI_DSI0_BASE (REGS_AHB2_BASE + 0xC40000)
/* Also seen as SUNXI_MIPI_DSI0_DPHY_BASE 0x01ca1000 */
#define SUNXI_MIPI_DSI0_DPHY_BASE (REGS_AHB2_BASE + 0xC40100)
#define SUNXI_HDMI_BASE (REGS_AHB2_BASE + 0xD00000)
/* APB0 Module */
#define SUNXI_CCM_BASE (REGS_APB0_BASE + 0x0000)
#define SUNXI_CCMMODULE_BASE (REGS_APB0_BASE + 0x0400)
#define SUNXI_PIO_BASE (REGS_APB0_BASE + 0x0800)
#define SUNXI_R_PIO_BASE (0x08002C00)