Skip to content
GitLab
Menu
Projects
Groups
Snippets
/
Help
Help
Support
Community forum
Keyboard shortcuts
?
Submit feedback
Sign in / Register
Toggle navigation
Menu
Open sidebar
Librem5
uboot-imx
Commits
3ba8bf7c
Commit
3ba8bf7c
authored
Sep 09, 2010
by
Marek Vasut
Committed by
Wolfgang Denk
Oct 19, 2010
Browse files
PXA: pxa-regs.h cleanup
Signed-off-by:
Marek Vasut
<
marek.vasut@gmail.com
>
parent
9f80a20e
Changes
25
Expand all
Hide whitespace changes
Inline
Side-by-side
arch/arm/cpu/pxa/cpu.c
View file @
3ba8bf7c
...
...
@@ -30,10 +30,11 @@
* CPU specific code
*/
#include
<common.h>
#include
<command.h>
#include
<asm/arch/pxa-regs.h>
#include
<asm/io.h>
#include
<asm/system.h>
#include
<command.h>
#include
<common.h>
static
void
cache_flush
(
void
);
...
...
@@ -71,17 +72,22 @@ void set_GPIO_mode(int gpio_mode)
{
int
gpio
=
gpio_mode
&
GPIO_MD_MASK_NR
;
int
fn
=
(
gpio_mode
&
GPIO_MD_MASK_FN
)
>>
8
;
int
gafr
;
int
val
;
/* This below changes direction setting of GPIO "gpio" */
val
=
readl
(
GPDR
(
gpio
));
if
(
gpio_mode
&
GPIO_MD_MASK_DIR
)
{
GPDR
(
gpio
)
|=
GPIO_bit
(
gpio
);
}
val
|=
GPIO_bit
(
gpio
);
else
{
GPDR
(
gpio
)
&=
~
GPIO_bit
(
gpio
);
}
gafr
=
GAFR
(
gpio
)
&
~
(
0x3
<<
(((
gpio
)
&
0xf
)
*
2
));
GAFR
(
gpio
)
=
gafr
|
(
fn
<<
(((
gpio
)
&
0xf
)
*
2
));
val
&=
~
GPIO_bit
(
gpio
);
writel
(
val
,
GPDR
(
gpio
));
/* This below updates only AF of GPIO "gpio" */
val
=
readl
(
GAFR
(
gpio
));
val
&=
~
(
0x3
<<
(((
gpio
)
&
0xf
)
*
2
));
val
|=
fn
<<
(((
gpio
)
&
0xf
)
*
2
);
writel
(
val
,
GAFR
(
gpio
));
}
#endif
/* CONFIG_CPU_MONAHANS */
arch/arm/cpu/pxa/i2c.c
View file @
3ba8bf7c
...
...
@@ -33,6 +33,7 @@
/* FIXME: this file is PXA255 specific! What about other XScales? */
#include
<common.h>
#include
<asm/io.h>
#ifdef CONFIG_HARD_I2C
...
...
@@ -93,19 +94,21 @@ struct i2c_msg {
static
void
i2c_reset
(
void
)
{
ICR
&
=
~
ICR_IUE
;
/* disable unit */
ICR
|
=
ICR_UR
;
/* reset the unit */
writel
(
readl
(
ICR
)
&
~
ICR_IUE
,
ICR
)
;
/* disable unit */
writel
(
readl
(
ICR
)
|
ICR_UR
,
ICR
);
/* reset the unit */
udelay
(
100
);
ICR
&
=
~
ICR_IUE
;
/* disable unit */
writel
(
readl
(
ICR
)
&
~
ICR_IUE
,
ICR
)
;
/* disable unit */
#ifdef CONFIG_CPU_MONAHANS
CKENB
|=
(
CKENB_4_I2C
);
/* | CKENB_1_PWM1 | CKENB_0_PWM0); */
/* | CKENB_1_PWM1 | CKENB_0_PWM0); */
writel
(
readl
(
CKENB
)
|
(
CKENB_4_I2C
),
CKENB
);
#else
/* CONFIG_CPU_MONAHANS */
CKEN
|=
CKEN14_I2C
;
/* set the global I2C clock on */
/* set the global I2C clock on */
writel
(
readl
(
CKEN
)
|
CKEN14_I2C
,
CKEN
);
#endif
ISAR
=
I2C_PXA_SLAVE_ADDR
;
/* set our slave address */
ICR
=
I2C_ICR_INIT
;
/* set control reg
ister
values */
ISR
=
I2C_ISR_INIT
;
/* set clear interrupt bits */
ICR
|
=
ICR_IUE
;
/* enable unit */
writel
(
I2C_PXA_SLAVE_ADDR
,
ISAR
)
;
/* set our slave address */
writel
(
I2C_ICR_INIT
,
ICR
)
;
/* set control reg values */
writel
(
I2C_ISR_INIT
,
ISR
)
;
/* set clear interrupt bits */
writel
(
readl
(
ICR
)
|
ICR_IUE
,
ICR
);
/* enable unit */
udelay
(
100
);
}
...
...
@@ -159,22 +162,26 @@ int i2c_transfer(struct i2c_msg *msg)
goto
transfer_error_bus_busy
;
/* start transmission */
ICR
&=
~
ICR_START
;
ICR
&=
~
ICR_STOP
;
IDBR
=
msg
->
data
;
if
(
msg
->
condition
==
I2C_COND_START
)
ICR
|=
ICR_START
;
if
(
msg
->
condition
==
I2C_COND_STOP
)
ICR
|=
ICR_STOP
;
if
(
msg
->
acknack
==
I2C_ACKNAK_SENDNAK
)
ICR
|=
ICR_ACKNAK
;
if
(
msg
->
acknack
==
I2C_ACKNAK_SENDACK
)
ICR
&=
~
ICR_ACKNAK
;
ICR
&=
~
ICR_ALDIE
;
ICR
|=
ICR_TB
;
writel
(
readl
(
ICR
)
&
~
ICR_START
,
ICR
);
writel
(
readl
(
ICR
)
&
~
ICR_STOP
,
ICR
);
writel
(
msg
->
data
,
IDBR
);
if
(
msg
->
condition
==
I2C_COND_START
)
writel
(
readl
(
ICR
)
|
ICR_START
,
ICR
);
if
(
msg
->
condition
==
I2C_COND_STOP
)
writel
(
readl
(
ICR
)
|
ICR_STOP
,
ICR
);
if
(
msg
->
acknack
==
I2C_ACKNAK_SENDNAK
)
writel
(
readl
(
ICR
)
|
ICR_ACKNAK
,
ICR
);
if
(
msg
->
acknack
==
I2C_ACKNAK_SENDACK
)
writel
(
readl
(
ICR
)
&
~
ICR_ACKNAK
,
ICR
);
writel
(
readl
(
ICR
)
&
~
ICR_ALDIE
,
ICR
);
writel
(
readl
(
ICR
)
|
ICR_TB
,
ICR
);
/* transmit register empty? */
if
(
!
i2c_isr_set_cleared
(
ISR_ITE
,
0
))
goto
transfer_error_transmit_timeout
;
/* clear 'transmit empty' state */
ISR
|
=
ISR_ITE
;
writel
(
readl
(
ISR
)
|
ISR_ITE
,
ISR
)
;
/* wait for ACK from slave */
if
(
msg
->
acknack
==
I2C_ACKNAK_WAITACK
)
...
...
@@ -189,23 +196,27 @@ int i2c_transfer(struct i2c_msg *msg)
goto
transfer_error_bus_busy
;
/* start receive */
ICR
&=
~
ICR_START
;
ICR
&=
~
ICR_STOP
;
if
(
msg
->
condition
==
I2C_COND_START
)
ICR
|=
ICR_START
;
if
(
msg
->
condition
==
I2C_COND_STOP
)
ICR
|=
ICR_STOP
;
if
(
msg
->
acknack
==
I2C_ACKNAK_SENDNAK
)
ICR
|=
ICR_ACKNAK
;
if
(
msg
->
acknack
==
I2C_ACKNAK_SENDACK
)
ICR
&=
~
ICR_ACKNAK
;
ICR
&=
~
ICR_ALDIE
;
ICR
|=
ICR_TB
;
writel
(
readl
(
ICR
)
&
~
ICR_START
,
ICR
);
writel
(
readl
(
ICR
)
&
~
ICR_STOP
,
ICR
);
if
(
msg
->
condition
==
I2C_COND_START
)
writel
(
readl
(
ICR
)
|
ICR_START
,
ICR
);
if
(
msg
->
condition
==
I2C_COND_STOP
)
writel
(
readl
(
ICR
)
|
ICR_STOP
,
ICR
);
if
(
msg
->
acknack
==
I2C_ACKNAK_SENDNAK
)
writel
(
readl
(
ICR
)
|
ICR_ACKNAK
,
ICR
);
if
(
msg
->
acknack
==
I2C_ACKNAK_SENDACK
)
writel
(
readl
(
ICR
)
&
~
ICR_ACKNAK
,
ICR
);
writel
(
readl
(
ICR
)
&
~
ICR_ALDIE
,
ICR
);
writel
(
readl
(
ICR
)
|
ICR_TB
,
ICR
);
/* receive register full? */
if
(
!
i2c_isr_set_cleared
(
ISR_IRF
,
0
))
goto
transfer_error_receive_timeout
;
msg
->
data
=
IDBR
;
msg
->
data
=
readl
(
IDBR
)
;
/* clear 'receive empty' state */
ISR
|
=
ISR_IRF
;
writel
(
readl
(
ISR
)
|
ISR_IRF
,
ISR
)
;
break
;
...
...
arch/arm/cpu/pxa/pxafb.c
View file @
3ba8bf7c
...
...
@@ -35,6 +35,7 @@
#include
<stdio_dev.h>
#include
<lcd.h>
#include
<asm/arch/pxa-regs.h>
#include
<asm/io.h>
/* #define DEBUG */
...
...
@@ -377,12 +378,14 @@ static void pxafb_setup_gpio (vidinfo_t *vid)
{
debug
(
"Setting GPIO for 4 bit data
\n
"
);
/* bits 58-61 */
GPDR1
|=
(
0xf
<<
26
);
GAFR1_U
=
(
GAFR1_U
&
~
(
0xff
<<
20
))
|
(
0xaa
<<
20
);
writel
(
readl
(
GPDR1
)
|
(
0xf
<<
26
),
GPDR1
);
writel
((
readl
(
GAFR1_U
)
&
~
(
0xff
<<
20
))
|
(
0xaa
<<
20
),
GAFR1_U
);
/* bits 74-77 */
GPDR2
|=
(
0xf
<<
10
);
GAFR2_L
=
(
GAFR2_L
&
~
(
0xff
<<
20
))
|
(
0xaa
<<
20
);
writel
(
readl
(
GPDR2
)
|
(
0xf
<<
10
),
GPDR2
);
writel
((
readl
(
GAFR2_L
)
&
~
(
0xff
<<
20
))
|
(
0xaa
<<
20
),
GAFR2_L
);
}
/* 8 bit interface */
...
...
@@ -391,15 +394,17 @@ static void pxafb_setup_gpio (vidinfo_t *vid)
{
debug
(
"Setting GPIO for 8 bit data
\n
"
);
/* bits 58-65 */
GPDR1
|
=
(
0x3f
<<
26
);
GPDR2
|
=
(
0x3
);
writel
(
readl
(
GPDR1
)
|
(
0x3f
<<
26
)
,
GPDR1
)
;
writel
(
readl
(
GPDR2
)
|
(
0x3
)
,
GPDR2
)
;
GAFR1_U
=
(
GAFR1_U
&
~
(
0xfff
<<
20
))
|
(
0xaaa
<<
20
);
GAFR2_L
=
(
GAFR2_L
&
~
0xf
)
|
(
0xa
);
writel
((
readl
(
GAFR1_U
)
&
~
(
0xfff
<<
20
))
|
(
0xaaa
<<
20
),
GAFR1_U
);
writel
((
readl
(
GAFR2_L
)
&
~
0xf
)
|
(
0xa
),
GAFR2_L
);
/* bits 74-77 */
GPDR2
|=
(
0xf
<<
10
);
GAFR2_L
=
(
GAFR2_L
&
~
(
0xff
<<
20
))
|
(
0xaa
<<
20
);
writel
(
readl
(
GPDR2
)
|
(
0xf
<<
10
),
GPDR2
);
writel
((
readl
(
GAFR2_L
)
&
~
(
0xff
<<
20
))
|
(
0xaa
<<
20
),
GAFR2_L
);
}
/* 16 bit interface */
...
...
@@ -407,11 +412,12 @@ static void pxafb_setup_gpio (vidinfo_t *vid)
{
debug
(
"Setting GPIO for 16 bit data
\n
"
);
/* bits 58-77 */
GPDR1
|
=
(
0x3f
<<
26
);
GPDR2
|
=
0x00003fff
;
writel
(
readl
(
GPDR1
)
|
(
0x3f
<<
26
)
,
GPDR1
)
;
writel
(
readl
(
GPDR2
)
|
0x00003fff
,
GPDR2
)
;
GAFR1_U
=
(
GAFR1_U
&
~
(
0xfff
<<
20
))
|
(
0xaaa
<<
20
);
GAFR2_L
=
(
GAFR2_L
&
0xf0000000
)
|
0x0aaaaaaa
;
writel
((
readl
(
GAFR1_U
)
&
~
(
0xfff
<<
20
))
|
(
0xaaa
<<
20
),
GAFR1_U
);
writel
((
readl
(
GAFR2_L
)
&
0xf0000000
)
|
0x0aaaaaaa
,
GAFR2_L
);
}
else
{
...
...
@@ -425,26 +431,26 @@ static void pxafb_enable_controller (vidinfo_t *vid)
debug
(
"Enabling LCD controller
\n
"
);
/* Sequence from 11.7.10 */
LCCR3
=
vid
->
pxa
.
reg_lccr3
;
LCCR2
=
vid
->
pxa
.
reg_lccr2
;
LCCR1
=
vid
->
pxa
.
reg_lccr1
;
LCCR0
=
vid
->
pxa
.
reg_lccr0
&
~
LCCR0_ENB
;
FDADR0
=
vid
->
pxa
.
fdadr0
;
FDADR1
=
vid
->
pxa
.
fdadr1
;
LCCR0
|
=
LCCR0_ENB
;
writel
(
vid
->
pxa
.
reg_lccr3
,
LCCR3
)
;
writel
(
vid
->
pxa
.
reg_lccr2
,
LCCR2
)
;
writel
(
vid
->
pxa
.
reg_lccr1
,
LCCR1
)
;
writel
(
vid
->
pxa
.
reg_lccr0
&
~
LCCR0_ENB
,
LCCR0
)
;
writel
(
vid
->
pxa
.
fdadr0
,
FDADR0
)
;
writel
(
vid
->
pxa
.
fdadr1
,
FDADR1
)
;
writel
(
readl
(
LCCR0
)
|
LCCR0_ENB
,
LCCR0
)
;
#ifdef CONFIG_CPU_MONAHANS
CKENA
|
=
CKENA_1_LCD
;
writel
(
readl
(
CKENA
)
|
CKENA_1_LCD
,
CKENA
)
;
#else
CKEN
|
=
CKEN16_LCD
;
writel
(
readl
(
CKEN
)
|
CKEN16_LCD
,
CKEN
)
;
#endif
debug
(
"FDADR0 = 0x%08x
\n
"
,
(
unsigned
int
)
FDADR0
);
debug
(
"FDADR1 = 0x%08x
\n
"
,
(
unsigned
int
)
FDADR1
);
debug
(
"LCCR0 = 0x%08x
\n
"
,
(
unsigned
int
)
LCCR0
);
debug
(
"LCCR1 = 0x%08x
\n
"
,
(
unsigned
int
)
LCCR1
);
debug
(
"LCCR2 = 0x%08x
\n
"
,
(
unsigned
int
)
LCCR2
);
debug
(
"LCCR3 = 0x%08x
\n
"
,
(
unsigned
int
)
LCCR3
);
debug
(
"FDADR0 = 0x%08x
\n
"
,
readl
(
FDADR0
)
)
;
debug
(
"FDADR1 = 0x%08x
\n
"
,
readl
(
FDADR1
)
)
;
debug
(
"LCCR0 = 0x%08x
\n
"
,
readl
(
LCCR0
)
)
;
debug
(
"LCCR1 = 0x%08x
\n
"
,
readl
(
LCCR1
)
)
;
debug
(
"LCCR2 = 0x%08x
\n
"
,
readl
(
LCCR2
)
)
;
debug
(
"LCCR3 = 0x%08x
\n
"
,
readl
(
LCCR3
)
)
;
}
static
int
pxafb_init
(
vidinfo_t
*
vid
)
...
...
arch/arm/cpu/pxa/timer.c
View file @
3ba8bf7c
...
...
@@ -26,8 +26,9 @@
* MA 02111-1307 USA
*/
#include
<common.h>
#include
<asm/arch/pxa-regs.h>
#include
<asm/io.h>
#include
<common.h>
#include
<div64.h>
#ifdef CONFIG_USE_IRQ
...
...
@@ -86,7 +87,7 @@ void __udelay (unsigned long usec)
void
reset_timer_masked
(
void
)
{
OSCR
=
0
;
writel
(
0
,
OSCR
)
;
}
ulong
get_timer_masked
(
void
)
...
...
@@ -113,7 +114,7 @@ void udelay_masked (unsigned long usec)
*/
unsigned
long
long
get_ticks
(
void
)
{
return
OSCR
;
return
readl
(
OSCR
)
;
}
/*
...
...
arch/arm/cpu/pxa/usb.c
View file @
3ba8bf7c
...
...
@@ -27,86 +27,79 @@
# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
#include
<asm/arch/pxa-regs.h>
#include
<asm/io.h>
#include
<usb.h>
int
usb_cpu_init
(
void
)
{
#if defined(CONFIG_CPU_MONAHANS)
/* Enable USB host clock. */
CKENA
|
=
(
CKENA_2_USBHOST
|
CKENA_20_UDC
);
writel
(
readl
(
CKENA
)
|
CKENA_2_USBHOST
|
CKENA_20_UDC
,
CKENA
);
udelay
(
100
);
#endif
#if defined(CONFIG_PXA27X)
/* Enable USB host clock. */
CKEN
|
=
CKEN10_USBHOST
;
writel
(
readl
(
CKEN
)
|
CKEN10_USBHOST
,
CKEN
)
;
#endif
#if defined(CONFIG_CPU_MONAHANS)
/* Configure Port 2 for Host (USB Client Registers) */
UP2OCR
=
0x3000c
;
writel
(
0x3000c
,
UP2OCR
)
;
#endif
UHCHR
|
=
UHCHR_FHR
;
writel
(
readl
(
UHCHR
)
|
UHCHR_FHR
,
UHCHR
)
;
wait_ms
(
11
);
UHCHR
&
=
~
UHCHR_FHR
;
writel
(
readl
(
UHCHR
)
&
~
UHCHR_FHR
,
UHCHR
)
;
UHCHR
|
=
UHCHR_FSBIR
;
while
(
UHCHR
&
UHCHR_FSBIR
)
writel
(
readl
(
UHCHR
)
|
UHCHR_FSBIR
,
UHCHR
)
;
while
(
readl
(
UHCHR
)
&
UHCHR_FSBIR
)
udelay
(
1
);
#if defined(CONFIG_CPU_MONAHANS)
UHCHR
&
=
~
UHCHR_SSEP0
;
writel
(
readl
(
UHCHR
)
&
~
UHCHR_SSEP0
,
UHCHR
)
;
#endif
#if defined(CONFIG_PXA27X)
UHCHR
&
=
~
UHCHR_SSEP2
;
writel
(
readl
(
UHCHR
)
&
~
UHCHR_SSEP2
,
UHCHR
)
;
#endif
UHCHR
&=
~
UHCHR_SSEP1
;
UHCHR
&=
~
UHCHR_SSE
;
writel
(
readl
(
UHCHR
)
&
~
(
UHCHR_SSEP1
|
UHCHR_SSE
),
UHCHR
);
return
0
;
}
int
usb_cpu_stop
(
void
)
{
UHCHR
|
=
UHCHR_FHR
;
writel
(
readl
(
UHCHR
)
|
UHCHR_FHR
,
UHCHR
)
;
udelay
(
11
);
UHCHR
&
=
~
UHCHR_FHR
;
writel
(
readl
(
UHCHR
)
&
~
UHCHR_FHR
,
UHCHR
)
;
UHCCOMS
|
=
1
;
writel
(
readl
(
UHCCOMS
)
|
UHCHR_FHR
,
UHCCOMS
)
;
udelay
(
10
);
#if defined(CONFIG_CPU_MONAHANS)
UHCHR
|
=
UHCHR_SSEP0
;
writel
(
readl
(
UHCHR
)
|
UHCHR_SSEP0
,
UHCHR
)
;
#endif
#if defined(CONFIG_PXA27X)
UHCHR
|
=
UHCHR_SSEP2
;
writel
(
readl
(
UHCHR
)
|
UHCHR_SSEP2
,
UHCHR
)
;
#endif
UHCHR
|=
UHCHR_SSEP1
;
UHCHR
|=
UHCHR_SSE
;
return
0
;
}
int
usb_cpu_init_fail
(
void
)
{
UHCHR
|=
UHCHR_FHR
;
udelay
(
11
);
UHCHR
&=
~
UHCHR_FHR
;
UHCCOMS
|=
1
;
udelay
(
10
);
writel
(
readl
(
UHCHR
)
|
UHCHR_SSEP1
|
UHCHR_SSE
,
UHCHR
);
#if defined(CONFIG_CPU_MONAHANS)
UHCHR
|=
UHCHR_SSEP0
;
/* Disable USB host clock. */
writel
(
readl
(
CKENA
)
&
~
(
CKENA_2_USBHOST
|
CKENA_20_UDC
),
CKENA
);
udelay
(
100
);
#endif
#if defined(CONFIG_PXA27X)
UHCHR
|=
UHCHR_SSEP2
;
/* Disable USB host clock. */
writel
(
readl
(
CKEN
)
&
~
CKEN10_USBHOST
,
CKEN
);
#endif
UHCHR
|=
UHCHR_SSEP1
;
UHCHR
|=
UHCHR_SSE
;
return
0
;
}
int
usb_cpu_init_fail
(
void
)
{
return
usb_cpu_stop
();
}
# endif
/* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) */
#endif
/* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
arch/arm/include/asm/arch-pxa/hardware.h
View file @
3ba8bf7c
...
...
@@ -21,6 +21,19 @@
#include
<linux/config.h>
#include
<asm/mach-types.h>
/*
* Define CONFIG_CPU_MONAHANS in case some CPU of the PXA3xx family is selected.
* PXA300/310/320 all have distinct register mappings in some cases, that's why
* the exact CPU has to be selected. CONFIG_CPU_MONAHANS is a helper for common
* drivers and compatibility glue with old source then.
*/
#ifndef CONFIG_CPU_MONAHANS
#if defined(CONFIG_CPU_PXA300) || \
defined(CONFIG_CPU_PXA310) || \
defined(CONFIG_CPU_PXA320)
#define CONFIG_CPU_MONAHANS
#endif
#endif
/*
* These are statically mapped PCMCIA IO space for designs using it as a
...
...
@@ -51,54 +64,6 @@
* 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff
*/
/* FIXME: Only this does work for u-boot... find out why... [RS] */
#define UBOOT_REG_FIX 1
#ifndef UBOOT_REG_FIX
#ifndef __ASSEMBLY__
#define io_p2v(x) ( ((x) | 0xbe000000) ^ (~((x) >> 1) & 0x06000000) )
#define io_v2p( x ) ( ((x) & 0x41ffffff) ^ ( ((x) & 0x06000000) << 1) )
/*
* This __REG() version gives the same results as the one above, except
* that we are fooling gcc somehow so it generates far better and smaller
* assembly code for access to contigous registers. It's a shame that gcc
* doesn't guess this by itself.
*/
#include
<asm/types.h>
typedef
struct
{
volatile
u32
offset
[
4096
];
}
__regbase
;
# define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
# define __REG(x) __REGP(io_p2v(x))
#endif
/* Let's kick gcc's ass again... */
# define __REG2(x,y) \
( __builtin_constant_p(y) ? (__REG((x) + (y))) \
: (*(volatile u32 *)((u32)&__REG(x) + (y))) )
# define __PREG(x) (io_v2p((u32)&(x)))
#else
# define __REG(x) io_p2v(x)
# define __PREG(x) io_v2p(x)
# undef io_p2v
# undef __REG
# ifndef __ASSEMBLY__
# define io_p2v(PhAdd) (PhAdd)
# define __REG(x) (*((volatile u32 *)io_p2v(x)))
# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y)))
# else
# define __REG(x) (x)
# ifdef CONFIG_CPU_MONAHANS
/* Hack to make this work with mona's pxa-regs.h */
# define __REG_2(x) (x)
# define __REG_3(x) (x)
# endif
# endif
#endif
/* UBOOT_REG_FIX */
#include
"pxa-regs.h"
#ifndef __ASSEMBLY__
...
...
arch/arm/include/asm/arch-pxa/pxa-regs.h
View file @
3ba8bf7c
This diff is collapsed.
Click to expand it.
board/colibri_pxa270/colibri_pxa270.c
View file @
3ba8bf7c
...
...
@@ -22,6 +22,7 @@
#include
<common.h>
#include
<asm/arch/hardware.h>
#include
<netdev.h>
#include
<asm/io.h>
DECLARE_GLOBAL_DATA_PTR
;
...
...
@@ -65,28 +66,30 @@ int dram_init (void)
#ifdef CONFIG_CMD_USB
int
usb_board_init
(
void
)
{
UHCHR
=
(
UHCHR
|
UHCHR_PCPL
|
UHCHR_PSPL
)
&
~
(
UHCHR_SSEP0
|
UHCHR_SSEP1
|
UHCHR_SSEP2
|
UHCHR_SSE
);
writel
((
readl
(
UHCHR
)
|
UHCHR_PCPL
|
UHCHR_PSPL
)
&
~
(
UHCHR_SSEP0
|
UHCHR_SSEP1
|
UHCHR_SSEP2
|
UHCHR_SSE
),
UHCHR
);
UHCHR
|
=
UHCHR_FSBIR
;
writel
(
readl
(
UHCHR
)
|
UHCHR_FSBIR
,
UHCHR
)
;
while
(
UHCHR
&
UHCHR_FSBIR
);
UHCHR
&
=
~
UHCHR_SSE
;
UHCHIE
=
(
UHCHIE_UPRIE
|
UHCHIE_RWIE
);
writel
(
readl
(
UHCHR
)
&
~
UHCHR_SSE
,
UHCHR
)
;
writel
(
(
UHCHIE_UPRIE
|
UHCHIE_RWIE
)
,
UHCHIE
)
;
/* Clear any OTG Pin Hold */
if
(
PSSR
&
PSSR_OTGPH
)
PSSR
|
=
PSSR_OTGPH
;
if
(
readl
(
PSSR
)
&
PSSR_OTGPH
)
writel
(
readl
(
PSSR
)
|
PSSR_OTGPH
,
PSSR
)
;
UHCRHDA
&
=
~
(
0x200
);
UHCRHDA
|
=
0x100
;
writel
(
readl
(
UHCRHDA
)
&
~
(
0x200
)
,
UHCRHDA
)
;
writel
(
readl
(
UHCRHDA
)
|
0x100
,
UHCRHDA
)
;
/* Set port power control mask bits, only 3 ports. */
UHCRHDB
|
=
(
0x7
<<
17
);
writel
(
readl
(
UHCRHDB
)
|
(
0x7
<<
17
)
,
UHCRHDB
)
;
/* enable port 2 */
UP2OCR
|=
UP2OCR_HXOE
|
UP2OCR_HXS
|
UP2OCR_DMPDE
|
UP2OCR_DPPDE
;
writel
(
readl
(
UP2OCR
)
|
UP2OCR_HXOE
|
UP2OCR_HXS
|
UP2OCR_DMPDE
|
UP2OCR_DPPDE
,
UP2OCR
);
return
0
;
}
...
...
@@ -98,14 +101,14 @@ void usb_board_init_fail(void)
void
usb_board_stop
(
void
)
{
UHCHR
|
=
UHCHR_FHR
;
writel
(
readl
(
UHCHR
)
|
UHCHR_FHR
,
UHCHR
)
;
udelay
(
11
);
UHCHR
&
=
~
UHCHR_FHR
;
writel
(
readl
(
UHCHR
)
&
~
UHCHR_FHR
,
UHCHR
)
;
UHCCOMS
|
=
1
;
writel
(
readl
(
UHCCOMS
)
|
1
,
UHCCOMS
)
;
udelay
(
10
);
CKEN
&
=
~
CKEN10_USBHOST
;
writel
(
readl
(
CKEN
)
&
~
CKEN10_USBHOST
,
CKEN
)
;
return
;
}
...
...
board/cradle/cradle.c
View file @
3ba8bf7c
...
...
@@ -28,6 +28,7 @@
#include
<asm/arch/pxa-regs.h>
#include
<common.h>
#include
<netdev.h>
#include
<asm/io.h>
DECLARE_GLOBAL_DATA_PTR
;
...
...
@@ -92,8 +93,8 @@ set_led (int led, int color)
int
shift
=
led
*
2
;
unsigned
long
mask
=
0x3
<<
shift
;
CRADLE_LED_CLR_REG
=
mask
;
/* clear bits */
CRADLE_LED_SET_REG
=
(
color
<<
shift
);
/* set bits */
writel
(
mask
,
GPCR2
)
;
/* clear bits */
writel
(
(
color
<<
shift
)
,
GPSR2
)
;
/* set bits */
udelay
(
5000
);
}
...
...
board/cradle/lowlevel_init.S
View file @
3ba8bf7c
...
...
@@ -34,10 +34,10 @@ DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
.
endm
.
macro
SET_LED
val
ldr
r6
,
=
CRADLE_LED_CLR_REG
ldr
r6
,
=
GPCR2
ldr
r7
,
=
0
str
r7
,
[
r6
]
ldr
r6
,
=
CRADLE_LED_SET_REG
ldr
r6
,
=
GPSR2
ldr
r7
,
=
\
val
str
r7
,
[
r6
]
.
endm
...
...
board/csb226/csb226.c
View file @
3ba8bf7c
...
...
@@ -26,6 +26,7 @@
#include
<common.h>
#include
<netdev.h>
#include
<asm/arch/pxa-regs.h>
#include
<asm/io.h>
DECLARE_GLOBAL_DATA_PTR
;
...
...
@@ -108,23 +109,23 @@ void csb226_set_led(int led, int state)
switch
(
led
)
{
case
0
:
if
(
state
==
1
)
{
GPCR0
|
=
CSB226_USER_LED0
;
writel
(
readl
(
GPCR0
)
|
CSB226_USER_LED0
,
GPCR0
)
;
}
else
if
(
state
==
0
)
{