Commit 3df5bea0 authored by Wolfgang Denk's avatar Wolfgang Denk
Browse files

Add support for NetSilicon NS7520 processor.

Patch by Art Shipkowski, 12 May 2005

Cleanup.
parent 7521af1c
......@@ -2,6 +2,11 @@
Changes for U-Boot 1.1.4:
======================================================================
* Cleanup
* Add support for NetSilicon NS7520 processor.
Patch by Art Shipkowski, 12 May 2005
* Add support for AP1000 board.
Patch by James MacAulay, 07 Oct 2005
......@@ -15,7 +20,7 @@ Changes for U-Boot 1.1.4:
issue - the table is aligned on a PAGE_SIZE (4096) boundary).
* Fixed compilation for ARM when using a (standard) hard-FP toolchain
Patch by Anders Larsen, 07 Oct 2005
Patch by Anders Larsen, 07 Oct 2005
* Cleanup warnings for cpu/arm720t & cpu/arm1136 files.
sed the linker scripts, rather than pre-process them.
......
......@@ -377,6 +377,10 @@ N: Robert Schwebel
E: r.schwebel@pengutronix.de
D: Support for csb226, logodl and innokom boards (PXA2xx)
N: Art Shipkowski
E: art@videon-central.com
D: Support for NetSilicon NS7520
N: Yasushi Shoji
E: yashi@atmark-techno.com
D: Support for Xilinx MicroBlaze, for Atmark Techno SUZAKU FPGA board
......
......@@ -297,9 +297,9 @@ The following options need to be configured:
CONFIG_FADS850SAR CONFIG_NX823 CONFIG_WALNUT
CONFIG_FADS860T CONFIG_OCRTC CONFIG_ZPC1900
CONFIG_FLAGADM CONFIG_ORSG CONFIG_ZUMA
CONFIG_FPS850L CONFIG_OXC
CONFIG_FPS850L CONFIG_OXC
CONFIG_FPS860L CONFIG_PCI405
ARM based boards:
-----------------
......
This diff is collapsed.
......@@ -20,22 +20,22 @@
*/
#define AP1xx_FPGA_REV_ADDR 0x29000000
#define AP1xx_PLATFORM_MASK 0xFF000000
#define AP100_BASELINE_PLATFORM 0x01000000
#define AP1xx_QUADGE_PLATFORM 0x02000000
#define AP1xx_MGT_REF_PLATFORM 0x03000000
#define AP1xx_STANDARD_PLATFORM 0x04000000
#define AP1xx_DUAL_PLATFORM 0x05000000
#define AP1xx_PLATFORM_MASK 0xFF000000
#define AP100_BASELINE_PLATFORM 0x01000000
#define AP1xx_QUADGE_PLATFORM 0x02000000
#define AP1xx_MGT_REF_PLATFORM 0x03000000
#define AP1xx_STANDARD_PLATFORM 0x04000000
#define AP1xx_DUAL_PLATFORM 0x05000000
#define AP1xx_BASE_SRAM_PLATFORM 0x06000000
#define AP1000_BASELINE_PLATFORM 0x21000000
#define AP1xx_TESTPLATFORM_MASK 0xC0000000
#define AP1xx_PCI_PCB_TESTPLATFORM 0xC0000000
#define AP1xx_TESTPLATFORM_MASK 0xC0000000
#define AP1xx_PCI_PCB_TESTPLATFORM 0xC0000000
#define AP1xx_DUAL_GE_MEZZ_TESTPLATFORM 0xC1000000
#define AP1xx_SFP_MEZZ_TESTPLATFORM 0xC2000000
#define AP1xx_SFP_MEZZ_TESTPLATFORM 0xC2000000
#define AP1000_PCI_PCB_TESTPLATFORM 0xC3000000
#define AP1000_PCI_PCB_TESTPLATFORM 0xC3000000
#define AP1xx_TARGET_MASK 0x00FF0000
#define AP1xx_AP107_TARGET 0x00010000
......@@ -46,18 +46,18 @@
#define AP1xx_UNKNOWN_STR "Unknown"
#define AP1xx_PLATFORM_STR " Platform"
#define AP1xx_PLATFORM_STR " Platform"
#define AP1xx_BASELINE_PLATFORM_STR "Baseline"
#define AP1xx_QUADGE_PLATFORM_STR "Quad GE"
#define AP1xx_MGT_REF_PLATFORM_STR "MGT Reference"
#define AP1xx_STANDARD_PLATFORM_STR "Standard"
#define AP1xx_DUAL_PLATFORM_STR "Dual"
#define AP1xx_DUAL_PLATFORM_STR "Dual"
#define AP1xx_BASE_SRAM_PLATFORM_STR "Baseline with SRAM"
#define AP1xx_TESTPLATFORM_STR " Test Platform"
#define AP1xx_PCI_PCB_TESTPLATFORM_STR "Base"
#define AP1xx_TESTPLATFORM_STR " Test Platform"
#define AP1xx_PCI_PCB_TESTPLATFORM_STR "Base"
#define AP1xx_DUAL_GE_MEZZ_TESTPLATFORM_STR "Dual GE Mezzanine"
#define AP1xx_SFP_MEZZ_TESTPLATFORM_STR "SFP Mezzanine"
#define AP1xx_SFP_MEZZ_TESTPLATFORM_STR "SFP Mezzanine"
#define AP1xx_TARGET_STR " Board"
#define AP1xx_AP107_TARGET_STR "AP107"
......@@ -78,84 +78,84 @@
*/
#define AP1000_SYSACE_REGBASE 0x28000000
#define SYSACE_STATREG0 0x04 // 7:0
#define SYSACE_STATREG1 0x05 // 15:8
#define SYSACE_STATREG2 0x06 // 23:16
#define SYSACE_STATREG3 0x07 // 31:24
#define SYSACE_STATREG0 0x04 /* 7:0 */
#define SYSACE_STATREG1 0x05 /* 15:8 */
#define SYSACE_STATREG2 0x06 /* 23:16 */
#define SYSACE_STATREG3 0x07 /* 31:24 */
#define SYSACE_ERRREG0 0x08 // 7:0
#define SYSACE_ERRREG1 0x09 // 15:8
#define SYSACE_ERRREG2 0x0a // 23:16
#define SYSACE_ERRREG3 0x0b // 31:24
#define SYSACE_ERRREG0 0x08 /* 7:0 */
#define SYSACE_ERRREG1 0x09 /* 15:8 */
#define SYSACE_ERRREG2 0x0a /* 23:16 */
#define SYSACE_ERRREG3 0x0b /* 31:24 */
#define SYSACE_CTRLREG0 0x18 // 7:0
#define SYSACE_CTRLREG1 0x19 // 15:8
#define SYSACE_CTRLREG2 0x1A // 23:16
#define SYSACE_CTRLREG3 0x1B // 31:24
#define SYSACE_CTRLREG0 0x18 /* 7:0 */
#define SYSACE_CTRLREG1 0x19 /* 15:8 */
#define SYSACE_CTRLREG2 0x1A /* 23:16 */
#define SYSACE_CTRLREG3 0x1B /* 31:24 */
/*
* Software reconfig thing
*/
#define SW_BYTE_SECTOR_ADDR 0x24FE0000
#define SW_BYTE_SECTOR_OFFSET 0x0001FFFF
#define SW_BYTE_SECTOR_SIZE 0x00020000
#define SW_BYTE_MASK 0x00000003
#define SW_BYTE_SECTOR_ADDR 0x24FE0000
#define SW_BYTE_SECTOR_OFFSET 0x0001FFFF
#define SW_BYTE_SECTOR_SIZE 0x00020000
#define SW_BYTE_MASK 0x00000003
#define DEFAULT_TEMP_ADDR 0x00100000
#define DEFAULT_TEMP_ADDR 0x00100000
#define AP1000_CPLD_BASE 0x26000000
#define AP1000_CPLD_BASE 0x26000000
/* PowerSpan II Stuff */
#define PSII_SYNC() asm("eieio")
#define PSPAN_BASEADDR 0x30000000
#define EEPROM_DEFAULT { 0x01, /* Byte 0 - Long Load = 0x02, short = 01, use 0xff for try no load */ \
0x0,0x0,0x0, /* Bytes 1 - 3 Power span reserved */ \
0x0, /* Byte 4 - Powerspan reserved - start of short load */ \
0x0F, /* Byte 5 - Enable PCI 1 & 2 as Bus masters and Memory targets. */ \
0x0E, /* Byte 6 - PCI 1 Target image prefetch - on for image 0,1,2, off for i20 & 3. */ \
0x00, 0x00, /* Byte 7,8 - PCI-1 Subsystem ID - */ \
0x00, 0x00, /* Byte 9,10 - PCI-1 Subsystem Vendor Id - */ \
0x00, /* Byte 11 - No PCI interrupt generation on PCI-1 PCI-2 int A */ \
0x1F, /* Byte 12 - PCI-1 enable bridge registers, all target images */ \
0xBA, /* Byte 13 - Target 0 image 128 Meg(Ram), Target 1 image 64 Meg. (config Flash/CPLD )*/ \
0xA0, /* Byte 14 - Target 2 image 64 Meg(program Flash), target 3 64k. */ \
0x00, /* Byte 15 - Vital Product Data Disabled. */ \
0x88, /* Byte 16 - PCI arbiter config complete, all requests routed through PCI-1, Unlock PCI-1 */ \
0x40, /* Byte 17 - Interrupt direction control - PCI-1 Int A out, everything else in. */ \
0x00, /* Byte 18 - I2O disabled */ \
0x00, /* Byte 19 - PCI-2 Target image prefetch - off for all images. */ \
0x00,0x00, /* Bytes 20,21 - PCI 2 Subsystem Id */ \
0x00,0x00, /* Bytes 22,23 - PCI 2 Subsystem Vendor id */ \
0x0C, /* Byte 24 - PCI-2 BAR enables, target image 0, & 1 */ \
0xBB, /* Byte 25 - PCI-2 target 0 - 128 Meg(Ram), target 1 - 128 Meg (program/config flash) */ \
0x00, /* Byte 26 - PCI-2 target 2 & 3 unused. */ \
0x00,0x00,0x00,0x00,0x00, /* Bytes 27,28,29,30, 31 - Reserved */ \
/* Long Load Information */ \
0x82,0x60, /* Bytes 32,33 - PCI-1 Device ID - Powerspan II */ \
0x10,0xE3, /* Bytes 24,35 - PCI-1 Vendor ID - Tundra */ \
0x06, /* Byte 36 - PCI-1 Class Base - Bridge device. */ \
0x80, /* Byte 37 - PCI-1 Class sub class - Other bridge. */ \
0x00, /* Byte 38 - PCI-1 Class programing interface - Other bridge */ \
0x01, /* Byte 39 - Power span revision 1. */ \
0x6E, /* Byte 40 - PB SI0 enabled, translation enabled, decode enabled, 64 Meg */ \
0x40, /* Byte 41 - PB SI0 memory command mode, PCI-1 dest */ \
0x22, /* Byte 42 - Prefetch discard after read, PCI-little endian conversion, 32 byte prefetch */ \
0x00,0x00, /* Bytes 43, 44 - Translation address for SI0, set to zero for now. */ \
0x0E, /* Byte 45 - Translation address (0) and PB bus master enables - all. */ \
0x2c,00,00, /* Bytes 46,47,48 - PB SI0 processor base address - 0x2C000000 */ \
0x30,00,00, /* Bytes 49,50,51 - PB Address for Powerspan registers - 0x30000000, big Endian */ \
0x82,0x60, /* Bytes 52, 53 - PCI-2 Device ID - Powerspan II */ \
0x10,0xE3, /* Bytes 54,55 - PCI 2 Vendor Id - Tundra */ \
0x06, /* Byte 56 - PCI-2 Class Base - Bridge device */ \
0x80, /* Byte 57 - PCI-2 Class sub class - Other Bridge. */ \
0x00, /* Byte 58 - PCI-2 class programming interface - Other bridge */ \
0x01, /* Byte 59 - PCI-2 class revision 1 */ \
0x00,0x00,0x00,0x00 }; /* Bytes 60,61, 62, 63 - Powerspan reserved */
#define EEPROM_LENGTH 64 /* Long Load */
#define I2C_SENSOR_DEV 0x9
#define EEPROM_DEFAULT { 0x01, /* Byte 0 - Long Load = 0x02, short = 01, use 0xff for try no load */ \
0x0,0x0,0x0, /* Bytes 1 - 3 Power span reserved */ \
0x0, /* Byte 4 - Powerspan reserved - start of short load */ \
0x0F, /* Byte 5 - Enable PCI 1 & 2 as Bus masters and Memory targets. */ \
0x0E, /* Byte 6 - PCI 1 Target image prefetch - on for image 0,1,2, off for i20 & 3. */ \
0x00, 0x00, /* Byte 7,8 - PCI-1 Subsystem ID - */ \
0x00, 0x00, /* Byte 9,10 - PCI-1 Subsystem Vendor Id - */ \
0x00, /* Byte 11 - No PCI interrupt generation on PCI-1 PCI-2 int A */ \
0x1F, /* Byte 12 - PCI-1 enable bridge registers, all target images */ \
0xBA, /* Byte 13 - Target 0 image 128 Meg(Ram), Target 1 image 64 Meg. (config Flash/CPLD )*/ \
0xA0, /* Byte 14 - Target 2 image 64 Meg(program Flash), target 3 64k. */ \
0x00, /* Byte 15 - Vital Product Data Disabled. */ \
0x88, /* Byte 16 - PCI arbiter config complete, all requests routed through PCI-1, Unlock PCI-1 */ \
0x40, /* Byte 17 - Interrupt direction control - PCI-1 Int A out, everything else in. */ \
0x00, /* Byte 18 - I2O disabled */ \
0x00, /* Byte 19 - PCI-2 Target image prefetch - off for all images. */ \
0x00,0x00, /* Bytes 20,21 - PCI 2 Subsystem Id */ \
0x00,0x00, /* Bytes 22,23 - PCI 2 Subsystem Vendor id */ \
0x0C, /* Byte 24 - PCI-2 BAR enables, target image 0, & 1 */ \
0xBB, /* Byte 25 - PCI-2 target 0 - 128 Meg(Ram), target 1 - 128 Meg (program/config flash) */ \
0x00, /* Byte 26 - PCI-2 target 2 & 3 unused. */ \
0x00,0x00,0x00,0x00,0x00, /* Bytes 27,28,29,30, 31 - Reserved */ \
/* Long Load Information */ \
0x82,0x60, /* Bytes 32,33 - PCI-1 Device ID - Powerspan II */ \
0x10,0xE3, /* Bytes 24,35 - PCI-1 Vendor ID - Tundra */ \
0x06, /* Byte 36 - PCI-1 Class Base - Bridge device. */ \
0x80, /* Byte 37 - PCI-1 Class sub class - Other bridge. */ \
0x00, /* Byte 38 - PCI-1 Class programing interface - Other bridge */ \
0x01, /* Byte 39 - Power span revision 1. */ \
0x6E, /* Byte 40 - PB SI0 enabled, translation enabled, decode enabled, 64 Meg */ \
0x40, /* Byte 41 - PB SI0 memory command mode, PCI-1 dest */ \
0x22, /* Byte 42 - Prefetch discard after read, PCI-little endian conversion, 32 byte prefetch */ \
0x00,0x00, /* Bytes 43, 44 - Translation address for SI0, set to zero for now. */ \
0x0E, /* Byte 45 - Translation address (0) and PB bus master enables - all. */ \
0x2c,00,00, /* Bytes 46,47,48 - PB SI0 processor base address - 0x2C000000 */ \
0x30,00,00, /* Bytes 49,50,51 - PB Address for Powerspan registers - 0x30000000, big Endian */ \
0x82,0x60, /* Bytes 52, 53 - PCI-2 Device ID - Powerspan II */ \
0x10,0xE3, /* Bytes 54,55 - PCI 2 Vendor Id - Tundra */ \
0x06, /* Byte 56 - PCI-2 Class Base - Bridge device */ \
0x80, /* Byte 57 - PCI-2 Class sub class - Other Bridge. */ \
0x00, /* Byte 58 - PCI-2 class programming interface - Other bridge */ \
0x01, /* Byte 59 - PCI-2 class revision 1 */ \
0x00,0x00,0x00,0x00 }; /* Bytes 60,61, 62, 63 - Powerspan reserved */
#define EEPROM_LENGTH 64 /* Long Load */
#define I2C_SENSOR_DEV 0x9
#define I2C_SENSOR_CHIP_SEL 0x4
/*
......
This diff is collapsed.
......@@ -25,10 +25,10 @@
#include <asm/mmu.h>
.globl ext_bus_cntlr_init
.globl ext_bus_cntlr_init
ext_bus_cntlr_init:
blr
blr
.globl sdram_init
.globl sdram_init
sdram_init:
blr
blr
......@@ -30,105 +30,121 @@
#define PCI_IO_82559ER_CSR_BASE 0x40000200
/** AP1100 specific values */
#define PSII_BASE 0x30000000 /**< PowerSpan II dual bridge local bus register address */
#define PSII_CONFIG_ADDR 0x30000290 /**< PowerSpan II Configuration Cycle Address configuration register */
#define PSII_CONFIG_DATA 0x30000294 /**< PowerSpan II Configuration Cycle Data register. */
#define PSII_CONFIG_DEST_PCI2 0x01000000 /**< PowerSpan II configuration cycle destination selection, set for PCI2 bus */
#define PSII_PCI_MEM_BASE 0x30200000 /**< Local Bus address for start of PCI memory space on PCI2 bus. */
#define PSII_PCI_MEM_SIZE 0x1BE00000 /**< PCI Memory space about 510 Meg. */
#define AP1000_SYS_MEM_START 0x00000000 /**< System memory starts at 0. */
#define AP1000_SYS_MEM_SIZE 0x08000000 /**< System memory is 128 Meg. */
#define PSII_BASE 0x30000000 /**< PowerSpan II dual bridge local bus register address */
#define PSII_CONFIG_ADDR 0x30000290 /**< PowerSpan II Configuration Cycle Address configuration register */
#define PSII_CONFIG_DATA 0x30000294 /**< PowerSpan II Configuration Cycle Data register. */
#define PSII_CONFIG_DEST_PCI2 0x01000000 /**< PowerSpan II configuration cycle destination selection, set for PCI2 bus */
#define PSII_PCI_MEM_BASE 0x30200000 /**< Local Bus address for start of PCI memory space on PCI2 bus. */
#define PSII_PCI_MEM_SIZE 0x1BE00000 /**< PCI Memory space about 510 Meg. */
#define AP1000_SYS_MEM_START 0x00000000 /**< System memory starts at 0. */
#define AP1000_SYS_MEM_SIZE 0x08000000 /**< System memory is 128 Meg. */
/* static int G_verbosity_level = 1; */
#define G_verbosity_level 1
void write1(unsigned long addr, unsigned char val) {
volatile unsigned char* p = (volatile unsigned char*)addr;
void write1 (unsigned long addr, unsigned char val)
{
volatile unsigned char *p = (volatile unsigned char *) addr;
if(G_verbosity_level > 1)
printf("write1: addr=%08x val=%02x\n", (unsigned int)addr, val);
*p = val;
asm("eieio");
if (G_verbosity_level > 1)
printf ("write1: addr=%08x val=%02x\n", (unsigned int) addr,
val);
*p = val;
asm ("eieio");
}
unsigned char read1(unsigned long addr) {
unsigned char val;
volatile unsigned char* p = (volatile unsigned char*)addr;
if(G_verbosity_level > 1)
printf("read1: addr=%08x ", (unsigned int)addr);
val = *p;
asm("eieio");
if(G_verbosity_level > 1)
printf("val=%08x\n", val);
return val;
unsigned char read1 (unsigned long addr)
{
unsigned char val;
volatile unsigned char *p = (volatile unsigned char *) addr;
if (G_verbosity_level > 1)
printf ("read1: addr=%08x ", (unsigned int) addr);
val = *p;
asm ("eieio");
if (G_verbosity_level > 1)
printf ("val=%08x\n", val);
return val;
}
void write2(unsigned long addr, unsigned short val) {
volatile unsigned short* p = (volatile unsigned short*)addr;
void write2 (unsigned long addr, unsigned short val)
{
volatile unsigned short *p = (volatile unsigned short *) addr;
if(G_verbosity_level > 1)
printf("write2: addr=%08x val=%04x -> *p=%04x\n", (unsigned int)addr, val,
((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8));
if (G_verbosity_level > 1)
printf ("write2: addr=%08x val=%04x -> *p=%04x\n",
(unsigned int) addr, val,
((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8));
*p = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
asm("eieio");
*p = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
asm ("eieio");
}
unsigned short read2(unsigned long addr) {
unsigned short val;
volatile unsigned short* p = (volatile unsigned short*)addr;
if(G_verbosity_level > 1)
printf("read2: addr=%08x ", (unsigned int)addr);
val = *p;
val = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
asm("eieio");
if(G_verbosity_level > 1)
printf("*p=%04x -> val=%04x\n",
((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8), val);
return val;
unsigned short read2 (unsigned long addr)
{
unsigned short val;
volatile unsigned short *p = (volatile unsigned short *) addr;
if (G_verbosity_level > 1)
printf ("read2: addr=%08x ", (unsigned int) addr);
val = *p;
val = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
asm ("eieio");
if (G_verbosity_level > 1)
printf ("*p=%04x -> val=%04x\n",
((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8), val);
return val;
}
void write4(unsigned long addr, unsigned long val) {
volatile unsigned long* p = (volatile unsigned long*)addr;
if(G_verbosity_level > 1)
printf("write4: addr=%08x val=%08x -> *p=%08x\n", (unsigned int)addr, (unsigned int)val,
(unsigned int)(((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8)));
*p = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
asm("eieio");
void write4 (unsigned long addr, unsigned long val)
{
volatile unsigned long *p = (volatile unsigned long *) addr;
if (G_verbosity_level > 1)
printf ("write4: addr=%08x val=%08x -> *p=%08x\n",
(unsigned int) addr, (unsigned int) val,
(unsigned int) (((val & 0xFF000000) >> 24) |
((val & 0x000000FF) << 24) |
((val & 0x00FF0000) >> 8) |
((val & 0x0000FF00) << 8)));
*p = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
asm ("eieio");
}
unsigned long read4(unsigned long addr) {
unsigned long val;
volatile unsigned long* p = (volatile unsigned long*)addr;
if(G_verbosity_level > 1)
printf("read4: addr=%08x", (unsigned int)addr);
val = *p;
val = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
asm("eieio");
if(G_verbosity_level > 1)
printf("*p=%04x -> val=%04x\n",
(unsigned int)(((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8)), (unsigned int)val);
return val;
unsigned long read4 (unsigned long addr)
{
unsigned long val;
volatile unsigned long *p = (volatile unsigned long *) addr;
if (G_verbosity_level > 1)
printf ("read4: addr=%08x", (unsigned int) addr);
val = *p;
val = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
asm ("eieio");
if (G_verbosity_level > 1)
printf ("*p=%04x -> val=%04x\n",
(unsigned int) (((val & 0xFF000000) >> 24) |
((val & 0x000000FF) << 24) |
((val & 0x00FF0000) >> 8) |
((val & 0x0000FF00) << 8)),
(unsigned int) val);
return val;
}
void write4be(unsigned long addr, unsigned long val) {
volatile unsigned long* p = (volatile unsigned long*)addr;
void write4be (unsigned long addr, unsigned long val)
{
volatile unsigned long *p = (volatile unsigned long *) addr;
if(G_verbosity_level > 1)
printf("write4: addr=%08x val=%08x\n", (unsigned int)addr, (unsigned int)val);
*p = val;
asm("eieio");
if (G_verbosity_level > 1)
printf ("write4: addr=%08x val=%08x\n", (unsigned int) addr,
(unsigned int) val);
*p = val;
asm ("eieio");
}
/** One byte configuration write on PSII.
......@@ -140,21 +156,14 @@ void write4be(unsigned long addr, unsigned long val) {
* @param val Address of location for received byte.
* @return Always Zero.
*/
static int psII_read_config_byte(
struct pci_controller *hose,
pci_dev_t dev,
int reg,
u8 *val)
static int psII_read_config_byte (struct pci_controller *hose,
pci_dev_t dev, int reg, u8 * val)
{
write4be(PSII_CONFIG_ADDR,
PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS(dev) << 16) |
(PCI_DEV(dev) << 11) |
(PCI_FUNC(dev) << 8) |
((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
*val = read1(PSII_CONFIG_DATA+(reg&0x03));
return(0);
write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
*val = read1 (PSII_CONFIG_DATA + (reg & 0x03));
return (0);
}
/** One byte configuration write on PSII.
......@@ -166,22 +175,15 @@ static int psII_read_config_byte(
* @param val Output byte.
* @return Always Zero.
*/
static int psII_write_config_byte(
struct pci_controller *hose,
pci_dev_t dev,
int reg,
u8 val)
static int psII_write_config_byte (struct pci_controller *hose,
pci_dev_t dev, int reg, u8 val)
{
write4be(PSII_CONFIG_ADDR,
PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS(dev) << 16) |
(PCI_DEV(dev) << 11) |
(PCI_FUNC(dev) << 8) |
((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
write1(PSII_CONFIG_DATA+(reg&0x03),(unsigned char )val);
write1 (PSII_CONFIG_DATA + (reg & 0x03), (unsigned char) val);
return(0);
return (0);
}
/** One word (16 bit) configuration read on PSII.
......@@ -193,21 +195,14 @@ static int psII_write_config_byte(
* @param val Address of location for received word.
* @return Always Zero.
*/
static int psII_read_config_word(
struct pci_controller *hose,
pci_dev_t dev,
int reg,
u16 *val)
static int psII_read_config_word (struct pci_controller *hose,
pci_dev_t dev, int reg, u16 * val)
{
write4be(PSII_CONFIG_ADDR,
PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS(dev) << 16) |
(PCI_DEV(dev) << 11) |
(PCI_FUNC(dev) << 8) |
((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
*val = read2(PSII_CONFIG_DATA+(reg&0x03));
return(0);
write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
*val = read2 (PSII_CONFIG_DATA + (reg & 0x03));
return (0);
}
/** One word (16 bit) configuration write on PSII.
......@@ -219,22 +214,15 @@ static int psII_read_config_word(
* @param val Output word.
* @return Always Zero.
*/
static int psII_write_config_word(
struct pci_controller *hose,
pci_dev_t dev,
int reg,
u16 val)
static int psII_write_config_word (struct pci_controller *hose,
pci_dev_t dev, int reg, u16 val)
{
write4be(PSII_CONFIG_ADDR,
PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS(dev) << 16) |
(PCI_DEV(dev) << 11) |
(PCI_FUNC(dev) << 8) |
((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
write2(PSII_CONFIG_DATA+(reg&0x03),(unsigned short )val);
write2 (PSII_CONFIG_DATA + (reg & 0x03), (unsigned short) val);
return(0);
return (0);
}
/** One DWord (32 bit) configuration read on PSII.
......@@ -246,21 +234,14 @@ static int psII_write_config_word(
* @param val Address of location for received byte.
* @return Always Zero.
*/
static int psII_read_config_dword(
struct pci_controller *hose,
pci_dev_t dev,
int reg,
u32 *val)
static int psII_read_config_dword (struct pci_controller *hose,
pci_dev_t dev, int reg, u32 * val)
{
write4be(PSII_CONFIG_ADDR,
PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
(PCI_BUS(dev) << 16) |
(PCI_DEV(dev) << 11) |
(PCI_FUNC(dev) << 8) |
((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */