Commit 416fef1a authored by wdenk's avatar wdenk
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Initial revision

parent 717b5aad
/*
* include/asm-ppc/cache.h
*/
#ifndef __ARCH_PPC_CACHE_H
#define __ARCH_PPC_CACHE_H
#include <linux/config.h>
#include <asm/processor.h>
/* bytes per L1 cache line */
#if !defined(CONFIG_8xx) || defined(CONFIG_8260)
#if defined(CONFIG_PPC64BRIDGE)
#define L1_CACHE_BYTES 128
#else
#define L1_CACHE_BYTES 32
#endif /* PPC64 */
#else
#define L1_CACHE_BYTES 16
#endif /* !8xx || 8260 */
#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
#define L1_CACHE_PAGES 8
#define SMP_CACHE_BYTES L1_CACHE_BYTES
#ifdef MODULE
#define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES)))
#else
#define __cacheline_aligned \
__attribute__((__aligned__(L1_CACHE_BYTES), \
__section__(".data.cacheline_aligned")))
#endif
#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
extern void flush_dcache_range(unsigned long start, unsigned long stop);
extern void clean_dcache_range(unsigned long start, unsigned long stop);
extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
#ifdef CFG_INIT_RAM_LOCK
extern void unlock_ram_in_cache(void);
#endif /* CFG_INIT_RAM_LOCK */
#endif /* __ASSEMBLY__ */
/* prep registers for L2 */
#define CACHECRBA 0x80000823 /* Cache configuration register address */
#define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */
#define L2CACHE_512KB 0x00 /* 512KB */
#define L2CACHE_256KB 0x01 /* 256KB */
#define L2CACHE_1MB 0x02 /* 1MB */
#define L2CACHE_NONE 0x03 /* NONE */
#define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */
#ifdef CONFIG_8xx
/* Cache control on the MPC8xx is provided through some additional
* special purpose registers.
*/
#define IC_CST 560 /* Instruction cache control/status */
#define IC_ADR 561 /* Address needed for some commands */
#define IC_DAT 562 /* Read-only data register */
#define DC_CST 568 /* Data cache control/status */
#define DC_ADR 569 /* Address needed for some commands */
#define DC_DAT 570 /* Read-only data register */
/* Commands. Only the first few are available to the instruction cache.
*/
#define IDC_ENABLE 0x02000000 /* Cache enable */
#define IDC_DISABLE 0x04000000 /* Cache disable */
#define IDC_LDLCK 0x06000000 /* Load and lock */
#define IDC_UNLINE 0x08000000 /* Unlock line */
#define IDC_UNALL 0x0a000000 /* Unlock all */
#define IDC_INVALL 0x0c000000 /* Invalidate all */
#define DC_FLINE 0x0e000000 /* Flush data cache line */
#define DC_SFWT 0x01000000 /* Set forced writethrough mode */
#define DC_CFWT 0x03000000 /* Clear forced writethrough mode */
#define DC_SLES 0x05000000 /* Set little endian swap mode */
#define DC_CLES 0x07000000 /* Clear little endian swap mode */
/* Status.
*/
#define IDC_ENABLED 0x80000000 /* Cache is enabled */
#define IDC_CERR1 0x00200000 /* Cache error 1 */
#define IDC_CERR2 0x00100000 /* Cache error 2 */
#define IDC_CERR3 0x00080000 /* Cache error 3 */
#define DC_DFWT 0x40000000 /* Data cache is forced write through */
#define DC_LES 0x20000000 /* Caches are little endian mode */
#endif /* CONFIG_8xx */
#endif
/* Core.h - Basic core logic functions and definitions */
/* Copyright Galileo Technology. */
/*
DESCRIPTION
This header file contains simple read/write macros for addressing
the SDRAM, devices, GT`s internal registers and PCI (using the PCI`s address
space). The macros take care of Big/Little endian conversions.
*/
#ifndef __INCcoreh
#define __INCcoreh
/* includes */
#include "gt64260R.h"
extern unsigned int INTERNAL_REG_BASE_ADDR;
/*
* GT-6426x variants
*/
#define GT_64260 0 /* includes both 64260A and 64260B */
#define GT_64261 1
#if (CFG_GT_6426x == GT_64260)
#ifdef CONFIG_ETHER_PORT_MII
#define GAL_ETH_DEVS 2
#else
#define GAL_ETH_DEVS 3
#endif
#elif (CFG_GT_6426x == GT_64261)
#define GAL_ETH_DEVS 2
#else
#define GAL_ETH_DEVS 3 /* default to a 64260 */
#endif
/****************************************/
/* GENERAL Definitions */
/****************************************/
#define NO_BIT 0x00000000
#define BIT0 0x00000001
#define BIT1 0x00000002
#define BIT2 0x00000004
#define BIT3 0x00000008
#define BIT4 0x00000010
#define BIT5 0x00000020
#define BIT6 0x00000040
#define BIT7 0x00000080
#define BIT8 0x00000100
#define BIT9 0x00000200
#define BIT10 0x00000400
#define BIT11 0x00000800
#define BIT12 0x00001000
#define BIT13 0x00002000
#define BIT14 0x00004000
#define BIT15 0x00008000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
#define _1K 0x00000400
#define _2K 0x00000800
#define _4K 0x00001000
#define _8K 0x00002000
#define _16K 0x00004000
#define _32K 0x00008000
#define _64K 0x00010000
#define _128K 0x00020000
#define _256K 0x00040000
#define _512K 0x00080000
#define _1M 0x00100000
#define _2M 0x00200000
#define _3M 0x00300000
#define _4M 0x00400000
#define _5M 0x00500000
#define _6M 0x00600000
#define _7M 0x00700000
#define _8M 0x00800000
#define _9M 0x00900000
#define _10M 0x00a00000
#define _11M 0x00b00000
#define _12M 0x00c00000
#define _13M 0x00d00000
#define _14M 0x00e00000
#define _15M 0x00f00000
#define _16M 0x01000000
#define _32M 0x02000000
#define _64M 0x04000000
#define _128M 0x08000000
#define _256M 0x10000000
#define _512M 0x20000000
#define _1G 0x40000000
#define _2G 0x80000000
typedef enum _bool{false,true} bool;
/* Little to Big endian conversion macros */
#ifdef LE /* Little Endian */
#define SHORT_SWAP(X) (X)
#define WORD_SWAP(X) (X)
#define LONG_SWAP(X) ((l64)(X))
#else /* Big Endian */
#define SHORT_SWAP(X) ((X <<8 ) | (X >> 8))
#define WORD_SWAP(X) (((X)&0xff)<<24)+ \
(((X)&0xff00)<<8)+ \
(((X)&0xff0000)>>8)+ \
(((X)&0xff000000)>>24)
#define LONG_SWAP(X) ( (l64) (((X)&0xffULL)<<56)+ \
(((X)&0xff00ULL)<<40)+ \
(((X)&0xff0000ULL)<<24)+ \
(((X)&0xff000000ULL)<<8)+ \
(((X)&0xff00000000ULL)>>8)+ \
(((X)&0xff0000000000ULL)>>24)+ \
(((X)&0xff000000000000ULL)>>40)+ \
(((X)&0xff00000000000000ULL)>>56))
#endif
#ifndef NULL
#define NULL 0
#endif
/* Those two definitions were defined to be compatible with MIPS */
#define NONE_CACHEABLE 0x00000000
#define CACHEABLE 0x00000000
/* 750 cache line */
#define CACHE_LINE_SIZE 32
#define CACHELINE_MASK_BITS (CACHE_LINE_SIZE - 1)
#define CACHELINE_ROUNDUP(A) (((A)+CACHELINE_MASK_BITS) & ~CACHELINE_MASK_BITS)
/* Read/Write to/from GT`s internal registers */
#define GT_REG_READ(offset, pData) \
*pData = ( *((volatile unsigned int *)(NONE_CACHEABLE | \
INTERNAL_REG_BASE_ADDR | (offset))) ) ; \
*pData = WORD_SWAP(*pData)
#define GTREGREAD(offset) \
(WORD_SWAP( *((volatile unsigned int *)(NONE_CACHEABLE | \
INTERNAL_REG_BASE_ADDR | (offset))) ))
#define GT_REG_WRITE(offset, data) \
*((unsigned int *)( INTERNAL_REG_BASE_ADDR | (offset))) = \
WORD_SWAP(data)
/* Write 32/16/8 bit */
#define WRITE_CHAR(address, data) \
*((unsigned char *)(address)) = data
#define WRITE_SHORT(address, data) \
*((unsigned short *)(address)) = data
#define WRITE_WORD(address, data) \
*((unsigned int *)(address)) = data
/* Read 32/16/8 bits - returns data in variable. */
#define READ_CHAR(address, pData) \
*pData = *((volatile unsigned char *)(address))
#define READ_SHORT(address, pData) \
*pData = *((volatile unsigned short *)(address))
#define READ_WORD(address, pData) \
*pData = *((volatile unsigned int *)(address))
/* Read 32/16/8 bit - returns data direct. */
#define READCHAR(address) \
*((volatile unsigned char *)((address) | NONE_CACHEABLE))
#define READSHORT(address) \
*((volatile unsigned short *)((address) | NONE_CACHEABLE))
#define READWORD(address) \
*((volatile unsigned int *)((address) | NONE_CACHEABLE))
/* Those two Macros were defined to be compatible with MIPS */
#define VIRTUAL_TO_PHY(x) (((unsigned int)x) & 0xffffffff)
#define PHY_TO_VIRTUAL(x) (((unsigned int)x) | NONE_CACHEABLE)
/* SET_REG_BITS(regOffset,bits) -
gets register offset and bits: a 32bit value. It set to logic '1' in the
internal register the bits which given as an input example:
SET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
'1' in register 0x840 while the other bits stays as is. */
#define SET_REG_BITS(regOffset,bits) \
*(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR | \
regOffset) |= (unsigned int)WORD_SWAP(bits)
/* RESET_REG_BITS(regOffset,bits) -
gets register offset and bits: a 32bit value. It set to logic '0' in the
internal register the bits which given as an input example:
RESET_REG_BITS(0x840,BIT3 | BIT24 | BIT30) - set bits: 3,24 and 30 to logic
'0' in register 0x840 while the other bits stays as is. */
#define RESET_REG_BITS(regOffset,bits) \
*(unsigned int*)(NONE_CACHEABLE | INTERNAL_REG_BASE_ADDR \
| regOffset) &= ~( (unsigned int)WORD_SWAP(bits) )
#endif /* __INCcoreh */
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