Commit 445a886d authored by Macpaul Lin's avatar Macpaul Lin Committed by Wolfgang Denk
Browse files

nds32/ag101: cpu and init funcs of SoC ag101



SoC ag101 is the first chip using NDS32 N1213 cpu core.
Add header file of device offset support for SoC ag101.
Add main function of SoC ag101 based on NDS32 n1213 core.
Add lowlevel_init.S and other periphal related code.

This version of lowlevel_init.S also replace hardcode value
by MARCO defines from the GPL version andesboot for better
code quality.
Signed-off-by: default avatarMacpaul Lin <macpaul@andestech.com>
parent 37e5708a
#
# (C) Copyright 2009
# Marvell Semiconductor <www.marvell.com>
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
#
# Copyright (C) 2011 Andes Technology Corporation
# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
# MA 02110-1301 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
COBJS-y := cpu.o timer.o
ifndef CONFIG_SKIP_LOWLEVEL_INIT
SOBJS := lowlevel_init.o
endif
ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
SOBJS += watchdog.o
endif
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
/*
* Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
*
* Generate definitions needed by assembly language modules.
* This code generates raw asm output which is post-processed to extract
* and format the required data.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <common.h>
#include <linux/kbuild.h>
int main(void)
{
#ifdef CONFIG_FTSMC020
OFFSET(FTSMC020_BANK0_CR, ftsmc020, bank[0].cr);
OFFSET(FTSMC020_BANK0_TPR, ftsmc020, bank[0].tpr);
#endif
BLANK();
#ifdef CONFIG_FTAHBC020S
OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]);
OFFSET(FTAHBC020S_CR, ftahbc02s, cr);
#endif
BLANK();
#ifdef CONFIG_FTPMU010
OFFSET(FTPMU010_PDLLCR0, ftpmu010, PDLLCR0);
#endif
BLANK();
#ifdef CONFIG_FTSDMC021
OFFSET(FTSDMC021_TP1, ftsdmc021, tp1);
OFFSET(FTSDMC021_TP2, ftsdmc021, tp2);
OFFSET(FTSDMC021_CR1, ftsdmc021, cr1);
OFFSET(FTSDMC021_CR2, ftsdmc021, cr2);
OFFSET(FTSDMC021_BANK0_BSR, ftsdmc021, bank0_bsr);
OFFSET(FTSDMC021_BANK1_BSR, ftsdmc021, bank1_bsr);
OFFSET(FTSDMC021_BANK2_BSR, ftsdmc021, bank2_bsr);
OFFSET(FTSDMC021_BANK3_BSR, ftsdmc021, bank3_bsr);
#endif
return 0;
}
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* Copyright (C) 2011 Andes Technology Corporation
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* CPU specific code */
#include <common.h>
#include <command.h>
#include <watchdog.h>
#include <asm/cache.h>
#include <faraday/ftwdt010_wdt.h>
/*
* cleanup_before_linux() is called just before we call linux
* it prepares the processor for linux
*
* we disable interrupt and caches.
*/
int cleanup_before_linux(void)
{
#ifdef CONFIG_MMU
unsigned long i;
#endif
disable_interrupts();
#ifdef CONFIG_MMU
/* turn off I/D-cache */
icache_disable();
dcache_disable();
/* flush I/D-cache */
invalidate_icac();
invalidate_dcac();
#endif
return 0;
}
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
disable_interrupts();
/*
* reset to the base addr of andesboot.
* currently no ROM loader at addr 0.
* do not use reset_cpu(0);
*/
#ifdef CONFIG_FTWDT010_WATCHDOG
/*
* workaround: if we use CONFIG_HW_WATCHDOG with ftwdt010, will lead
* automatic hardware reset when booting Linux.
* Please do not use CONFIG_HW_WATCHDOG and WATCHDOG_RESET() here.
*/
ftwdt010_wdt_reset();
while (1)
;
#endif /* CONFIG_FTWDT010_WATCHDOG */
/*NOTREACHED*/
}
static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
{
if (cache == ICACHE)
return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
>> ICM_CFG_OFF_ISZ) - 1);
else
return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
>> DCM_CFG_OFF_DSZ) - 1);
}
void dcache_flush_range(unsigned long start, unsigned long end)
{
unsigned long line_size;
line_size = CACHE_LINE_SIZE(DCACHE);
while (end > start) {
__asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
start += line_size;
}
}
void icache_inval_range(unsigned long start, unsigned long end)
{
unsigned long line_size;
line_size = CACHE_LINE_SIZE(ICACHE);
while (end > start) {
__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
start += line_size;
}
}
void flush_cache(unsigned long addr, unsigned long size)
{
dcache_flush_range(addr , addr + size);
icache_inval_range(addr , addr + size);
}
void icache_enable(void)
{
__asm__ __volatile__ (
"mfsr $p0, $mr8\n\t"
"ori $p0, $p0, 0x01\n\t"
"mtsr $p0, $mr8\n\t"
"isb\n\t"
);
}
void icache_disable(void)
{
__asm__ __volatile__ (
"mfsr $p0, $mr8\n\t"
"li $p1, ~0x01\n\t"
"and $p0, $p0, $p1\n\t"
"mtsr $p0, $mr8\n\t"
"isb\n\t"
);
}
int icache_status(void)
{
int ret;
__asm__ __volatile__ (
"mfsr $p0, $mr8\n\t"
"andi %0, $p0, 0x01\n\t"
: "=r" (ret)
:
: "memory"
);
return ret;
}
void dcache_enable(void)
{
__asm__ __volatile__ (
"mfsr $p0, $mr8\n\t"
"ori $p0, $p0, 0x02\n\t"
"mtsr $p0, $mr8\n\t"
"isb\n\t"
);
}
void dcache_disable(void)
{
__asm__ __volatile__ (
"mfsr $p0, $mr8\n\t"
"li $p1, ~0x02\n\t"
"and $p0, $p0, $p1\n\t"
"mtsr $p0, $mr8\n\t"
"isb\n\t"
);
}
int dcache_status(void)
{
int ret;
__asm__ __volatile__ (
"mfsr $p0, $mr8\n\t"
"andi %0, $p0, 0x02\n\t"
: "=r" (ret)
:
: "memory"
);
return ret;
}
/*
* Copyright (C) 2011 Andes Technology Corporation
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
.text
#include <common.h>
#include <config.h>
#include <asm/macro.h>
#include <generated/asm-offsets.h>
/*
* parameters for the SDRAM controller
*/
#define SDMC_TP1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
#define SDMC_TP2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
#define SDMC_CR1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
#define SDMC_CR2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
#define SDMC_B0_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
#define SDMC_TP1_D CONFIG_SYS_FTSDMC021_TP1
#define SDMC_TP2_D CONFIG_SYS_FTSDMC021_TP2
#define SDMC_CR1_D CONFIG_SYS_FTSDMC021_CR1
#define SDMC_CR2_D CONFIG_SYS_FTSDMC021_CR2
#define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR
/*
* parameters for the static memory controller
*/
#define SMC_BANK0_CR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
#define SMC_BANK0_TPR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
#define SMC_BANK0_CR_D FTSMC020_BANK0_LOWLV_CONFIG
#define SMC_BANK0_TPR_D FTSMC020_BANK0_LOWLV_TIMING
/*
* parameters for the ahbc controller
*/
#define AHBC_CR_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
#define AHBC_BSR6_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
#define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
/*
* parameters for the pmu controoler
*/
#define PMU_PDLLCR0_A (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
/*
* numeric 7 segment display
*/
.macro led, num
write32 CONFIG_DEBUG_LED, \num
.endm
/*
* Waiting for SDRAM to set up
*/
.macro wait_sdram
li $r0, CONFIG_FTSDMC021_BASE
1:
lwi $r1, [$r0+FTSDMC021_CR2]
bnez $r1, 1b
.endm
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
.globl lowlevel_init
lowlevel_init:
move $r10, $lp
led 0x0
jal mem_init
led 0x10
jal remap
led 0x20
ret $r10
mem_init:
move $r11, $lp
/*
* mem_init:
* There are 2 bank connected to FTSMC020 on AG101
* BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
* we need to set onboard SDRAM before remap and relocation.
*/
led 0x01
write32 SMC_BANK0_CR_A, SMC_BANK0_CR_D ! 0x10000052
write32 SMC_BANK0_TPR_A, SMC_BANK0_TPR_D ! 0x00151151
/*
* config AHB Controller
*/
led 0x02
write32 AHBC_BSR6_A, AHBC_BSR6_D
/*
* config PMU controller
*/
/* ftpmu010_dlldis_disable, must do it in lowleve_init */
led 0x03
setbf32 PMU_PDLLCR0_A, FTPMU010_PDLLCR0_DLLDIS ! 0x00010000
/*
* config SDRAM controller
*/
led 0x04
write32 SDMC_TP1_A, SDMC_TP1_D ! 0x00011312
led 0x05
write32 SDMC_TP2_A, SDMC_TP2_D ! 0x00480180
led 0x06
write32 SDMC_CR1_A, SDMC_CR1_D ! 0x00002326
led 0x07
write32 SDMC_CR2_A, FTSDMC021_CR2_IPREC ! 0x00000010
wait_sdram
led 0x08
write32 SDMC_CR2_A, FTSDMC021_CR2_ISMR ! 0x00000004
wait_sdram
led 0x09
write32 SDMC_CR2_A, FTSDMC021_CR2_IREF ! 0x00000008
wait_sdram
led 0x0a
move $lp, $r11
ret
remap:
move $r11, $lp
#ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA - AG101 Only */
bal 2f
relo_base:
move $r0, $lp
#else
relo_base:
mfusr $r0, $pc
#endif /* __NDS32_N1213_43U1H__ */
/*
* Remapping
*/
led 0x1a
write32 SDMC_B0_BSR_A, SDMC_B0_BSR_D ! 0x00001100
/* clear empty BSR registers */
led 0x1b
li $r4, CONFIG_FTSDMC021_BASE
li $r5, 0x0
swi $r5, [$r4 + FTSDMC021_BANK1_BSR]
swi $r5, [$r4 + FTSDMC021_BANK2_BSR]
swi $r5, [$r4 + FTSDMC021_BANK3_BSR]
#ifdef CONFIG_MEM_REMAP
/*
* Copy ROM code to SDRAM base for memory remap layout.
* This is not the real relocation, the real relocation is the function
* relocate_code() is start.S which supports the systems is memory
* remapped or not.
*/
/*
* Doing memory remap is essential for preparing some non-OS or RTOS
* applications.
*
* This is also a must on ADP-AG101 board.
* The reason is because the ROM/FLASH circuit on PCB board.
* AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
* ROM/FLASH is used to boot.
*
* When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
* and the FLASH is connected to BANK1.
* When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
* and the FLASH is connected to BANK0.
* It will occur problem when doing flash probing if the flash is at
* BANK0 (0x00000000) while memory remapping was skipped.
*
* Other board like ADP-AG101P may not enable this since there is only
* a FLASH connected to bank0.
*/
led 0x11
li $r4, PHYS_SDRAM_0_AT_INIT /* 0x10000000 */
li $r5, 0x0
la $r1, relo_base /* get $pc or $lp */
sub $r2, $r0, $r1
sethi $r6, hi20(_end)
ori $r6, $r6, lo12(_end)
add $r6, $r6, $r2
1:
lwi.p $r7, [$r5], #4
swi.p $r7, [$r4], #4
blt $r5, $r6, 1b
/* set remap bit */
/*
* MEM remap bit is operational
* - use it to map writeable memory at 0x00000000, in place of flash
* - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
* - after remap: flash/rom 0x80000000, sdram: 0x00000000
*/
led 0x1c
setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP ! 0x1
#endif /* #ifdef CONFIG_MEM_REMAP */
move $lp, $r11
2:
ret
.globl show_led
show_led:
li $r8, (CONFIG_DEBUG_LED)
swi $r7, [$r8]
ret
#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
/*
* (C) Copyright 2009 Faraday Technology
* Po-Yu Chuang <ratbert@faraday-tech.com>
*
* Copyright (C) 2011 Andes Technology Corporation
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <common.h>
#include <asm/io.h>
#include <faraday/fttmr010.h>
static ulong timestamp;
static ulong lastdec;
int timer_init(void)
{
static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
unsigned int cr;
debug("%s()\n", __func__);
/* disable timers */
writel(0, &tmr->cr);
#ifdef CONFIG_FTTMR010_EXT_CLK
/* use 32768Hz oscillator for RTC, WDT, TIMER */
ftpmu010_32768osc_enable();
#endif
/* setup timer */
writel(TIMER_LOAD_VAL, &tmr->timer3_load);
writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
writel(0, &tmr->timer3_match1);
writel(0, &tmr->timer3_match2);
/* we don't want timer to issue interrupts */
writel(FTTMR010_TM3_MATCH1 |
FTTMR010_TM3_MATCH2 |
FTTMR010_TM3_OVERFLOW,
&tmr->interrupt_mask);
cr = readl(&tmr->cr);
#ifdef CONFIG_FTTMR010_EXT_CLK
cr |= FTTMR010_TM3_CLOCK; /* use external clock */
#endif
cr |= FTTMR010_TM3_ENABLE;
writel(cr, &tmr->cr);
/* init the timestamp and lastdec value */
reset_timer_masked();
return 0;
}
/*
* timer without interrupts