Commit 44d6cbb6 authored by Anton Staaf's avatar Anton Staaf Committed by Wolfgang Denk
Browse files

arm: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment


Signed-off-by: default avatarAnton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
parent f8df9d0d
......@@ -42,4 +42,15 @@ static inline void invalidate_l2_cache(void)
void l2_cache_enable(void);
void l2_cache_disable(void);
/*
* The current upper bound for ARM L1 data cache line sizes is 64 bytes. We
* use that value for aligning DMA buffers unless the board config has specified
* an alternate cache line size.
*/
#ifdef CONFIG_SYS_CACHELINE_SIZE
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
#else
#define ARCH_DMA_MINALIGN 64
#endif
#endif /* _ASM_CACHE_H */
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