Commit 472d5460 authored by York Sun's avatar York Sun Committed by Tom Rini
Browse files

Consolidate bool type



'bool' is defined in random places. This patch consolidates them into a
single header file include/linux/types.h, using stdbool.h introduced in C99.

All other #define, typedef and enum are removed. They are all consistent with
true = 1, false = 0.

Replace FALSE, False with false. Replace TRUE, True with true.
Skip *.py, *.php, lib/* files.
Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
parent 56443694
......@@ -1938,15 +1938,15 @@ CBFS (Coreboot Filesystem) support
I2C_READ
Code that returns TRUE if the I2C data line is high,
FALSE if it is low.
Code that returns true if the I2C data line is high,
false if it is low.
eg: #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
I2C_SDA(bit)
If <bit> is TRUE, sets the I2C data line high. If it
is FALSE, it clears it (low).
If <bit> is true, sets the I2C data line high. If it
is false, it clears it (low).
eg: #define I2C_SDA(bit) \
if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
......@@ -1954,8 +1954,8 @@ CBFS (Coreboot Filesystem) support
I2C_SCL(bit)
If <bit> is TRUE, sets the I2C clock line high. If it
is FALSE, it clears it (low).
If <bit> is true, sets the I2C clock line high. If it
is false, it clears it (low).
eg: #define I2C_SCL(bit) \
if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
......
......@@ -28,9 +28,6 @@
#include <asm/arch/spr_misc.h>
#include <asm/arch/spr_defs.h>
#define FALSE 0
#define TRUE (!FALSE)
static void sel_1v8(void)
{
struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
......@@ -133,8 +130,8 @@ void soc_init(void)
/*
* xxx_boot_selected:
*
* return TRUE if the particular booting option is selected
* return FALSE otherwise
* return true if the particular booting option is selected
* return false otherwise
*/
static u32 read_bootstrap(void)
{
......@@ -150,18 +147,18 @@ int snor_boot_selected(void)
/* Check whether SNOR boot is selected */
if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) ==
CONFIG_SPEAR_ONLYSNORBOOT)
return TRUE;
return true;
if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
CONFIG_SPEAR_NORNAND8BOOT)
return TRUE;
return true;
if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
CONFIG_SPEAR_NORNAND16BOOT)
return TRUE;
return true;
}
return FALSE;
return false;
}
int nand_boot_selected(void)
......@@ -172,20 +169,20 @@ int nand_boot_selected(void)
/* Check whether NAND boot is selected */
if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
CONFIG_SPEAR_NORNAND8BOOT)
return TRUE;
return true;
if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
CONFIG_SPEAR_NORNAND16BOOT)
return TRUE;
return true;
}
return FALSE;
return false;
}
int pnor_boot_selected(void)
{
/* Parallel NOR boot is not selected in any SPEAr600 revision */
return FALSE;
return false;
}
int usb_boot_selected(void)
......@@ -195,39 +192,39 @@ int usb_boot_selected(void)
if (USB_BOOT_SUPPORTED) {
/* Check whether USB boot is selected */
if (!(bootstrap & CONFIG_SPEAR_USBBOOT))
return TRUE;
return true;
}
return FALSE;
return false;
}
int tftp_boot_selected(void)
{
/* TFTP boot is not selected in any SPEAr600 revision */
return FALSE;
return false;
}
int uart_boot_selected(void)
{
/* UART boot is not selected in any SPEAr600 revision */
return FALSE;
return false;
}
int spi_boot_selected(void)
{
/* SPI boot is not selected in any SPEAr600 revision */
return FALSE;
return false;
}
int i2c_boot_selected(void)
{
/* I2C boot is not selected in any SPEAr600 revision */
return FALSE;
return false;
}
int mmc_boot_selected(void)
{
return FALSE;
return false;
}
void plat_late_init(void)
......
......@@ -120,7 +120,7 @@ u32 spl_boot(void)
/*
* All the supported booting devices are listed here. Each of
* the booting type supported by the platform would define the
* macro xxx_BOOT_SUPPORTED to TRUE.
* macro xxx_BOOT_SUPPORTED to true.
*/
if (SNOR_BOOT_SUPPORTED && snor_boot_selected()) {
......
......@@ -61,9 +61,6 @@ typedef unsigned int __kernel_gid32_t;
typedef unsigned short __kernel_old_uid_t;
typedef unsigned short __kernel_old_gid_t;
#define BOOL_WAS_DEFINED
typedef enum { false = 0, true = 1 } bool;
#ifdef __GNUC__
typedef long long __kernel_loff_t;
#endif
......
......@@ -96,7 +96,7 @@ int disable_interrupts (void)
sr = get_sr ();
set_sr (sr | 0x0700);
return ((sr & 0x0700) == 0); /* return TRUE, if interrupts were enabled before */
return ((sr & 0x0700) == 0); /* return true, if interrupts were enabled before */
}
void int_handler (struct pt_regs *fp)
......
......@@ -59,7 +59,7 @@ void enable_interrupts(void)
/*
* disable interrupts
* Return TRUE if GIE is enabled before we disable it.
* Return true if GIE is enabled before we disable it.
*/
int disable_interrupts(void)
{
......
......@@ -513,7 +513,7 @@ void fsl_serdes_init(void)
size_t arglen;
#endif
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001
int need_serdes_a001; /* TRUE == need work-around for SERDES A001 */
int need_serdes_a001; /* true == need work-around for SERDES A001 */
#endif
#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
char buffer[HWCONFIG_BUFFER_SIZE];
......
......@@ -88,8 +88,6 @@ void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang"))
#define NUMMEMTESTS 8
#define NUMMEMWORDS 8
#define MAXBXCR 4
#define TRUE 1
#define FALSE 0
/*
* This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
......@@ -298,7 +296,7 @@ static void get_spd_info(unsigned long *dimm_populated,
unsigned char num_of_bytes;
unsigned char total_size;
dimm_found = FALSE;
dimm_found = false;
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
num_of_bytes = 0;
total_size = 0;
......@@ -307,16 +305,16 @@ static void get_spd_info(unsigned long *dimm_populated,
total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
if ((num_of_bytes != 0) && (total_size != 0)) {
dimm_populated[dimm_num] = TRUE;
dimm_found = TRUE;
dimm_populated[dimm_num] = true;
dimm_found = true;
debug("DIMM slot %lu: populated\n", dimm_num);
} else {
dimm_populated[dimm_num] = FALSE;
dimm_populated[dimm_num] = false;
debug("DIMM slot %lu: Not populated\n", dimm_num);
}
}
if (dimm_found == FALSE) {
if (dimm_found == false) {
printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
spd_ddr_init_hang ();
}
......@@ -330,7 +328,7 @@ static void check_mem_type(unsigned long *dimm_populated,
unsigned char dimm_type;
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
if (dimm_populated[dimm_num] == TRUE) {
if (dimm_populated[dimm_num] == true) {
dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
switch (dimm_type) {
case 7:
......@@ -356,7 +354,7 @@ static void check_volt_type(unsigned long *dimm_populated,
unsigned long voltage_type;
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
if (dimm_populated[dimm_num] == TRUE) {
if (dimm_populated[dimm_num] == true) {
voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
if (voltage_type != 0x04) {
printf("ERROR: DIMM %lu with unsupported voltage level.\n",
......@@ -398,12 +396,12 @@ static void program_cfg0(unsigned long *dimm_populated,
/*
* FIXME: assume the DDR SDRAMs in both banks are the same
*/
ecc_enabled = TRUE;
ecc_enabled = true;
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
if (dimm_populated[dimm_num] == TRUE) {
if (dimm_populated[dimm_num] == true) {
ecc = spd_read(iic0_dimm_addr[dimm_num], 11);
if (ecc != 0x02) {
ecc_enabled = FALSE;
ecc_enabled = false;
}
/*
......@@ -437,7 +435,7 @@ static void program_cfg0(unsigned long *dimm_populated,
/*
* program Memory Data Error Checking
*/
if (ecc_enabled == TRUE) {
if (ecc_enabled == true) {
cfg0 |= SDRAM_CFG0_MCHK_GEN;
} else {
cfg0 |= SDRAM_CFG0_MCHK_NON;
......@@ -493,7 +491,7 @@ static void program_rtr(unsigned long *dimm_populated,
bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
if (dimm_populated[dimm_num] == TRUE) {
if (dimm_populated[dimm_num] == true) {
refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
switch (refresh_rate_type) {
case 0x00:
......@@ -585,15 +583,15 @@ static void program_tr0(unsigned long *dimm_populated,
t_rp_ns = 0;
t_rcd_ns = 0;
t_ras_ns = 0;
cas_2_0_available = TRUE;
cas_2_5_available = TRUE;
cas_3_0_available = TRUE;
cas_2_0_available = true;
cas_2_5_available = true;
cas_3_0_available = true;
tcyc_2_0_ns_x_10 = 0;
tcyc_2_5_ns_x_10 = 0;
tcyc_3_0_ns_x_10 = 0;
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
if (dimm_populated[dimm_num] == TRUE) {
if (dimm_populated[dimm_num] == true) {
wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
......@@ -640,7 +638,7 @@ static void program_tr0(unsigned long *dimm_populated,
if (cas_index != 0) {
cas_index++;
}
cas_3_0_available = FALSE;
cas_3_0_available = false;
}
if (((cas_bit & 0x08) != 0) || (cas_index < 3)) {
......@@ -650,7 +648,7 @@ static void program_tr0(unsigned long *dimm_populated,
if (cas_index != 0) {
cas_index++;
}
cas_2_5_available = FALSE;
cas_2_5_available = false;
}
if (((cas_bit & 0x04) != 0) || (cas_index < 3)) {
......@@ -660,7 +658,7 @@ static void program_tr0(unsigned long *dimm_populated,
if (cas_index != 0) {
cas_index++;
}
cas_2_0_available = FALSE;
cas_2_0_available = false;
}
break;
......@@ -683,13 +681,13 @@ static void program_tr0(unsigned long *dimm_populated,
/*
* Program SD_CASL field
*/
if ((cas_2_0_available == TRUE) &&
if ((cas_2_0_available == true) &&
(bus_period_x_10 >= tcyc_2_0_ns_x_10)) {
tr0 |= SDRAM_TR0_SDCL_2_0_CLK;
} else if ((cas_2_5_available == TRUE) &&
} else if ((cas_2_5_available == true) &&
(bus_period_x_10 >= tcyc_2_5_ns_x_10)) {
tr0 |= SDRAM_TR0_SDCL_2_5_CLK;
} else if ((cas_3_0_available == TRUE) &&
} else if ((cas_3_0_available == true) &&
(bus_period_x_10 >= tcyc_3_0_ns_x_10)) {
tr0 |= SDRAM_TR0_SDCL_3_0_CLK;
} else {
......@@ -950,9 +948,9 @@ static void program_tr1(void)
current_fail_length = 0;
current_start = 0;
rdclt_offset = 0;
window_found = FALSE;
fail_found = FALSE;
pass_found = FALSE;
window_found = false;
fail_found = false;
pass_found = false;
debug("Starting memory test ");
for (k = 0; k < NUMHALFCYCLES; k++) {
......@@ -963,8 +961,8 @@ static void program_tr1(void)
mtsdram(SDRAM0_TR1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
if (short_mem_test()) {
if (fail_found == TRUE) {
pass_found = TRUE;
if (fail_found == true) {
pass_found = true;
if (current_pass_length == 0) {
current_start = rdclt_offset + rdclt;
}
......@@ -983,10 +981,10 @@ static void program_tr1(void)
current_fail_length++;
if (current_fail_length >= (dly_val>>2)) {
if (fail_found == FALSE) {
fail_found = TRUE;
} else if (pass_found == TRUE) {
window_found = TRUE;
if (fail_found == false) {
fail_found = true;
} else if (pass_found == true) {
window_found = true;
break;
}
}
......@@ -994,9 +992,8 @@ static void program_tr1(void)
}
debug(".");
if (window_found == TRUE) {
if (window_found == true)
break;
}
tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
rdclt_offset += dly_val;
......@@ -1006,7 +1003,7 @@ static void program_tr1(void)
/*
* make sure we find the window
*/
if (window_found == FALSE) {
if (window_found == false) {
printf("ERROR: Cannot determine a common read delay.\n");
spd_ddr_init_hang ();
}
......@@ -1115,7 +1112,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
bank_base_addr = CONFIG_SYS_SDRAM_BASE;
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
if (dimm_populated[dimm_num] == TRUE) {
if (dimm_populated[dimm_num] == true) {
num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3);
num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
num_banks = spd_read(iic0_dimm_addr[dimm_num], 5);
......
......@@ -241,13 +241,6 @@ void board_add_ram_info(int use_default)
/*-----------------------------------------------------------------------------+
* Defines
*-----------------------------------------------------------------------------*/
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
#define SDRAM_DDR1 1
#define SDRAM_DDR2 2
#define SDRAM_NONE 0
......@@ -683,7 +676,7 @@ static void get_spd_info(unsigned long *dimm_populated,
unsigned char num_of_bytes;
unsigned char total_size;
dimm_found = FALSE;
dimm_found = false;
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
num_of_bytes = 0;
total_size = 0;
......@@ -696,16 +689,16 @@ static void get_spd_info(unsigned long *dimm_populated,
iic0_dimm_addr[dimm_num], total_size);
if ((num_of_bytes != 0) && (total_size != 0)) {
dimm_populated[dimm_num] = TRUE;
dimm_found = TRUE;
dimm_populated[dimm_num] = true;
dimm_found = true;
debug("DIMM slot %lu: populated\n", dimm_num);
} else {
dimm_populated[dimm_num] = FALSE;
dimm_populated[dimm_num] = false;
debug("DIMM slot %lu: Not populated\n", dimm_num);
}
}
if (dimm_found == FALSE) {
if (dimm_found == false) {
printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
spd_ddr_init_hang ();
}
......@@ -724,7 +717,7 @@ static void check_mem_type(unsigned long *dimm_populated,
unsigned long dimm_type;
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
if (dimm_populated[dimm_num] == TRUE) {
if (dimm_populated[dimm_num] == true) {
dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
switch (dimm_type) {
case 1:
......@@ -994,14 +987,14 @@ static void program_copt1(unsigned long *dimm_populated,
unsigned long val;
#ifdef CONFIG_DDR_ECC
ecc_enabled = TRUE;
ecc_enabled = true;
#else
ecc_enabled = FALSE;
ecc_enabled = false;
#endif
dimm_32bit = FALSE;
dimm_64bit = FALSE;
buf0 = FALSE;
buf1 = FALSE;
dimm_32bit = false;
dimm_64bit = false;
buf0 = false;
buf1 = false;
/*------------------------------------------------------------------
* Set memory controller options reg 1, SDRAM_MCOPT1.
......@@ -1026,7 +1019,7 @@ static void program_copt1(unsigned long *dimm_populated,
/* test ecc support */
ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
if (ecc != 0x02) /* ecc not supported */
ecc_enabled = FALSE;
ecc_enabled = false;
/* test bank count */
bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
......@@ -1048,15 +1041,15 @@ static void program_copt1(unsigned long *dimm_populated,
if (registered == 1) { /* DDR2 always buffered */
/* TODO: what about above comments ? */
mcopt1 |= SDRAM_MCOPT1_RDEN;
buf0 = TRUE;
buf0 = true;
} else {
/* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
if ((attribute & 0x02) == 0x00) {
/* buffered not supported */
buf0 = FALSE;
buf0 = false;
} else {
mcopt1 |= SDRAM_MCOPT1_RDEN;
buf0 = TRUE;
buf0 = true;
}
}
}
......@@ -1068,14 +1061,14 @@ static void program_copt1(unsigned long *dimm_populated,
if (registered == 1) {
/* DDR2 always buffered */
mcopt1 |= SDRAM_MCOPT1_RDEN;
buf1 = TRUE;
buf1 = true;
} else {
if ((attribute & 0x02) == 0x00) {
/* buffered not supported */
buf1 = FALSE;
buf1 = false;
} else {
mcopt1 |= SDRAM_MCOPT1_RDEN;
buf1 = TRUE;
buf1 = true;
}
}
}
......@@ -1087,11 +1080,11 @@ static void program_copt1(unsigned long *dimm_populated,
switch (data_width) {
case 72:
case 64:
dimm_64bit = TRUE;
dimm_64bit = true;
break;
case 40:
case 32:
dimm_32bit = TRUE;
dimm_32bit = true;
break;
default:
printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
......@@ -1110,20 +1103,19 @@ static void program_copt1(unsigned long *dimm_populated,
}
}
if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
if ((dimm_64bit == true) && (dimm_32bit == true)) {
printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
spd_ddr_init_hang ();
}
else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
} else if ((dimm_64bit == true) && (dimm_32bit == false)) {
mcopt1 |= SDRAM_MCOPT1_DMWD_64;
} else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
} else if ((dimm_64bit == false) && (dimm_32bit == true)) {
mcopt1 |= SDRAM_MCOPT1_DMWD_32;
} else {
printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
spd_ddr_init_hang ();
}
if (ecc_enabled == TRUE)
if (ecc_enabled == true)
mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
else
mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
......@@ -1171,14 +1163,14 @@ static void program_codt(unsigned long *dimm_populated,
total_rank += dimm_rank;
total_dimm++;
if ((dimm_num == 0) && (total_dimm == 1))
firstSlot = TRUE;
firstSlot = true;
else
firstSlot = FALSE;
firstSlot = false;
}
}
if (dimm_type == SDRAM_DDR2) {
codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
if ((total_dimm == 1) && (firstSlot == TRUE)) {
if ((total_dimm == 1) && (firstSlot == true)) {
if (total_rank == 1) { /* PUUU */
codt |= CALC_ODT_R(0);
modt0 = CALC_ODT_W(0);
......@@ -1193,7 +1185,7 @@ static void program_codt(unsigned long *dimm_populated,
modt2 = 0x00000000;
modt3 = 0x00000000;
}
} else if ((total_dimm == 1) && (firstSlot != TRUE)) {
} else if ((total_dimm == 1) && (firstSlot != true)) {
if (total_rank == 1) { /* UUPU */
codt |= CALC_ODT_R(2);
modt0 = 0x00000000;
......@@ -1467,26 +1459,26 @@ static void program_mode(unsigned long *dimm_populated,
* the dimm modules installed.
*-----------------------------------------------------------------*/