Commit 488f5d87 authored by Ladislav Michl's avatar Ladislav Michl Committed by Jean-Christophe PLAGNIOL-VILLARD
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Remove nowhere used symbol CONFIG_SYS_CLKS_IN_HZ


Signed-off-by: default avatarLadislav Michl <ladis@linux-mips.org>
parent 88685b5f
......@@ -44,7 +44,6 @@
#define CONFIG_ADNPESC1 1 /* SSV ADNP/ESC1 board */
#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_NIOS_CPU_CLK/* 50 MHz core clock */
#define CONFIG_SYS_HZ 1000 /* 1 msec time tick */
#undef CONFIG_SYS_CLKS_IN_HZ
#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/
/*------------------------------------------------------------------------
......
......@@ -116,8 +116,6 @@
#define CONFIG_SYS_MEMTEST_START 0x0C400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C800000 /* 4 ... 8 MB in DRAM */
#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CONFIG_SYS_LOAD_ADDR 0x0c700000 /* default load address */
#define CONFIG_SYS_HZ 1000 /* 1 kHz */
......
......@@ -50,7 +50,6 @@
#define CONFIG_DK1C20 1 /* Cyclone DK-1C20 board*/
#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_NIOS_CPU_CLK/* 50 MHz core clock */
#define CONFIG_SYS_HZ 1000 /* 1 msec time tick */
#undef CONFIG_SYS_CLKS_IN_HZ
#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/
/*------------------------------------------------------------------------
......
......@@ -48,7 +48,6 @@
#define CONFIG_DK1S10 1 /* Stratix DK-1S10 board*/
#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_NIOS_CPU_CLK/* 50 MHz core clock */
#define CONFIG_SYS_HZ 1000 /* 1 msec time tick */
#undef CONFIG_SYS_CLKS_IN_HZ
#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/
/*------------------------------------------------------------------------
......
......@@ -129,8 +129,6 @@
{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
57600, 115200, 230400, 460800, 921600 }
#define CONFIG_SYS_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
......
......@@ -139,8 +139,6 @@
#define CONFIG_SYS_MEMTEST_START 0x81800000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x83000000 /* 24 MB in SRAM */
#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
/* for uClinux img is here*/
......
......@@ -133,8 +133,6 @@
#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */
/* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
......
......@@ -172,9 +172,6 @@
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_LOAD_ADDR 0x30800000 /* default load address */
#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
/* we configure PWM Timer 4 to 1us ~ 1MHz */
/*#define CONFIG_SYS_HZ 1000000 */
#define CONFIG_SYS_HZ 1562500
......
......@@ -131,8 +131,6 @@
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE {9600}
#define CONFIG_SYS_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info (bd_t) */
......
......@@ -139,8 +139,6 @@
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE {9600}
#define CONFIG_SYS_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info (bd_t) */
......
......@@ -95,8 +95,6 @@
#define CONFIG_SYS_MEMTEST_START 0x00400000
#define CONFIG_SYS_MEMTEST_END 0x00800000
/* everything, incl board info, in Hz */
#undef CONFIG_SYS_CLKS_IN_HZ
/* spec says 66.666 MHz, but it appears to be 33 */
#define CONFIG_SYS_HZ 3333333
......
......@@ -86,8 +86,6 @@
#define CONFIG_SYS_MEMTEST_START 0x00400000
#define CONFIG_SYS_MEMTEST_END 0x00800000
/* everything, incl board info, in Hz */
#undef CONFIG_SYS_CLKS_IN_HZ
/* spec says 66.666 MHz, but it appears to be 33 */
#define CONFIG_SYS_HZ 3333333
......
......@@ -84,8 +84,6 @@
#define CONFIG_SYS_MEMTEST_START 0x00400000
#define CONFIG_SYS_MEMTEST_END 0x00800000
/* everything, incl board info, in Hz */
#undef CONFIG_SYS_CLKS_IN_HZ
/* spec says 66.666 MHz, but it appears to be 33 */
#define CONFIG_SYS_HZ 3333333
......
......@@ -83,8 +83,6 @@
#define CONFIG_SYS_MEMTEST_START 0x00400000
#define CONFIG_SYS_MEMTEST_END 0x00800000
/* everything, incl board info, in Hz */
#undef CONFIG_SYS_CLKS_IN_HZ
/* spec says 66.666 MHz, but it appears to be 33 */
#define CONFIG_SYS_HZ 3333333
......
......@@ -196,7 +196,6 @@
#define CONFIG_SYS_MEMTEST_START (OMAP2420_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M)
#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
/* default load address */
#define CONFIG_SYS_LOAD_ADDR (OMAP2420_SDRC_CS0)
......
......@@ -105,8 +105,6 @@
#define CONFIG_SYS_MEMTEST_START 0xc0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */
#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CONFIG_SYS_LOAD_ADDR 0x00040000 /* default load address for armadillo: kernel img is here*/
#define CONFIG_SYS_HZ 2000 /* decrementer freq: 2 kHz */
......
......@@ -105,8 +105,6 @@
#define CONFIG_SYS_MEMTEST_START 0xc0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */
#undef CONFIG_SYS_CLKS_IN_HZ
#define CONFIG_SYS_LOAD_ADDR 0xc0000000 /* default load address */
#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
......
......@@ -113,8 +113,6 @@
#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
#undef CONFIG_SYS_CLKS_IN_HZ
#define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */
#define CONFIG_SYS_HZ 1000
......
......@@ -93,8 +93,6 @@
#define CONFIG_SYS_MEMTEST_START 0x00800000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 16 MB in DRAM */
#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CONFIG_SYS_LOAD_ADDR 0x00008000 /* default load address */
#define CONFIG_SYS_HZ (1000) /* 1ms resolution ticks */
......
......@@ -93,8 +93,6 @@
#define CONFIG_SYS_MEMTEST_START 0x00800000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 16 MB in DRAM */
#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CONFIG_SYS_LOAD_ADDR 0x00008000 /* default load address */
#define CONFIG_SYS_HZ (1000) /* 1ms resolution ticks */
......
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