Commit 48b42616 authored by wdenk's avatar wdenk
Browse files

* Patches by David Mller, 12 Jun 2003:

  - rewrite of the S3C24X0 register definitions stuff
  - "driver" for the built-in S3C24X0 RTC

* Patches by Yuli Barcohen, 12 Jun 2003:
  - Add MII support and Ethernet PHY initialization for MPC8260ADS board
  - Fix incorrect SIUMCR initialisation caused by wrong Hard Reset
    configuration word supplied by FPGA on some MPC8260ADS boards

* Patch by Pantelis Antoniou, 10 Jun 2003:
  Unify status LED interface
parent 15ef8a5d
...@@ -2,6 +2,18 @@ ...@@ -2,6 +2,18 @@
Changes since U-Boot 0.3.1: Changes since U-Boot 0.3.1:
====================================================================== ======================================================================
* Patches by David Mller, 12 Jun 2003:
- rewrite of the S3C24X0 register definitions stuff
- "driver" for the built-in S3C24X0 RTC
* Patches by Yuli Barcohen, 12 Jun 2003:
- Add MII support and Ethernet PHY initialization for MPC8260ADS board
- Fix incorrect SIUMCR initialisation caused by wrong Hard Reset
configuration word supplied by FPGA on some MPC8260ADS boards
* Patch by Pantelis Antoniou, 10 Jun 2003:
Unify status LED interface
* Add support for DS12887 RTC; add RTC support for ATC board * Add support for DS12887 RTC; add RTC support for ATC board
* Patch by Nicolas Lacressonniere, 11 Jun 2003: * Patch by Nicolas Lacressonniere, 11 Jun 2003:
......
...@@ -9,6 +9,10 @@ ...@@ -9,6 +9,10 @@
* (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
* Added support for the 16M dram simm on the 8260ads boards * Added support for the 16M dram simm on the 8260ads boards
* *
* (C) Copyright 2003 Arabella Software Ltd.
* Yuli Barcohen <yuli@arabellasw.com>
* Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
*
* See file CREDITS for list of people who contributed to this * See file CREDITS for list of people who contributed to this
* project. * project.
* *
......
...@@ -45,7 +45,11 @@ extern int gunzip (void *, int, unsigned char *, int *); ...@@ -45,7 +45,11 @@ extern int gunzip (void *, int, unsigned char *, int *);
extern int mem_test(unsigned long start, unsigned long ramsize, int quiet); extern int mem_test(unsigned long start, unsigned long ramsize, int quiet);
#define I2C_BACKUP_ADDR 0x7C00 /* 0x200 bytes for backup */ #define I2C_BACKUP_ADDR 0x7C00 /* 0x200 bytes for backup */
#if defined(CONFIG_PIP405) || defined(CONFIG_MIP405)
#define IMAGE_SIZE 0x80000 #define IMAGE_SIZE 0x80000
#elif defined(CONFIG_VCMA9)
#define IMAGE_SIZE 0x40000 /* ugly, but it works for now */
#endif
extern flash_info_t flash_info[]; /* info for FLASH chips */ extern flash_info_t flash_info[]; /* info for FLASH chips */
......
...@@ -15,10 +15,10 @@ ...@@ -15,10 +15,10 @@
# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 # Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
# optionally with a ramdisk at 3080'0000 # optionally with a ramdisk at 3080'0000
# #
# we load ourself to 33F0'0000 # we load ourself to 33F8'0000
# #
# download area is 3300'0000 # download area is 3300'0000
# #
TEXT_BASE = 0x33F00000 TEXT_BASE = 0x33F80000
...@@ -54,8 +54,10 @@ ...@@ -54,8 +54,10 @@
/* BANK0CON */ /* BANK0CON */
#define B0_Tacs 0x0 /* 0clk */ #define B0_Tacs 0x0 /* 0clk */
#define B0_Tcos 0x0 /* 0clk */ #define B0_Tcos 0x1 /* 1clk */
#define B0_Tacc 0x5 /* 8clk */ /*#define B0_Tcos 0x0 0clk */
#define B0_Tacc 0x7 /* 14clk */
/*#define B0_Tacc 0x5 8clk */
#define B0_Tcoh 0x0 /* 0clk */ #define B0_Tcoh 0x0 /* 0clk */
#define B0_Tah 0x0 /* 0clk */ #define B0_Tah 0x0 /* 0clk */
#define B0_Tacp 0x0 /* page mode is not used */ #define B0_Tacp 0x0 /* page mode is not used */
...@@ -63,8 +65,10 @@ ...@@ -63,8 +65,10 @@
/* BANK1CON */ /* BANK1CON */
#define B1_Tacs 0x0 /* 0clk */ #define B1_Tacs 0x0 /* 0clk */
#define B1_Tcos 0x0 /* 0clk */ #define B1_Tcos 0x1 /* 1clk */
#define B1_Tacc 0x5 /* 8clk */ /*#define B1_Tcos 0x0 0clk */
#define B1_Tacc 0x7 /* 14clk */
/*#define B1_Tacc 0x5 8clk */
#define B1_Tcoh 0x0 /* 0clk */ #define B1_Tcoh 0x0 /* 0clk */
#define B1_Tah 0x0 /* 0clk */ #define B1_Tah 0x0 /* 0clk */
#define B1_Tacp 0x0 /* page mode is not used */ #define B1_Tacp 0x0 /* page mode is not used */
......
...@@ -72,41 +72,46 @@ static inline void delay(unsigned long loops) ...@@ -72,41 +72,46 @@ static inline void delay(unsigned long loops)
int board_init(void) int board_init(void)
{ {
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
/* to reduce PLL lock time, adjust the LOCKTIME register */ /* to reduce PLL lock time, adjust the LOCKTIME register */
rLOCKTIME = 0xFFFFFF; clk_power->LOCKTIME = 0xFFFFFF;
/* configure MPLL */ /* configure MPLL */
rMPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
/* some delay between MPLL and UPLL */ /* some delay between MPLL and UPLL */
delay (4000); delay (4000);
/* configure UPLL */ /* configure UPLL */
rUPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
/* some delay between MPLL and UPLL */ /* some delay between MPLL and UPLL */
delay (8000); delay (8000);
/* set up the I/O ports */ /* set up the I/O ports */
rGPACON = 0x007FFFFF; gpio->GPACON = 0x007FFFFF;
rGPBCON = 0x002AAAAA; gpio->GPBCON = 0x002AAAAA;
rGPBUP = 0x000002BF; gpio->GPBUP = 0x000002BF;
rGPCCON = 0xAAAAAAAA; gpio->GPCCON = 0xAAAAAAAA;
rGPCUP = 0x0000FFFF; gpio->GPCUP = 0x0000FFFF;
rGPDCON = 0xAAAAAAAA; gpio->GPDCON = 0xAAAAAAAA;
rGPDUP = 0x0000FFFF; gpio->GPDUP = 0x0000FFFF;
rGPECON = 0xAAAAAAAA; gpio->GPECON = 0xAAAAAAAA;
rGPEUP = 0x000037F7; gpio->GPEUP = 0x000037F7;
rGPFCON = 0x00000000; gpio->GPFCON = 0x00000000;
rGPFUP = 0x00000000; gpio->GPFUP = 0x00000000;
rGPGCON = 0xFFEAFF5A; gpio->GPGCON = 0xFFEAFF5A;
rGPGUP = 0x0000F0DC; gpio->GPGUP = 0x0000F0DC;
rGPHCON = 0x0028AAAA; gpio->GPHCON = 0x0028AAAA;
rGPHUP = 0x00000656; gpio->GPHUP = 0x00000656;
/* setup correct IRQ modes for NIC */ /* setup correct IRQ modes for NIC */
rEXTINT2 = (rEXTINT2 & ~(7<<8)) | (4<<8); /* rising edge mode */ gpio->EXTINT2 = (gpio->EXTINT2 & ~(7<<8)) | (4<<8); /* rising edge mode */
/* select USB port 2 to be host or device (fix to host for now) */
gpio->MISCCR |= 0x08;
/* init serial */ /* init serial */
gd->baudrate = CONFIG_BAUDRATE; gd->baudrate = CONFIG_BAUDRATE;
...@@ -135,6 +140,50 @@ int dram_init(void) ...@@ -135,6 +140,50 @@ int dram_init(void)
return 0; return 0;
} }
/*
* NAND flash initialization.
*/
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
extern void
nand_probe(ulong physadr);
static inline void NF_Reset(void)
{
int i;
NF_SetCE(NFCE_LOW);
NF_Cmd(0xFF); /* reset command */
for(i = 0; i < 10; i++); /* tWB = 100ns. */
NF_WaitRB(); /* wait 200~500us; */
NF_SetCE(NFCE_HIGH);
}
static inline void NF_Init(void)
{
#define TACLS 0
#define TWRPH0 3
#define TWRPH1 0
NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0));
//nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0);
// 1 1 1 1, 1 xxx, r xxx, r xxx
// En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1
NF_Reset();
}
void
nand_init(void)
{
S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
NF_Init();
printf("NAND flash probing at 0x%.8lX\n", (ulong)nand);
nand_probe((ulong)nand);
}
#endif
/* /*
* Get some Board/PLD Info * Get some Board/PLD Info
*/ */
...@@ -195,12 +244,12 @@ int checkboard(void) ...@@ -195,12 +244,12 @@ int checkboard(void)
puts ("### No HW ID - assuming VCMA9"); puts ("### No HW ID - assuming VCMA9");
} else { } else {
b->serial_name[5] = 0; b->serial_name[5] = 0;
printf ("%s-%d Rev %c SN: %s", b->serial_name, Get_Board_Config(), printf ("%s-%d PCB Rev %c SN: %s", b->serial_name, Get_Board_Config(),
Get_Board_PCB(), &b->serial_name[6]); Get_Board_PCB(), &b->serial_name[6]);
} }
} else { } else {
s[5] = 0; s[5] = 0;
printf ("%s-%d Rev %c SN: %s", s, Get_Board_Config(), Get_Board_PCB(), printf ("%s-%d PCB Rev %c SN: %s", s, Get_Board_Config(), Get_Board_PCB(),
&s[6]); &s[6]);
} }
printf("\n"); printf("\n");
...@@ -211,7 +260,7 @@ int checkboard(void) ...@@ -211,7 +260,7 @@ int checkboard(void)
void print_vcma9_rev(void) void print_vcma9_rev(void)
{ {
printf("Board: VCMA9-%d Rev: %c (PLD Ver: %d, Rev: %d)\n", printf("Board: VCMA9-%d PCB Rev: %c (PLD Ver: %d, Rev: %d)\n",
Get_Board_Config(), Get_Board_PCB(), Get_Board_Config(), Get_Board_PCB(),
Get_PLD_Version(), Get_PLD_Revision()); Get_PLD_Version(), Get_PLD_Revision());
} }
...@@ -245,5 +294,3 @@ void print_vcma9_info(void) ...@@ -245,5 +294,3 @@ void print_vcma9_info(void)
{ {
print_vcma9_rev(); print_vcma9_rev();
} }
...@@ -25,11 +25,97 @@ ...@@ -25,11 +25,97 @@
* Global routines used for VCMA9 * Global routines used for VCMA9
*****************************************************************************/ *****************************************************************************/
#include <s3c2410.h>
extern int mem_test(unsigned long start, unsigned long ramsize,int mode); extern int mem_test(unsigned long start, unsigned long ramsize,int mode);
void print_vcma9_info(void); void print_vcma9_info(void);
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
typedef enum {
NFCE_LOW,
NFCE_HIGH
} NFCE_STATE;
static inline void NF_Conf(u16 conf)
{
S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
nand->NFCONF = conf;
}
static inline void NF_Cmd(u8 cmd)
{
S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
nand->NFCMD = cmd;
}
static inline void NF_CmdW(u8 cmd)
{
NF_Cmd(cmd);
udelay(1);
}
static inline void NF_Addr(u8 addr)
{
S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
nand->NFADDR = addr;
}
static inline void NF_SetCE(NFCE_STATE s)
{
S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
switch (s) {
case NFCE_LOW:
nand->NFCONF &= ~(1<<11);
break;
case NFCE_HIGH:
nand->NFCONF |= (1<<11);
break;
}
}
static inline void NF_WaitRB(void)
{
S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
while (!(nand->NFSTAT & (1<<0)));
}
static inline void NF_Write(u8 data)
{
S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
nand->NFDATA = data;
}
static inline u8 NF_Read(void)
{
S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
return(nand->NFDATA);
}
static inline void NF_Init_ECC(void)
{
S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
nand->NFCONF |= (1<<12);
}
static inline u32 NF_Read_ECC(void)
{
S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
return(nand->NFECC);
}
#endif
#define PLD_BASE_ADDRESS 0x2C000100 #define PLD_BASE_ADDRESS 0x2C000100
#define PLD_ID_REG (PLD_BASE_ADDRESS + 0) #define PLD_ID_REG (PLD_BASE_ADDRESS + 0)
...@@ -39,5 +125,3 @@ void print_vcma9_info(void); ...@@ -39,5 +125,3 @@ void print_vcma9_info(void);
#define PLD_GPCD_REG (PLD_BASE_ADDRESS + 4) #define PLD_GPCD_REG (PLD_BASE_ADDRESS + 4)
#define PLD_BOARD_REG (PLD_BASE_ADDRESS + 5) #define PLD_BOARD_REG (PLD_BASE_ADDRESS + 5)
...@@ -46,33 +46,35 @@ extern int do_mdm_init; /* defined in common/main.c */ ...@@ -46,33 +46,35 @@ extern int do_mdm_init; /* defined in common/main.c */
int board_init (void) int board_init (void)
{ {
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
/* memory and cpu-speed are setup before relocation */ /* memory and cpu-speed are setup before relocation */
/* change the clock to be 50 MHz 1:1:1 */ /* change the clock to be 50 MHz 1:1:1 */
rMPLLCON = 0x5c042; clk_power->MPLLCON = 0x5c042;
rCLKDIVN = 0; clk_power->CLKDIVN = 0;
/* set up the I/O ports */ /* set up the I/O ports */
rPACON = 0x3ffff; gpio->PACON = 0x3ffff;
rPBCON = 0xaaaaaaaa; gpio->PBCON = 0xaaaaaaaa;
rPBUP = 0xffff; gpio->PBUP = 0xffff;
rPECON = 0x0; gpio->PECON = 0x0;
rPEUP = 0x0; gpio->PEUP = 0x0;
#ifdef CONFIG_HWFLOW #ifdef CONFIG_HWFLOW
/*CTS[0] RTS[0] INPUT INPUT TXD[0] INPUT RXD[0] */ /*CTS[0] RTS[0] INPUT INPUT TXD[0] INPUT RXD[0] */
/* 10, 10, 00, 00, 10, 00, 10 */ /* 10, 10, 00, 00, 10, 00, 10 */
rPFCON=0xa22; gpio->PFCON=0xa22;
/* Disable pull-up on Rx, Tx, CTS and RTS pins */ /* Disable pull-up on Rx, Tx, CTS and RTS pins */
rPFUP=0x35; gpio->PFUP=0x35;
#else #else
/*INPUT INPUT INPUT INPUT TXD[0] INPUT RXD[0] */ /*INPUT INPUT INPUT INPUT TXD[0] INPUT RXD[0] */
/* 00, 00, 00, 00, 10, 00, 10 */ /* 00, 00, 00, 00, 10, 00, 10 */
rPFCON = 0x22; gpio->PFCON = 0x22;
/* Disable pull-up on Rx and Tx pins */ /* Disable pull-up on Rx and Tx pins */
rPFUP = 0x5; gpio->PFUP = 0x5;
#endif /* CONFIG_HWFLOW */ #endif /* CONFIG_HWFLOW */
rPGCON = 0x0; gpio->PGCON = 0x0;
rPGUP = 0x0; gpio->PGUP = 0x0;
rOPENCR = 0x0; gpio->OPENCR = 0x0;
/* arch number of SAMSUNG-Board to MACH_TYPE_SMDK2400 */ /* arch number of SAMSUNG-Board to MACH_TYPE_SMDK2400 */
gd->bd->bi_arch_number = 145; gd->bd->bi_arch_number = 145;
......
...@@ -16,10 +16,10 @@ ...@@ -16,10 +16,10 @@
# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 # Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
# optionally with a ramdisk at 3080'0000 # optionally with a ramdisk at 3080'0000
# #
# we load ourself to 33F0'0000 # we load ourself to 33F8'0000
# #
# download area is 3300'0000 # download area is 3300'0000
# #
TEXT_BASE = 0x33F00000 TEXT_BASE = 0x33F80000
...@@ -68,38 +68,40 @@ static inline void delay (unsigned long loops) ...@@ -68,38 +68,40 @@ static inline void delay (unsigned long loops)
int board_init (void) int board_init (void)
{ {
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
/* to reduce PLL lock time, adjust the LOCKTIME register */ /* to reduce PLL lock time, adjust the LOCKTIME register */
rLOCKTIME = 0xFFFFFF; clk_power->LOCKTIME = 0xFFFFFF;
/* configure MPLL */ /* configure MPLL */
rMPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
/* some delay between MPLL and UPLL */ /* some delay between MPLL and UPLL */
delay (4000); delay (4000);
/* configure UPLL */ /* configure UPLL */
rUPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
/* some delay between MPLL and UPLL */ /* some delay between MPLL and UPLL */
delay (8000); delay (8000);
/* set up the I/O ports */ /* set up the I/O ports */
rGPACON = 0x007FFFFF; gpio->GPACON = 0x007FFFFF;
rGPBCON = 0x00044555; gpio->GPBCON = 0x00044555;
rGPBUP = 0x000007FF; gpio->GPBUP = 0x000007FF;
rGPCCON = 0xAAAAAAAA; gpio->GPCCON = 0xAAAAAAAA;
rGPCUP = 0x0000FFFF; gpio->GPCUP = 0x0000FFFF;
rGPDCON = 0xAAAAAAAA; gpio->GPDCON = 0xAAAAAAAA;
rGPDUP = 0x0000FFFF; gpio->GPDUP = 0x0000FFFF;
rGPECON = 0xAAAAAAAA; gpio->GPECON = 0xAAAAAAAA;
rGPEUP = 0x0000FFFF; gpio->GPEUP = 0x0000FFFF;
rGPFCON = 0x000055AA; gpio->GPFCON = 0x000055AA;
rGPFUP = 0x000000FF; gpio->GPFUP = 0x000000FF;
rGPGCON = 0xFF95FFBA; gpio->GPGCON = 0xFF95FFBA;
rGPGUP = 0x0000FFFF; gpio->GPGUP = 0x0000FFFF;
rGPHCON = 0x002AFAAA; gpio->GPHCON = 0x002AFAAA;
rGPHUP = 0x000007FF; gpio->GPHUP = 0x000007FF;
/* arch number of SMDK2410-Board */ /* arch number of SMDK2410-Board */
gd->bd->bi_arch_number = 193; gd->bd->bi_arch_number = 193;
......
...@@ -71,37 +71,39 @@ int board_init () ...@@ -71,37 +71,39 @@ int board_init ()
extern int vfd_init_clocks(void); extern int vfd_init_clocks(void);
#endif #endif
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
/* memory and cpu-speed are setup before relocation */ /* memory and cpu-speed are setup before relocation */
#ifdef CONFIG_TRAB_50MHZ #ifdef CONFIG_TRAB_50MHZ
/* change the clock to be 50 MHz 1:1:1 */ /* change the clock to be 50 MHz 1:1:1 */
/* MDIV:0x5c PDIV:4 SDIV:2 */ /* MDIV:0x5c PDIV:4 SDIV:2 */
rMPLLCON = 0x5c042; clk_power->MPLLCON = 0x5c042;
rCLKDIVN = 0; clk_power->CLKDIVN = 0;
#else #else
/* change the clock to be 133 MHz 1:2:4 */ /* change the clock to be 133 MHz 1:2:4 */
/* MDIV:0x7d PDIV:4 SDIV:1 */ /* MDIV:0x7d PDIV:4 SDIV:1 */
rMPLLCON = 0x7d041; clk_power->MPLLCON = 0x7d041;
rCLKDIVN = 3; clk_power->CLKDIVN = 3;
#endif #endif
/* set up the I/O ports */ /* set up the I/O ports */
rPACON = 0x3ffff; gpio->PACON = 0x3ffff;
rPBCON = 0xaaaaaaaa; gpio->PBCON = 0xaaaaaaaa;
rPBUP = 0xffff; gpio->PBUP = 0xffff;
/* INPUT nCTS0 nRTS0 TXD[1] TXD[0] RXD[1] RXD[0] */ /* INPUT nCTS0 nRTS0 TXD[1] TXD[0] RXD[1] RXD[0] */
/* 00, 10, 10, 10, 10, 10, 10 */ /* 00, 10, 10, 10, 10, 10, 10 */
rPFCON = (2<<0) | (2<<2) | (2<<4) | (2<<6) | (2<<8) | (2<<10); gpio->PFCON = (2<<0) | (2<<2) | (2<<4) | (2<<6) | (2<<8) | (2<<10);
#ifdef CONFIG_HWFLOW #ifdef CONFIG_HWFLOW
/* do not pull up RXD0, RXD1, TXD0, TXD1, CTS0, RTS0 */ /* do not pull up RXD0, RXD1, TXD0, TXD1, CTS0, RTS0 */
rPFUP = (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5); gpio->PFUP = (1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<4) | (1<<5);