Commit 499b8475 authored by Matthias Schiffer's avatar Matthias Schiffer Committed by Daniel Schwierzeck
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MIPS: fix mips_cache fallback without __builtin_mips_cache

The "R" constraint supplies the address of an variable in a register. Use
"r" instead and adjust asm to supply the content of addr in a register

Fixes: 2b8bcc5a

 ("MIPS: avoid .set ISA for cache operations")
Signed-off-by: default avatarMatthias Schiffer <>
Cc: Paul Burton <>
Cc: Daniel Schwierzeck <>
parent deff6fb3
......@@ -16,7 +16,7 @@ static inline void mips_cache(int op, const volatile void *addr)
__builtin_mips_cache(op, addr);
__asm__ __volatile__("cache %0, %1" : : "i"(op), "R"(addr));
__asm__ __volatile__("cache %0, 0(%1)" : : "i"(op), "r"(addr));
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