Commit 4af34177 authored by Wolfgang Denk's avatar Wolfgang Denk Committed by Jean-Christophe PLAGNIOL-VILLARD
Browse files

Monahans: avoid floating point calculations



Current code for the Monahans CPU defined OSCR_CLK_FREQ as 3.250 (MHz)
which caused floating point operations to be used. This resulted in
unresolved references to some FP related libgcc functions when using
U-Boot's private libgcc functions.

Change the code to use fixed point math only.
Signed-off-by: default avatarWolfgang Denk <wd@denx.de>
parent 7dedefdf
......@@ -193,7 +193,7 @@ static unsigned long get_delta(unsigned long start)
static void wait_us(unsigned long us)
{
unsigned long start = OSCR;
us *= OSCR_CLK_FREQ;
us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000);
while (get_delta(start) < us) {
/* do nothing */
......@@ -214,9 +214,11 @@ static unsigned long dfc_wait_event(unsigned long event)
if(!event)
return 0xff000000;
else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
timeout = CONFIG_SYS_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ;
timeout = DIV_ROUND_UP(CONFIG_SYS_NAND_PROG_ERASE_TO
* OSCR_CLK_FREQ, 1000);
else
timeout = CONFIG_SYS_NAND_OTHER_TO * OSCR_CLK_FREQ;
timeout = DIV_ROUND_UP(CONFIG_SYS_NAND_OTHER_TO
* OSCR_CLK_FREQ, 1000);
while(1) {
ndsr = NDSR;
......
......@@ -198,7 +198,7 @@ static unsigned long get_delta(unsigned long start)
static void wait_us(unsigned long us)
{
unsigned long start = OSCR;
us *= OSCR_CLK_FREQ;
us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000);
while (get_delta(start) < us) {
/* do nothing */
......@@ -219,9 +219,11 @@ static unsigned long dfc_wait_event(unsigned long event)
if(!event)
return 0xff000000;
else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
timeout = CONFIG_SYS_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ;
timeout = DIV_ROUND_UP(CONFIG_SYS_NAND_PROG_ERASE_TO
* OSCR_CLK_FREQ, 1000);
else
timeout = CONFIG_SYS_NAND_OTHER_TO * OSCR_CLK_FREQ;
timeout = DIV_ROUND_UP(CONFIG_SYS_NAND_OTHER_TO
* OSCR_CLK_FREQ, 1000);
while(1) {
ndsr = NDSR;
......
......@@ -1094,7 +1094,7 @@ typedef void (*ExcpHndlr) (void) ;
#define OMCR10 __REG(0x40A000D8) /* OS Match Control Register 10 */
#define OMCR11 __REG(0x40A000DC) /* OS Match Control Register 11 */
#define OSCR_CLK_FREQ 3.250 /* MHz */
#define OSCR_CLK_FREQ 3250 /* kHz = 3.25 MHz */
#endif /* CONFIG_CPU_MONAHANS */
#define OSSR_M4 (1 << 4) /* Match status channel 4 */
......
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