Merge with rsync://git-user@source.denx.net/git/u-boot.git

4b1d95d9 · Jon Loeliger · de1d0a69 · 095b8a37 · 4b1d95d9 · 4b1d95d9
Commit 4b1d95d9 authored Aug 02, 2005 by Jon Loeliger
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -46,6 +46,29 @@ Changes for U-Boot 1.1.3:
    Eliminates the CONFIG_MPC8560 option entirely.  Distributes the
    new CONFIG_CPM2 option to each 8260 board.

+* Patch by Stefan Roese, 01 Aug 2005:
+  - Major cleanup for AMCC eval boards Walnut, Bubinga, Ebony, Ocotea
+    (former IBM eval board). Please see "doc/README.AMCC-eval-boards-cleanup"
+    for details.
+  - Sycamore (PPC405GPr) eval board added (Walnut port is extended
+    to run on both 405GP and 405GPr eval boards).
+
+* Patch by Steven Blakeslee, 27 Jul 2005:
+  - Add support for AMCC PPC440EP/GR.
+  - Add support for AMCC Yosemite PPC440EP eval board.
+  - Add support for AMCC Yellowstone PPC440GR eval board.
+
+* Minor fixes for PPChameleon Board:
+  - fix alignment of NAND size
+  - make code do what the comment says
+
+* Implement h/w sector protection status synchronization at boot.
+  The code is provided for, and was tested on, the Yukon/Alaska
+  and PM520 boards only.
+
+  A bug in flash_real_protect() for the Yukon board was fixed by
+  adding a function that tells if two banks are on one flash chip.
+
 * Fix sysmon POST problem: check I2C error codes
  This fixes a problem of displaying bogus voltages when the voltages
  are so low that the I2C devices start failing while the rest of the

--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -210,6 +210,11 @@ Keith Outwater <Keith_Outwater@mvis.com>
 	GEN860T			MPC860T
 	GEN860T_SC		MPC860T

+Stefan Roese <sr@denx.de>
+
+	sycamore		PPC4xx
+	walnut			PPC4xx
+
 Frank Panno <fpanno@delphintech.com>

 	ep8260			MPC8260
@@ -327,7 +332,6 @@ Unknown / orphaned boards:

 	CRAYL1			PPC4xx
 	ERIC			PPC4xx
-	WALNUT405		PPC4xx

 	MOUSSE			MPC824x


--- a/MAKEALL
+++ b/MAKEALL
@@ -60,16 +60,17 @@ LIST_8xx="	\
 #########################################################################

 LIST_4xx="	\
-	ADCIOP		AR405		ASH405		BUBINGA405EP	\
+	ADCIOP		AR405		ASH405		bubinga	        \
 	CANBT		CPCI405		CPCI4052	CPCI405AB	\
 	CPCI440		CPCIISER4	CRAYL1		csb272		\
 	csb472		DASA_SIM	DP405		DU405		\
-	EBONY		ERIC		EXBITGEN	HUB405		\
+	ebony		ERIC		EXBITGEN	HUB405		\
 	JSE		MIP405		MIP405T		ML2		\
-	ml300		OCOTEA		OCRTC		ORSG		\
+	ml300		ocotea		OCRTC		ORSG		\
 	PCI405		PIP405		PLU405		PMC405		\
 	PPChameleonEVB	VOH405		W7OLMC		W7OLMG		\
-	WALNUT405	WUH405          XPEDITE1K			\
+	walnut	        WUH405          XPEDITE1K	yellowstone     \
+	yosemite                                                        \
 "

 #########################################################################

--- a/Makefile
+++ b/Makefile
@@ -710,8 +710,11 @@ AR405_config:	unconfig
 ASH405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx ash405 esd

-BUBINGA405EP_config:	unconfig
-	@./mkconfig $(@:_config=) ppc ppc4xx bubinga405ep
+bamboo_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx bamboo amcc
+
+bubinga_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx bubinga amcc

 CANBT_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx canbt esd
@@ -762,8 +765,8 @@ DP405_config:	unconfig
 DU405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx du405 esd

-EBONY_config:	unconfig
-	@./mkconfig $(@:_config=) ppc ppc4xx ebony
+ebony_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx ebony amcc

 ERIC_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx eric
@@ -797,8 +800,8 @@ ML2_config:	unconfig
 ml300_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx ml300 xilinx

-OCOTEA_config:	unconfig
-	@./mkconfig $(@:_config=) ppc ppc4xx ocotea
+ocotea_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx ocotea amcc

 OCRTC_config		\
 ORSG_config:	unconfig
@@ -849,6 +852,10 @@ PPChameleonEVB_HI_33_config:	unconfig
 sbc405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx sbc405

+sycamore_config:	unconfig
+	@echo "Configuring for sycamore board as subset of walnut..."
+	@./mkconfig -a walnut ppc ppc4xx walnut amcc
+
 VOH405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx voh405 esd

@@ -859,8 +866,8 @@ W7OLMC_config	\
 W7OLMG_config: unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx w7o

-WALNUT405_config:	unconfig
-	@./mkconfig $(@:_config=) ppc ppc4xx walnut405
+walnut_config: unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx walnut amcc

 WUH405_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx wuh405 esd
@@ -868,6 +875,12 @@ WUH405_config:	unconfig
 XPEDITE1K_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx xpedite1k

+yosemite_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx yosemite amcc
+
+yellowstone_config:	unconfig
+	@./mkconfig $(@:_config=) ppc ppc4xx yellowstone amcc
+
 #########################################################################
 ## MPC8220 Systems
 #########################################################################

--- a/README
+++ b/README
@@ -295,7 +295,7 @@ The following options need to be configured:
 		CONFIG_FADS823		CONFIG_NETTA		CONFIG_V37
 		CONFIG_FADS850SAR	CONFIG_NETVIA		CONFIG_W7OLMC
 		CONFIG_FADS860T		CONFIG_NX823		CONFIG_W7OLMG
-		CONFIG_FLAGADM		CONFIG_OCRTC		CONFIG_WALNUT405
+		CONFIG_FLAGADM		CONFIG_OCRTC		CONFIG_WALNUT
 		CONFIG_FPS850L		CONFIG_ORSG		CONFIG_ZPC1900
 		CONFIG_FPS860L		CONFIG_OXC		CONFIG_ZUMA

@@ -2192,7 +2192,7 @@ configurations; the following names are supported:
 	FADS850SAR_config	omap1510inn_config	TQM850L_config
 	FADS860T_config		omap1610h2_config	TQM855L_config
 	FPS850L_config		omap1610inn_config	TQM860L_config
-				omap5912osk_config	WALNUT405_config
+				omap5912osk_config	walnut_config
 				omap2420h4_config	Yukon8220_config
 							ZPC1900_config

@@ -3135,7 +3135,7 @@ locked as (mis-) used as memory, etc.
 	CFG_INIT_RAM_ADDR should be somewhere that won't interfere
 	with your processor/board/system design. The default value
 	you will find in any recent u-boot distribution in
-	Walnut405.h should work for you. I'd set it to a value larger
+	walnut.h should work for you. I'd set it to a value larger
 	than your SDRAM module. If you have a 64MB SDRAM module, set
 	it above 400_0000. Just make sure your board has no resources
 	that are supposed to respond to that address! That code in

--- a/board/alaska/flash.c
+++ b/board/alaska/flash.c
@@ -64,7 +64,6 @@ typedef volatile unsigned char FLASH_PORT_WIDTHV;
 #define FLASH_CYCLE2    0x02aa

 #define WR_BLOCK        0x20
-
 /*-----------------------------------------------------------------------
 * Functions
 */
@@ -74,6 +73,9 @@ static int write_data_block (flash_info_t * info, ulong src, ulong dest);
 static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data);
 static void flash_get_offsets (ulong base, flash_info_t * info);
 void inline spin_wheel (void);
+static void flash_sync_real_protect (flash_info_t * info);
+static unsigned char intel_sector_protected (flash_info_t *info, ushort sector);
+static unsigned char same_chip_banks (int bank1, int bank2);

 /*-----------------------------------------------------------------------
 */
@@ -115,6 +117,9 @@ unsigned long flash_init (void)
 			break;
 		}
 		size += flash_info[i].size;
+
+		/* get the h/w and s/w protection status in sync */
+		flash_sync_real_protect(&flash_info[i]);
 	}

 	/* Protect monitor and environment sectors
@@ -167,7 +172,6 @@ static void flash_get_offsets (ulong base, flash_info_t * info)
 	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
 		for (i = 0; i < info->sector_count; i++) {
 			info->start[i] = base + (i * PHYS_INTEL_SECT_SIZE);
-			info->protect[i] = 0;
 		}
 	}
 }
@@ -305,6 +309,98 @@ static ulong flash_get_size (FPW * addr, flash_info_t * info)
 }


+/*
+ * This function gets the u-boot flash sector protection status
+ * (flash_info_t.protect[]) in sync with the sector protection
+ * status stored in hardware.
+ */
+static void flash_sync_real_protect (flash_info_t * info)
+{
+	int i;
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_28F128J3A:
+		for (i = 0; i < info->sector_count; ++i) {
+			info->protect[i] = intel_sector_protected(info, i);
+		}
+		break;
+	case FLASH_AM040:
+	default:
+		/* no h/w protect support */
+		break;
+	}
+}
+
+
+/*
+ * checks if "sector" in bank "info" is protected. Should work on intel
+ * strata flash chips 28FxxxJ3x in 8-bit mode.
+ * Returns 1 if sector is protected (or timed-out while trying to read
+ * protection status), 0 if it is not.
+ */
+static unsigned char intel_sector_protected (flash_info_t *info, ushort sector)
+{
+	FPWV *addr;
+	FPWV *lock_conf_addr;
+	ulong start;
+	unsigned char ret;
+
+	/*
+	 * first, wait for the WSM to be finished. The rationale for
+	 * waiting for the WSM to become idle for at most
+	 * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy
+	 * because of: (1) erase, (2) program or (3) lock bit
+	 * configuration. So we just wait for the longest timeout of
+	 * the (1)-(3), i.e. the erase timeout.
+	 */
+
+	/* wait at least 35ns (W12) before issuing Read Status Register */
+	udelay(1);
+	addr = (FPWV *) info->start[sector];
+	*addr = (FPW) INTEL_STATUS;
+
+	start = get_timer (0);
+	while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
+		if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
+			*addr = (FPW) INTEL_RESET; /* restore read mode */
+			printf("WSM busy too long, can't get prot status\n");
+			return 1;
+		}
+	}
+
+	/* issue the Read Identifier Codes command */
+	*addr = (FPW) INTEL_READID;
+
+	/* wait at least 35ns (W12) before reading */
+	udelay(1);
+
+	/* Intel example code uses offset of 4 for 8-bit flash */
+	lock_conf_addr = (FPWV *) info->start[sector] + 4;
+	ret = (*lock_conf_addr & (FPW) INTEL_PROTECT) ? 1 : 0;
+
+	/* put flash back in read mode */
+	*addr = (FPW) INTEL_RESET;
+
+	return ret;
+}
+
+
+/*
+ * Checks if "bank1" and "bank2" are on the same chip.  Returns 1 if they
+ * are and 0 otherwise.
+ */
+static unsigned char same_chip_banks (int bank1, int bank2)
+{
+	unsigned char same_chip[CFG_MAX_FLASH_BANKS][CFG_MAX_FLASH_BANKS] = {
+		{1, 1, 0, 0},
+		{1, 1, 0, 0},
+		{0, 0, 1, 1},
+		{0, 0, 1, 1}
+	};
+	return same_chip[bank1][bank2];
+}
+
+
 /*-----------------------------------------------------------------------
 */
 int flash_erase (flash_info_t * info, int s_first, int s_last)
@@ -729,7 +825,9 @@ void inline spin_wheel (void)
 int flash_real_protect (flash_info_t * info, long sector, int prot)
 {
 	ulong start;
-	int i;
+	int i, j;
+	int curr_bank;
+	int bank;
 	int rc = 0;
 	FPWV *addr = (FPWV *) (info->start[sector]);
 	int flag = disable_interrupts ();
@@ -779,23 +877,54 @@ int flash_real_protect (flash_info_t * info, long sector, int prot)
 	 * we have to restore lock bits of protected sectors.
 	 */
 	if (!prot) {
-		for (i = 0; i < info->sector_count; i++) {
-			if (info->protect[i]) {
-				start = get_timer (0);
-				addr = (FPWV *) (info->start[i]);
-				*addr = INTEL_LOCKBIT;	/* Sector lock bit  */
-				*addr = INTEL_PROTECT;	/* set              */
-				while ((*addr & INTEL_FINISHED) !=
-				       INTEL_FINISHED) {
-					if (get_timer (start) >
-					    CFG_FLASH_UNLOCK_TOUT) {
-						printf ("Flash lock bit operation timed out\n");
-						rc = 1;
-						break;
+		/*
+		 * re-locking must be done for all banks that belong on one
+		 * FLASH chip, as all the sectors on the chip were unlocked
+		 * by INTEL_LOCKBIT/INTEL_CONFIRM commands. (let's hope
+		 * that banks never span chips, in particular chips which
+		 * support h/w protection differently).
+		 */
+
+		/* find the current bank number */
+		curr_bank = CFG_MAX_FLASH_BANKS + 1;
+		for (j = 0; j < CFG_MAX_FLASH_BANKS; ++j) {
+			if (&flash_info[j] == info) {
+				curr_bank = j;
+			}
+		}
+		if (curr_bank == CFG_MAX_FLASH_BANKS + 1) {
+			printf("Error: can't determine bank number!\n");
+		}
+
+		for (bank = 0; bank < CFG_MAX_FLASH_BANKS; ++bank) {
+			if (!same_chip_banks(curr_bank, bank)) {
+				continue;
+			}
+			info = &flash_info[bank];
+			for (i = 0; i < info->sector_count; i++) {
+				if (info->protect[i]) {
+					start = get_timer (0);
+					addr = (FPWV *) (info->start[i]);
+					*addr = INTEL_LOCKBIT;	/* Sector lock bit  */
+					*addr = INTEL_PROTECT;	/* set              */
+					while ((*addr & INTEL_FINISHED) !=
+					       INTEL_FINISHED) {
+						if (get_timer (start) >
+						    CFG_FLASH_UNLOCK_TOUT) {
+							printf ("Flash lock bit operation timed out\n");
+							rc = 1;
+							break;
+						}
 					}
 				}
 			}
 		}
+
+		/*
+		 * get the s/w sector protection status in sync with the h/w,
+		 * in case something went wrong during the re-locking.
+		 */
+		flash_sync_real_protect(info); /* resets flash to read  mode */
 	}

 	if (flag)

--- a/board/amcc/bamboo/Makefile
+++ b/board/amcc/bamboo/Makefile
+#
+# (C) Copyright 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	= $(BOARD).o
+#OBJS   += flash.o
+SOBJS	= init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
+/*
+ * (C) Copyright 2005
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <spd_sdram.h>
+
+int board_early_init_f(void)
+{
+	register uint reg;
+
+	/*--------------------------------------------------------------------
+	 * Setup the external bus controller/chip selects
+	 *-------------------------------------------------------------------*/
+	mtdcr(ebccfga, xbcfg);
+	reg = mfdcr(ebccfgd);
+	mtdcr(ebccfgd, reg | 0x04000000);	/* Set ATC */
+
+#if 0 /* test-only */
+	mtebc(pb0ap, 0x03017300);	/* FLASH/SRAM */
+	mtebc(pb0cr, 0xfe0ba000);	/* BAS=0xfe0 32MB r/w 16-bit */
+
+	mtebc(pb1ap, 0x00000000);
+	mtebc(pb1cr, 0x00000000);
+
+	mtebc(pb2ap, 0x04814500);
+	/*CPLD*/ mtebc(pb2cr, 0x80018000);	/*BAS=0x800 1MB r/w 8-bit */
+#else
+	mtebc(pb0ap, 0x04055200);	/* FLASH/SRAM */
+	mtebc(pb0cr, 0xfff18000);	/* BAS=0xfe0 1MB r/w 8-bit */
+#endif
+
+	mtebc(pb3ap, 0x00000000);
+	mtebc(pb3cr, 0x00000000);
+
+	mtebc(pb4ap, 0x00000000);
+	mtebc(pb4cr, 0x00000000);
+
+	mtebc(pb5ap, 0x00000000);
+	mtebc(pb5cr, 0x00000000);
+
+	/*--------------------------------------------------------------------
+	 * Setup the interrupt controller polarities, triggers, etc.
+	 *-------------------------------------------------------------------*/
+	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+	mtdcr(uic0er, 0x00000000);	/* disable all */
+	mtdcr(uic0cr, 0x00000009);	/* ATI & UIC1 crit are critical */
+	mtdcr(uic0pr, 0xfffffe13);	/* per ref-board manual */
+	mtdcr(uic0tr, 0x01c00008);	/* per ref-board manual */
+	mtdcr(uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(uic0sr, 0xffffffff);	/* clear all */
+
+	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+	mtdcr(uic1er, 0x00000000);	/* disable all */
+	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
+	mtdcr(uic1pr, 0xffffe0ff);	/* per ref-board manual */
+	mtdcr(uic1tr, 0x00ffc000);	/* per ref-board manual */
+	mtdcr(uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
+	mtdcr(uic1sr, 0xffffffff);	/* clear all */
+
+	/*--------------------------------------------------------------------
+	 * Setup the GPIO pins
+	 *-------------------------------------------------------------------*/
+	/*CPLD cs */
+	/*setup Address lines for flash sizes larger than 16Meg. */
+	out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000);
+	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000);
+	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000);
+
+	/*setup emac */
+	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
+	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
+	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
+	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
+	out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
+
+	/*UART1 */
+	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
+	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
+	out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
+
+	/*setup USB 2.0 */
+	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
+	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
+	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
+	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
+	out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
+
+	/*--------------------------------------------------------------------
+	 * Setup other serial configuration
+	 *-------------------------------------------------------------------*/
+	mfsdr(sdr_pci0, reg);
+	mtsdr(sdr_pci0, 0x80000000 | reg);	/* PCI arbiter enabled */
+	mtsdr(sdr_pfc0, 0x00003e00);	/* Pin function */
+	mtsdr(sdr_pfc1, 0x00048000);	/* Pin function: UART0 has 4 pins */
+
+#if 0 /* test-only */
+	/*clear tmrclk divisor */
+	*(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
+
+	/*enable ethernet */
+	*(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
+
+	/*enable usb 1.1 fs device and remove usb 2.0 reset */
+	*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
+
+	/*get rid of flash write protect */
+	*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	sys_info_t sysinfo;
+	unsigned char *s = getenv("serial#");
+
+	get_sys_info(&sysinfo);
+
+	printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
+	if (s != NULL) {
+		puts(", serial# ");
+		puts(s);
+	}
+	putc('\n');
+
+	printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
+	printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
+	printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
+	printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
+	printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
+	return (0);
+}
+
+/*************************************************************************
+ *  sdram_init -- doesn't use serial presence detect.
+ *
+ *  Assumes:    256 MB, ECC, non-registered
+ *              PLB @ 133 MHz
+ *
+ ************************************************************************/
+void sdram_init(void)
+{
+	register uint reg;
+
+	/*--------------------------------------------------------------------
+	 * Setup some default
+	 *------------------------------------------------------------------*/
+	mtsdram(mem_uabba, 0x00000000);	/* ubba=0 (default)             */
+	mtsdram(mem_slio, 0x00000000);	/* rdre=0 wrre=0 rarw=0         */
+	mtsdram(mem_devopt, 0x00000000);	/* dll=0 ds=0 (normal)          */
+	mtsdram(mem_clktr, 0x40000000);	/* ?? */
+	mtsdram(mem_wddctr, 0x40000000);	/* ?? */
+
+	/*clear this first, if the DDR is enabled by a debugger
+	   then you can not make changes. */
+	mtsdram(mem_cfg0, 0x00000000);	/* Disable EEC */
+
+	/*--------------------------------------------------------------------
+	 * Setup for board-specific specific mem
+	 *------------------------------------------------------------------*/
+	/*
+	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
+	 */
+	mtsdram(mem_b0cr, 0x000a4001);	/* SDBA=0x000 128MB, Mode 3, enabled */
+	mtsdram(mem_b1cr, 0x080a4001);	/* SDBA=0x080 128MB, Mode 3, enabled */
+
+	mtsdram(mem_tr0, 0x410a4012);	/* ?? */
+	mtsdram(mem_tr1, 0x8080080b);	/* ?? */
+	mtsdram(mem_rtr, 0x04080000);	/* ?? */
+	mtsdram(mem_cfg1, 0x00000000);	/* Self-refresh exit, disable PM    */
+	mtsdram(mem_cfg0, 0x34000000);	/* Disable EEC */
+	udelay(400);		/* Delay 200 usecs (min)            */
+
+	/*--------------------------------------------------------------------
+	 * Enable the controller, then wait for DCEN to complete
+	 *------------------------------------------------------------------*/
+	mtsdram(mem_cfg0, 0x84000000);	/* Enable */
+
+	for (;;) {
+		mfsdram(mem_mcsts, reg);
+		if (reg & 0x80000000)