Commit 507e2d79 authored by Joe D'Abbraccio's avatar Joe D'Abbraccio Committed by Kim Phillips
Browse files

Modified the DDR SDRAM clock control register to delay MCK/MCK_B 3/4 clock

With the original value of 1/2 clock cycle delay, the system ran relatively
stable except when we run benchmarks that are intensive users of memory.
When I run samba connected disk with a HDBENCH test, the system locks-up
or reboots sporadically.

Signed-off by: Joe D'Abbraccio <Joe.D'>
parent a7ba32d4
......@@ -156,7 +156,7 @@
#define CFG_MEMTEST_END 0x2000
#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
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