Commit 511d0c72 authored by Wolfgang Denk's avatar Wolfgang Denk
Browse files

Coding style cleanup

parent 8d4ac794
......@@ -2,6 +2,8 @@
Changes since U-Boot 1.1.4:
======================================================================
* Coding style cleanup
* Add support for EP82xxM boards
Patch by Aaron Sells, 20 Jun 2006
......
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
#
# (C) Copyright 2001
# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
#
......
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
#
# (C) Copyright 2001
# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
#
......
......@@ -4,7 +4,7 @@
*
* (C) Copyright 2006
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
......@@ -123,12 +123,12 @@ int board_early_init_f(void)
/* setup NAND FLASH */
mfsdr(SDR0_CUST0, sdr0_cust0);
sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
SDR0_CUST0_NDFC_ENABLE |
SDR0_CUST0_NDFC_BW_8_BIT |
SDR0_CUST0_NDFC_ARE_MASK |
(0x80000000 >> (28 + CFG_NAND_CS));
mtsdr(SDR0_CUST0, sdr0_cust0);
mtsdr(SDR0_CUST0, sdr0_cust0);
return 0;
}
......@@ -216,38 +216,38 @@ int misc_init_r(void)
#ifdef CONFIG_440EPX
if (act == NULL || strcmp(act, "hostdev") == 0) {
/* SDR Setting */
mfsdr(SDR0_PFC1, sdr0_pfc1);
mfsdr(SDR0_USB0, usb2d0cr);
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mfsdr(SDR0_USB2H0CR, usb2h0cr);
mfsdr(SDR0_PFC1, sdr0_pfc1);
mfsdr(SDR0_USB0, usb2d0cr);
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mfsdr(SDR0_USB2H0CR, usb2h0cr);
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
/* An 8-bit/60MHz interface is the only possible alternative
when connecting the Device to the PHY */
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
/* To enable the USB 2.0 Device function through the UTMI interface */
usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/
/* To enable the USB 2.0 Device function through the UTMI interface */
usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/
sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/
sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/
mtsdr(SDR0_PFC1, sdr0_pfc1);
mtsdr(SDR0_USB0, usb2d0cr);
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mtsdr(SDR0_USB2H0CR, usb2h0cr);
mtsdr(SDR0_PFC1, sdr0_pfc1);
mtsdr(SDR0_USB0, usb2d0cr);
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mtsdr(SDR0_USB2H0CR, usb2h0cr);
/*clear resets*/
udelay (1000);
......@@ -264,11 +264,11 @@ int misc_init_r(void)
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
udelay (1000);
......@@ -287,33 +287,33 @@ int misc_init_r(void)
/*-------------------PATCH-------------------------------*/
/* SDR Setting */
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mfsdr(SDR0_USB2H0CR, usb2h0cr);
mfsdr(SDR0_USB0, usb2d0cr);
mfsdr(SDR0_PFC1, sdr0_pfc1);
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; /*0*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; /*0*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; /*0*/
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; /*0*/
usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; /*0*/
usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0*/
usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0*/
usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; /*0*/
usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; /*0*/
sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1*/
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1*/
mtsdr(SDR0_USB2H0CR, usb2h0cr);
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mtsdr(SDR0_USB2H0CR, usb2h0cr);
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mtsdr(SDR0_USB0, usb2d0cr);
mtsdr(SDR0_PFC1, sdr0_pfc1);
......
......@@ -958,7 +958,6 @@ int is_pci_host(struct pci_controller *hose)
return 1;
}
int yucca_pcie_card_present(int port)
{
u16 reg;
......@@ -1084,8 +1083,6 @@ void yucca_setup_pcie_fpga_endpoint(int port)
(endpoint | in_be16((u16 *)FPGA_REG1C)));
}
static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
void pcie_setup_hoses(void)
......
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
#
# (C) Copyright 2002
# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
# Marius Groeger <mgroeger@sysgo.de>
......
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
#
# (C) Copyright 2001
# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
#
......
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
#
# (C) Copyright 2001
# Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
#
......
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
#
# Copyright (C) 2004 Arabella Software Ltd.
# Yuli Barcohen <yuli@arabellasw.com>
#
......
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
#
# Copyright 2004 Picture Elements, Inc.
# Stephen Williams <steve@icarus.com>
#
......
#
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
......
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
#
# (C) Copyright 2002
# Daniel Engstrm, Omicron Ceti AB, daniel@omicron.se.
#
......
......@@ -46,7 +46,7 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
* swapping is necessary within each 16 bit wide flash 'word'.
*
* This driver's task is to handle both flash devices: 32 bit TQM5200B
* flash chip and 16 bit NIOS cpu flash chip. In the below
* flash chip and 16 bit NIOS cpu flash chip. In the below
* flash_addr_table table we use least significant address bit to mark
* 16 bit flash bank and two sets of routines *_32 and *_16 to handle
* specifics of both flashes.
......
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
#
# Copyright 2004 Freescale Semiconductor, Inc.
#
# See file CREDITS for list of people who contributed to this
......
......@@ -661,8 +661,8 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
* So, in case of Monochrome BMP we should align widths
* on a byte boundary and convert them from Bit to Byte
* units.
* Probably, PXA250 and MPC823 process 1bpp BMP images in
* their own ways, so make the converting to be MCC200
* Probably, PXA250 and MPC823 process 1bpp BMP images in
* their own ways, so make the converting to be MCC200
* specific.
*/
#if defined(CONFIG_MCC200)
......
......@@ -25,7 +25,7 @@
ifneq ($(OBJTREE),$(SRCTREE))
ifeq ($(CURDIR),$(SRCTREE))
dir :=
dir :=
else
dir := $(subst $(SRCTREE)/,,$(CURDIR))
endif
......
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
#
# (C) Copyright 2002
# Daniel Engstrm, Omicron Ceti AB, daniel@omicron.se.
#
......
......@@ -32,7 +32,7 @@
*
* Based on (well, mostly copied from) the code from the 2.4 kernel by
* Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
*
*
* Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
* Copyright (C) 2003 Montavista Software, Inc
*/
......
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
#
# Copyright 2004 Freescale Semiconductor, Inc.
#
# See file CREDITS for list of people who contributed to this
......
......@@ -65,8 +65,8 @@ static void ndfc_hwcontrol(struct mtd_info *mtdinfo, int cmd)
static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte)
{
struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W;
struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W;
if (hwctl & 0x1)
out8(base + NDFC_CMD, byte);
......@@ -78,16 +78,16 @@ static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte)
static u_char ndfc_read_byte(struct mtd_info *mtdinfo)
{
struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W;
struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W;
return (in8(base + NDFC_DATA));
}
static int ndfc_dev_ready(struct mtd_info *mtdinfo)
{
struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W;
struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W;
while (!(in32(base + NDFC_STAT) & NDFC_STAT_IS_READY))
;
......@@ -110,8 +110,8 @@ static int ndfc_dev_ready(struct mtd_info *mtdinfo)
*/
static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
{
struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W;
struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W;
uint32_t *p = (uint32_t *) buf;
for(;len > 0; len -= 4)
......@@ -120,8 +120,8 @@ static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
{
struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W;
struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W;
uint32_t *p = (uint32_t *) buf;
for(; len > 0; len -= 4)
......@@ -130,8 +130,8 @@ static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len
static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
{
struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W;
struct nand_chip *this = mtdinfo->priv;
ulong base = (ulong) this->IO_ADDR_W;
uint32_t *p = (uint32_t *) buf;
for(; len > 0; len -= 4)
......
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