Commit 51e9dad2 authored by Simon Glass's avatar Simon Glass
Browse files

x86: Add support for panther (Asus Chromebox)



Support running U-Boot as a coreboot payload. Tested peripherals include:

- Video (HDMI and DisplayPort)
- SATA disk
- Gigabit Ethernet
- SPI flash

USB3 does not work. This may be a problem with the USB3 PCI driver or
something in the USB3 stack and has not been investigated So far this is
disabled. The SD card slot also does not work.

For video, coreboot will need to run the OPROM to set this up.

With this board, bare support (running without coreboot) is not available
as yet.
Signed-off-by: default avatarSimon Glass <sjg@chromium.org>
parent cc285c56
......@@ -32,6 +32,20 @@ config TARGET_CHROMEBOOK_LINK
and it provides a 2560x1700 high resolution touch-enabled LCD
display.
config TARGET_CHROMEBOX_PANTHER
bool "Support Chromebox panther (not available)"
select n
help
Note: At present this must be used with Coreboot. See README.x86
for instructions.
This is the Asus Chromebox CN60 released in 2014. It uses an Intel
Haswell Celeron 2955U Dual Core CPU with 2GB of SDRAM. It has a
Lynx Point platform controller hub, PCIe WiFi and Bluetooth. It also
includes a USB SD reader, four USB3 ports, display port and HDMI
video output and a 16GB SATA solid state drive. There is no Chrome
OS EC on this model.
config TARGET_CROWNBAY
bool "Support Intel Crown Bay CRB"
help
......@@ -432,6 +446,8 @@ source "board/coreboot/coreboot/Kconfig"
source "board/google/chromebook_link/Kconfig"
source "board/google/chromebox_panther/Kconfig"
source "board/intel/crownbay/Kconfig"
source "board/intel/minnowmax/Kconfig"
......
dtb-y += chromebook_link.dtb \
chromebox_panther.dtb \
crownbay.dtb \
galileo.dtb \
minnowmax.dtb
......
/dts-v1/;
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/ {
model = "Google Panther";
compatible = "google,panther", "intel,haswell";
aliases {
spi0 = "/spi";
};
config {
silent-console = <0>;
no-keyboard;
};
gpioa {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0 0x10>;
bank-name = "A";
};
gpiob {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0x30 0x10>;
bank-name = "B";
};
gpioc {
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
reg = <0x40 0x10>;
bank-name = "C";
};
chosen {
stdout-path = "/serial";
};
spi {
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ich-spi";
spi-flash@0 {
#size-cells = <1>;
#address-cells = <1>;
reg = <0>;
compatible = "winbond,w25q64", "spi-flash";
memory-map = <0xff800000 0x00800000>;
rw-mrc-cache {
label = "rw-mrc-cache";
/* Alignment: 4k (for updating) */
reg = <0x003e0000 0x00010000>;
type = "wiped";
wipe-value = [ff];
};
};
};
};
if TARGET_CHROMEBOX_PANTHER
config SYS_BOARD
default "chromebox_panther"
config SYS_VENDOR
default "google"
config SYS_SOC
default "ivybridge"
config SYS_CONFIG_NAME
default "chromebox_panther"
# Panther actually uses haswell, not ivybridge, so this is just a placeholder
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select X86_RESET_VECTOR
select CPU_INTEL_SOCKET_RPGA989
select NORTHBRIDGE_INTEL_IVYBRIDGE
select SOUTHBRIDGE_INTEL_C216
select HAVE_ACPI_RESUME
select MARK_GRAPHICS_MEM_WRCOMB
select BOARD_ROMSIZE_KB_8192
config SYS_CAR_ADDR
hex
default 0xff7e0000
config SYS_CAR_SIZE
hex
default 0x20000
endif
CHROMEBOX PANTHER BOARD
M: Simon Glass <sjg@chromium.org>
S: Maintained
F: board/google/chromebook_panther/
F: include/configs/chromebox_panther.h
F: configs/chromebox_panther_defconfig
#
# Copyright (c) 2015 Google, Inc
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += panther.o
/*
* Copyright (C) 2015 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/pch.h>
int arch_early_init_r(void)
{
return 0;
}
int board_early_init_f(void)
{
return 0;
}
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
{
}
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000"
CONFIG_X86=y
CONFIG_TARGET_CHROMEBOX_PANTHER=y
CONFIG_OF_CONTROL=y
CONFIG_OF_SEPARATE=y
CONFIG_DEFAULT_DEVICE_TREE="chromebox_panther"
CONFIG_HAVE_MRC=y
CONFIG_SMM_TSEG_SIZE=0x800000
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
/*
* Copyright (c) 2011 The Chromium OS Authors.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <configs/x86-common.h>
#include <configs/x86-chromebook.h>
#define CONFIG_RTL8169
/* Avoid a warning in the Realtek Ethernet driver */
#define CONFIG_SYS_CACHELINE_SIZE 16
#endif /* __CONFIG_H */
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