Commit 5289e83a authored by Chandan Nath's avatar Chandan Nath Committed by Albert ARIBAUD
Browse files

ARM:AM33XX: Add support for TI AM335X EVM



This patch adds basic support for booting the board.
This patch adds support for the UART necessary to
get to the u-boot prompt.
Signed-off-by: default avatarChandan Nath <chandan.nath@ti.com>
Signed-off-by: default avatarSandeep Paulraj <s-paulraj@ti.com>
parent f0f4b5ff
......@@ -738,6 +738,10 @@ Nagendra T S <nagendra@mistralsolutions.com>
am3517_crane ARM ARMV7 (AM35x SoC)
Chandan Nath <chandan.nath@ti.com>
am335x_evm ARM ARMV7 (AM33xx Soc)
Kyungmin Park <kyungmin.park@samsung.com>
apollon ARM1136EJS
......
......@@ -22,7 +22,7 @@ COBJS += clock.o
COBJS += sys_info.o
COBJS += ddr.o
COBJS += emif4.o
COBJS += board.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
......
/*
* board.c
*
* Common board functions for AM33XX based boards
*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
* GNU General Public License for more details.
*/
#include <common.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
struct timer_reg *timerreg = (struct timer_reg *)DM_TIMER2_BASE;
/*
* early system init of muxing and clocks.
*/
void s_init(u32 in_ddr)
{
/* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
*/
writel(0xAAAA, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
writel(0x5555, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
/* Setup the PLLs and the clocks for the peripherals */
#ifdef CONFIG_SETUP_PLL
pll_init();
#endif
if (!in_ddr)
config_ddr();
}
/* Initialize timer */
void init_timer(void)
{
/* Reset the Timer */
writel(0x2, (&timerreg->tsicrreg));
/* Wait until the reset is done */
while (readl(&timerreg->tiocpcfgreg) & 1)
;
/* Start the Timer */
writel(0x1, (&timerreg->tclrreg));
}
#
# Makefile
#
# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed "as is" WITHOUT ANY WARRANTY of any
# kind, whether express or implied; without even the implied warranty
# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS := evm.o mux.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
/*
* common_def.h
*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __COMMON_DEF_H__
#define __COMMON_DEF_H__
extern void enable_uart0_pin_mux(void);
extern void configure_evm_pin_mux(unsigned char daughter_board_id,
unsigned short daughter_board_profile,
unsigned char daughter_board_flag);
#endif/*__COMMON_DEF_H__ */
/*
* evm.c
*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <common.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include "common_def.h"
#include <serial.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_RESET (0x1 << 1)
#define UART_CLK_RUNNING_MASK 0x1
#define UART_SMART_IDLE_EN (0x1 << 0x3)
/*
* Basic board specific setup
*/
int init_basic_setup(void)
{
/* Initialize the Timer */
init_timer();
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
return 0;
}
int board_init(void)
{
enable_uart0_pin_mux();
init_basic_setup();
return 0;
}
/*
* mux.c
*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <config.h>
#include "common_def.h"
#include <asm/arch/hardware.h>
#include <asm/io.h>
#define MUX_CFG(value, offset) \
__raw_writel(value, (CTRL_BASE + offset));
/* PAD Control Fields */
#define SLEWCTRL (0x1 << 6)
#define RXACTIVE (0x1 << 5)
#define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
#define PULLUDEN (0x0 << 3) /* Pull up enabled */
#define PULLUDDIS (0x1 << 3) /* Pull up disabled */
#define MODE(val) val /* used for Readability */
/*
* PAD CONTROL OFFSETS
* Field names corresponds to the pad signal name
*/
struct pad_signals {
int gpmc_ad0;
int gpmc_ad1;
int gpmc_ad2;
int gpmc_ad3;
int gpmc_ad4;
int gpmc_ad5;
int gpmc_ad6;
int gpmc_ad7;
int gpmc_ad8;
int gpmc_ad9;
int gpmc_ad10;
int gpmc_ad11;
int gpmc_ad12;
int gpmc_ad13;
int gpmc_ad14;
int gpmc_ad15;
int gpmc_a0;
int gpmc_a1;
int gpmc_a2;
int gpmc_a3;
int gpmc_a4;
int gpmc_a5;
int gpmc_a6;
int gpmc_a7;
int gpmc_a8;
int gpmc_a9;
int gpmc_a10;
int gpmc_a11;
int gpmc_wait0;
int gpmc_wpn;
int gpmc_be1n;
int gpmc_csn0;
int gpmc_csn1;
int gpmc_csn2;
int gpmc_csn3;
int gpmc_clk;
int gpmc_advn_ale;
int gpmc_oen_ren;
int gpmc_wen;
int gpmc_be0n_cle;
int lcd_data0;
int lcd_data1;
int lcd_data2;
int lcd_data3;
int lcd_data4;
int lcd_data5;
int lcd_data6;
int lcd_data7;
int lcd_data8;
int lcd_data9;
int lcd_data10;
int lcd_data11;
int lcd_data12;
int lcd_data13;
int lcd_data14;
int lcd_data15;
int lcd_vsync;
int lcd_hsync;
int lcd_pclk;
int lcd_ac_bias_en;
int mmc0_dat3;
int mmc0_dat2;
int mmc0_dat1;
int mmc0_dat0;
int mmc0_clk;
int mmc0_cmd;
int mii1_col;
int mii1_crs;
int mii1_rxerr;
int mii1_txen;
int mii1_rxdv;
int mii1_txd3;
int mii1_txd2;
int mii1_txd1;
int mii1_txd0;
int mii1_txclk;
int mii1_rxclk;
int mii1_rxd3;
int mii1_rxd2;
int mii1_rxd1;
int mii1_rxd0;
int rmii1_refclk;
int mdio_data;
int mdio_clk;
int spi0_sclk;
int spi0_d0;
int spi0_d1;
int spi0_cs0;
int spi0_cs1;
int ecap0_in_pwm0_out;
int uart0_ctsn;
int uart0_rtsn;
int uart0_rxd;
int uart0_txd;
int uart1_ctsn;
int uart1_rtsn;
int uart1_rxd;
int uart1_txd;
int i2c0_sda;
int i2c0_scl;
int mcasp0_aclkx;
int mcasp0_fsx;
int mcasp0_axr0;
int mcasp0_ahclkr;
int mcasp0_aclkr;
int mcasp0_fsr;
int mcasp0_axr1;
int mcasp0_ahclkx;
int xdma_event_intr0;
int xdma_event_intr1;
int nresetin_out;
int porz;
int nnmi;
int osc0_in;
int osc0_out;
int rsvd1;
int tms;
int tdi;
int tdo;
int tck;
int ntrst;
int emu0;
int emu1;
int osc1_in;
int osc1_out;
int pmic_power_en;
int rtc_porz;
int rsvd2;
int ext_wakeup;
int enz_kaldo_1p8v;
int usb0_dm;
int usb0_dp;
int usb0_ce;
int usb0_id;
int usb0_vbus;
int usb0_drvvbus;
int usb1_dm;
int usb1_dp;
int usb1_ce;
int usb1_id;
int usb1_vbus;
int usb1_drvvbus;
int ddr_resetn;
int ddr_csn0;
int ddr_cke;
int ddr_ck;
int ddr_nck;
int ddr_casn;
int ddr_rasn;
int ddr_wen;
int ddr_ba0;
int ddr_ba1;
int ddr_ba2;
int ddr_a0;
int ddr_a1;
int ddr_a2;
int ddr_a3;
int ddr_a4;
int ddr_a5;
int ddr_a6;
int ddr_a7;
int ddr_a8;
int ddr_a9;
int ddr_a10;
int ddr_a11;
int ddr_a12;
int ddr_a13;
int ddr_a14;
int ddr_a15;
int ddr_odt;
int ddr_d0;
int ddr_d1;
int ddr_d2;
int ddr_d3;
int ddr_d4;
int ddr_d5;
int ddr_d6;
int ddr_d7;
int ddr_d8;
int ddr_d9;
int ddr_d10;
int ddr_d11;
int ddr_d12;
int ddr_d13;
int ddr_d14;
int ddr_d15;
int ddr_dqm0;
int ddr_dqm1;
int ddr_dqs0;
int ddr_dqsn0;
int ddr_dqs1;
int ddr_dqsn1;
int ddr_vref;
int ddr_vtp;
int ddr_strben0;
int ddr_strben1;
int ain7;
int ain6;
int ain5;
int ain4;
int ain3;
int ain2;
int ain1;
int ain0;
int vrefp;
int vrefn;
};
struct module_pin_mux {
short reg_offset;
unsigned char val;
};
/* Pad control register offset */
#define PAD_CTRL_BASE 0x800
#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
(PAD_CTRL_BASE))->x)
static struct module_pin_mux uart0_pin_mux[] = {
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
{-1},
};
/*
* Configure the pin mux for the module
*/
static void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux)
{
int i;
if (!mod_pin_mux)
return;
for (i = 0; mod_pin_mux[i].reg_offset != -1; i++)
MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset);
}
void enable_uart0_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
}
......@@ -161,6 +161,7 @@ dkb arm arm926ejs - Marvell pantheon
integratorap_cm946es arm arm946es integrator armltd - integratorap
integratorcp_cm946es arm arm946es integrator armltd - integratorcp
ca9x4_ct_vxp arm armv7 vexpress armltd
am335x_evm arm armv7 am335x ti am33xx
efikamx arm armv7 efikamx - mx5 efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/efikamx/imximage_mx.cfg
efikasb arm armv7 efikamx - mx5 efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/efikamx/imximage_sb.cfg
mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg
......
......@@ -37,7 +37,8 @@
void NS16550_init(NS16550_t com_port, int baud_divisor)
{
serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
#if defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)
#if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
defined(CONFIG_AM33XX)
serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/
#endif
serial_out(UART_LCR_BKSE | UART_LCRVAL, (ulong)&com_port->lcr);
......@@ -50,7 +51,9 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
serial_out(baud_divisor & 0xff, &com_port->dll);
serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm);
serial_out(UART_LCRVAL, &com_port->lcr);
#if defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)
#if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \
defined(CONFIG_AM33XX)
#if defined(CONFIG_APTIX)
/* /13 mode so Aptix 6MHz can hit 115200 */
serial_out(3, &com_port->mdr1);
......
/*
* am335x_evm.h
*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __CONFIG_AM335X_EVM_H
#define __CONFIG_AM335X_EVM_H
#define CONFIG_AM335X
#define CONFIG_CMD_MEMORY /* for mtest */
#undef CONFIG_GZIP
#undef CONFIG_ZLIB
#undef CONFIG_SYS_HUSH_PARSER
#undef CONFIG_CMD_NET
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#define CONFIG_SETUP_PLL
#define CONFIG_AM335X_CONFIG_DDR
#define CONFIG_ENV_SIZE 0x400
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 * 1024))
#define CONFIG_SYS_PROMPT "AM335X# "
#define CONFIG_SYS_NO_FLASH
#define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM
#define CONFIG_CMD_ASKENV
#define CONFIG_VERSION_VARIABLE
/* set to negative value for no autoboot */
#define CONFIG_BOOTDELAY 3
#define CONFIG_SYS_AUTOLOAD "no"
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=yes\0" \
"ramdisk_file=ramdisk.gz\0" \
/* Clock Defines */
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for
initial data */
#define CONFIG_CMD_ECHO
/* max number of command args */
#define CONFIG_SYS_MAXARGS 32
/* Console I/O Buffer Size */
#define CONFIG_SYS_CBSIZE 512
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/*
* memtest works on 8 MB in DRAM after skipping 32MB from
* start addr of ram disk
*/
#define CONFIG_SYS_MEMTEST_START (PHYS_DRAM_1 + (64 * 1024 * 1024))
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \
+ (8 * 1024 * 1024))
#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
#define CONFIG_SYS_HZ 1000 /* 1ms clock */
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
#define PHYS_DRAM_1_SIZE 0x10000000 /*(0x80000000 / 8) 256 MB */
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
GENERATED_GBL_DATA_SIZE)
/* Platform/Board specific defs */
#define CONFIG_SYS_CLK_FREQ 24000000
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK (48000000)
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
#define CONFIG_SYS_NS16550_COM4 0x481A6000 /* UART3 on IA BOard */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \
4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 }
/*
* select serial console configuration
*/
#define CONFIG_SERIAL1 1
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_SYS_TEXT_BASE 0x402f0400
/* Unsupported features */
#undef CONFIG_USE_IRQ