Commit 541c9be8 authored by Tom Rini's avatar Tom Rini
Browse files

Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze

parents 3f8085e9 58ed7f66
......@@ -580,6 +580,7 @@ config ARCH_ZYNQ
select SPL_OF_CONTROL if SPL
select DM
select DM_ETH
select DM_GPIO
select SPL_DM if SPL
select DM_MMC
select DM_SPI
......@@ -592,8 +593,6 @@ config ARCH_ZYNQMP
select ARM64
select DM
select OF_CONTROL
select DM_ETH
select DM_MMC
select DM_SERIAL
config TEGRA
......
......@@ -81,7 +81,12 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
zynq-zc770-xm012.dtb \
zynq-zc770-xm013.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-ep108.dtb
zynqmp-ep108.dtb \
zynqmp-zcu102.dtb \
zynqmp-zcu102-revB.dtb \
zynqmp-zc1751-xm015-dc1.dtb \
zynqmp-zc1751-xm016-dc2.dtb \
zynqmp-zc1751-xm019-dc5.dtb
dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-evm.dtb
dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb
dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
......
......@@ -96,8 +96,10 @@
gpio0: gpio@e000a000 {
compatible = "xlnx,zynq-gpio-1.0";
#gpio-cells = <2>;
#interrupt-cells = <2>;
clocks = <&clkc 42>;
gpio-controller;
interrupt-controller;
interrupt-parent = <&intc>;
interrupts = <0 20 4>;
reg = <0xe000a000 0x1000>;
......@@ -270,6 +272,13 @@
reg = <0x100 0x100>;
};
rstc: rstc@200 {
compatible = "xlnx,zynq-reset";
reg = <0x200 0x48>;
#reset-cells = <1>;
syscon = <&slcr>;
};
pinctrl0: pinctrl@700 {
compatible = "xlnx,pinctrl-zynq";
reg = <0x700 0x200>;
......@@ -297,7 +306,12 @@
devcfg: devcfg@f8007000 {
compatible = "xlnx,zynq-devcfg-1.0";
interrupt-parent = <&intc>;
interrupts = <0 8 4>;
reg = <0xf8007000 0x100>;
clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
syscon = <&slcr>;
};
global_timer: timer@f8f00200 {
......
/*
* Xilinx MicroZED board DTS
*
* Copyright (C) 2013 Xilinx, Inc.
* Copyright (C) 2013 - 2016 Xilinx, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
......@@ -15,12 +15,27 @@
aliases {
serial0 = &uart1;
spi0 = &qspi;
mmc0 = &sdhci0;
};
memory {
device_type = "memory";
reg = <0 0x40000000>;
};
chosen {
bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
usb_phy0: phy0 {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
};
&clkc {
ps-clk-frequency = <33333333>;
};
&qspi {
......@@ -32,3 +47,24 @@
u-boot,dm-pre-reloc;
status = "okay";
};
&gem0 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy>;
ethernet_phy: ethernet-phy@0 {
reg = <0>;
};
};
&sdhci0 {
u-boot,dm-pre-reloc;
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
usb-phy = <&usb_phy0>;
};
......@@ -27,7 +27,7 @@
};
chosen {
bootargs = "earlyprintk";
bootargs = "";
stdout-path = "serial0:115200n8";
};
......@@ -91,6 +91,8 @@
phy-handle = <&ethernet_phy>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem0_default>;
phy-reset-gpio = <&gpio0 11 0>;
phy-reset-active-low;
ethernet_phy: ethernet-phy@7 {
reg = <7>;
......@@ -128,6 +130,21 @@
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
adv7511: hdmi-tx@39 {
compatible = "adi,adv7511";
reg = <0x39>;
adi,input-depth = <8>;
adi,input-colorspace = "yuv422";
adi,input-clock = "1x";
adi,input-style = <3>;
adi,input-justification = "right";
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
......@@ -370,6 +387,11 @@
};
};
&qspi {
u-boot,dm-pre-reloc;
status = "okay";
};
&sdhci0 {
u-boot,dm-pre-reloc;
status = "okay";
......@@ -384,11 +406,6 @@
pinctrl-0 = <&pinctrl_uart1_default>;
};
&qspi {
u-boot,dm-pre-reloc;
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
......
......@@ -27,7 +27,7 @@
};
chosen {
bootargs = "earlyprintk";
bootargs = "";
stdout-path = "serial0:115200n8";
};
......@@ -84,6 +84,21 @@
};
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
adv7511: hdmi-tx@39 {
compatible = "adi,adv7511";
reg = <0x39>;
adi,input-depth = <8>;
adi,input-colorspace = "yuv422";
adi,input-clock = "1x";
adi,input-style = <3>;
adi,input-justification = "evenly";
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
......@@ -291,6 +306,11 @@
};
};
&qspi {
u-boot,dm-pre-reloc;
status = "okay";
};
&sdhci0 {
u-boot,dm-pre-reloc;
status = "okay";
......@@ -305,11 +325,6 @@
pinctrl-0 = <&pinctrl_uart1_default>;
};
&qspi {
u-boot,dm-pre-reloc;
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
......
......@@ -21,7 +21,7 @@
};
chosen {
bootargs = "root=/dev/ram rw earlyprintk";
bootargs = "";
stdout-path = "serial0:115200n8";
};
......@@ -36,27 +36,6 @@
};
};
&spi1 {
status = "okay";
num-cs = <4>;
is-decoded-cs = <0>;
flash@0 {
compatible = "sst25wf080";
reg = <1>;
spi-max-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <1>;
partition@test {
label = "spi-flash";
reg = <0x0 0x100000>;
};
};
};
&qspi {
status = "okay";
};
&can0 {
status = "okay";
};
......@@ -82,10 +61,31 @@
};
&qspi {
status = "okay";
};
&sdhci0 {
status = "okay";
};
&spi1 {
status = "okay";
num-cs = <4>;
is-decoded-cs = <0>;
flash@0 {
compatible = "sst25wf080";
reg = <1>;
spi-max-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <1>;
partition@test {
label = "spi-flash";
reg = <0x0 0x100000>;
};
};
};
&uart1 {
u-boot,dm-pre-reloc;
status = "okay";
......
......@@ -7,6 +7,7 @@
*/
/dts-v1/;
#include "zynq-7000.dtsi"
/ {
compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000";
model = "Xilinx Zynq";
......@@ -18,7 +19,7 @@
};
chosen {
bootargs = "root=/dev/ram rw earlyprintk";
bootargs = "";
stdout-path = "serial0:115200n8";
};
......
......@@ -20,7 +20,7 @@
};
chosen {
bootargs = "root=/dev/ram rw earlyprintk";
bootargs = "";
stdout-path = "serial0:115200n8";
};
......
......@@ -16,11 +16,12 @@
ethernet0 = &gem1;
i2c0 = &i2c1;
serial0 = &uart0;
spi0 = &spi0;
spi0 = &qspi;
spi1 = &spi0;
};
chosen {
bootargs = "root=/dev/ram rw earlyprintk";
bootargs = "";
stdout-path = "serial0:115200n8";
};
......@@ -58,6 +59,10 @@
};
};
&qspi {
status = "okay";
};
&spi0 {
status = "okay";
num-cs = <4>;
......
......@@ -26,7 +26,7 @@
};
chosen {
bootargs = "earlyprintk";
bootargs = "";
stdout-path = "serial0:115200n8";
};
......@@ -50,17 +50,17 @@
};
};
&sdhci0 {
&qspi {
u-boot,dm-pre-reloc;
status = "okay";
};
&uart1 {
&sdhci0 {
u-boot,dm-pre-reloc;
status = "okay";
};
&qspi {
&uart1 {
u-boot,dm-pre-reloc;
status = "okay";
};
......
......@@ -26,13 +26,13 @@
};
chosen {
bootargs = "earlyprintk";
bootargs = "";
stdout-path = "serial0:115200n8";
};
usb_phy0: phy0 {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
reset-gpios = <&gpio0 46 1>;
};
};
......@@ -51,17 +51,17 @@
};
};
&sdhci0 {
&qspi {
u-boot,dm-pre-reloc;
status = "okay";
};
&uart1 {
&sdhci0 {
u-boot,dm-pre-reloc;
status = "okay";
};
&qspi {
&uart1 {
u-boot,dm-pre-reloc;
status = "okay";
};
......
/*
* Clock specification for Xilinx ZynqMP
*
* (C) Copyright 2015, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
&amba {
clk100: clk100 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
clk125: clk125 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
clk200: clk200 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
};
clk250: clk250 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <250000000>;
};
clk300: clk300 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <300000000>;
};
clk600: clk600 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <600000000>;
};
dp_aclk: clock0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-accuracy = <100>;
};
dp_aud_clk: clock1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24576000>;
clock-accuracy = <100>;
};
dpdma_clk: dpdma_clk {
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <533000000>;
};
drm_clock: drm_clock {
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <262750000>;
clock-accuracy = <0x64>;
};
};
&can0 {
clocks = <&clk100 &clk100>;
};
&can1 {
clocks = <&clk100 &clk100>;
};
&fpd_dma_chan1 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan2 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan3 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan4 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan5 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan6 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan7 {
clocks = <&clk600>, <&clk100>;
};
&fpd_dma_chan8 {
clocks = <&clk600>, <&clk100>;
};
&nand0 {
clocks = <&clk100 &clk100>;
};
&gem0 {
clocks = <&clk125>, <&clk125>, <&clk125>;
};
&gem1 {
clocks = <&clk125>, <&clk125>, <&clk125>;
};
&gem2 {
clocks = <&clk125>, <&clk125>, <&clk125>;
};
&gem3 {
clocks = <&clk125>, <&clk125>, <&clk125>;
};
&gpio {
clocks = <&clk100>;
};
&i2c0 {
clocks = <&clk100>;
};
&i2c1 {
clocks = <&clk100>;
};
&qspi {
clocks = <&clk300 &clk300>;
};
&sata {
clocks = <&clk250>;
};
&sdhci0 {
clocks = <&clk200 &clk200>;
};
&sdhci1 {
clocks = <&clk200 &clk200>;
};
&spi0 {
clocks = <&clk200 &clk200>;
};
&spi1 {
clocks = <&clk200 &clk200>;
};
&uart0 {
clocks = <&clk100 &clk100>;
};
&uart1 {
clocks = <&clk100 &clk100>;
};
&usb0 {
clocks = <&clk250>, <&clk250>;
};
&usb1 {
clocks = <&clk250>, <&clk250>;
};
&xilinx_drm {
clocks = <&drm_clock>;
};
&xlnx_dp {
clocks = <&dp_aclk>, <&dp_aud_clk>;
};
&xlnx_dpdma {
clocks = <&dpdma_clk>;
};
&xlnx_dp_snd_codec0 {
clocks = <&dp_aud_clk>;
};