Commit 555da617 authored by Dave Liu's avatar Dave Liu Committed by Kim Phillips
Browse files

mpc83xx: Add the support of MPC8315E SoC



The MPC8315E SoC including e300c3 core and new IP blocks,
such as TDM, PCI Express and SATA controller.
Signed-off-by: default avatarDave Liu <daveliu@freescale.com>
parent 03051c3d
......@@ -153,6 +153,18 @@ int checkcpu(void)
case SPR_8313E_REV10:
puts("MPC8313E, ");
break;
case SPR_8315E_REV10:
puts("MPC8315E, ");
break;
case SPR_8315_REV10:
puts("MPC8315, ");
break;
case SPR_8314E_REV10:
puts("MPC8314E, ");
break;
case SPR_8314_REV10:
puts("MPC8314, ");
break;
case SPR_8379E_REV10:
puts("MPC8379E, ");
break;
......
......@@ -113,6 +113,9 @@ int get_clocks(void)
#if !defined(CONFIG_MPC832X)
u32 i2c2_clk;
#endif
#if defined(CONFIG_MPC8315)
u32 tdm_clk;
#endif
#if defined(CONFIG_MPC837X)
u32 sdhc_clk;
#endif
......@@ -132,6 +135,8 @@ int get_clocks(void)
#if defined(CONFIG_MPC837X)
u32 pciexp1_clk;
u32 pciexp2_clk;
#endif
#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
u32 sata_clk;
#endif
......@@ -197,7 +202,7 @@ int get_clocks(void)
}
#endif
#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC837X)
#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
case 0:
tsec2_clk = 0;
......@@ -215,7 +220,7 @@ int get_clocks(void)
/* unkown SCCR_TSEC2CM value */
return -4;
}
#elif defined(CONFIG_MPC831X)
#elif defined(CONFIG_MPC8313)
tsec2_clk = tsec1_clk;
if (!(sccr & SCCR_TSEC1ON))
......@@ -288,6 +293,25 @@ int get_clocks(void)
return -8;
}
#endif
#if defined(CONFIG_MPC8315)
switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
case 0:
tdm_clk = 0;
break;
case 1:
tdm_clk = csb_clk;
break;
case 2:
tdm_clk = csb_clk / 2;
break;
case 3:
tdm_clk = csb_clk / 3;
break;
default:
/* unkown SCCR_TDMCM value */
return -8;
}
#endif
#if defined(CONFIG_MPC834X)
i2c1_clk = tsec2_clk;
......@@ -342,7 +366,7 @@ int get_clocks(void)
}
#endif
#if defined(CONFIG_MPC837X)
#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
case 0:
sata_clk = 0;
......@@ -428,6 +452,9 @@ int get_clocks(void)
#if defined(CONFIG_MPC834X)
gd->usbmph_clk = usbmph_clk;
#endif
#if defined(CONFIG_MPC8315)
gd->tdm_clk = tdm_clk;
#endif
#if defined(CONFIG_MPC837X)
gd->sdhc_clk = sdhc_clk;
#endif
......@@ -450,6 +477,8 @@ int get_clocks(void)
#if defined(CONFIG_MPC837X)
gd->pciexp1_clk = pciexp1_clk;
gd->pciexp2_clk = pciexp2_clk;
#endif
#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
gd->sata_clk = sata_clk;
#endif
gd->pci_clk = pci_sync_in;
......@@ -488,6 +517,9 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
#if !defined(CONFIG_MPC832X)
printf(" I2C2: %4d MHz\n", gd->i2c2_clk / 1000000);
#endif
#if defined(CONFIG_MPC8315)
printf(" TDM: %4d MHz\n", gd->tdm_clk / 1000000);
#endif
#if defined(CONFIG_MPC837X)
printf(" SDHC: %4d MHz\n", gd->sdhc_clk / 1000000);
#endif
......@@ -502,6 +534,8 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
#if defined(CONFIG_MPC837X)
printf(" PCIEXP1: %4d MHz\n", gd->pciexp1_clk / 1000000);
printf(" PCIEXP2: %4d MHz\n", gd->pciexp2_clk / 1000000);
#endif
#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
printf(" SATA: %4d MHz\n", gd->sata_clk / 1000000);
#endif
return 0;
......
......@@ -63,6 +63,9 @@ typedef struct global_data {
#if defined (CONFIG_MPC834X)
u32 usbmph_clk;
#endif /* CONFIG_MPC834X */
#if defined(CONFIG_MPC815)
u32 tdm_clk;
#endif
#if defined(CONFIG_MPC837X)
u32 sdhc_clk;
#endif
......@@ -77,6 +80,8 @@ typedef struct global_data {
#if defined(CONFIG_MPC837X)
u32 pciexp1_clk;
u32 pciexp2_clk;
#endif
#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
u32 sata_clk;
#endif
#if defined(CONFIG_MPC8360)
......
......@@ -589,6 +589,20 @@ typedef struct rom83xx {
u8 mem[0x10000];
} rom83xx_t;
/*
* TDM
*/
typedef struct tdm83xx {
u8 fixme[0x200];
} tdm83xx_t;
/*
* TDM DMAC
*/
typedef struct tdmdmac83xx {
u8 fixme[0x2000];
} tdmdmac83xx_t;
#if defined(CONFIG_MPC834X)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
......@@ -626,7 +640,7 @@ typedef struct immap {
u8 res7[0xC0000];
} immap_t;
#elif defined(CONFIG_MPC831X)
#elif defined(CONFIG_MPC8313)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
......@@ -661,6 +675,51 @@ typedef struct immap {
u8 res7[0xC0000];
} immap_t;
#elif defined(CONFIG_MPC8315)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
rtclk83xx_t rtc; /* Real Time Clock Module Registers */
rtclk83xx_t pit; /* Periodic Interval Timer */
gtm83xx_t gtm[2]; /* Global Timers Module */
ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */
arbiter83xx_t arbiter; /* System Arbiter Registers */
reset83xx_t reset; /* Reset Module */
clk83xx_t clk; /* System Clock Module */
pmc83xx_t pmc; /* Power Management Control Module */
gpio83xx_t gpio[1]; /* General purpose I/O module */
u8 res0[0x1300];
ddr83xx_t ddr; /* DDR Memory Controller Memory */
fsl_i2c_t i2c[2]; /* I2C Controllers */
u8 res1[0x1300];
duart83xx_t duart[2]; /* DUART */
u8 res2[0x900];
lbus83xx_t lbus; /* Local Bus Controller Registers */
u8 res3[0x1000];
spi83xx_t spi; /* Serial Peripheral Interface */
dma83xx_t dma; /* DMA */
pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
u8 res4[0x80];
ios83xx_t ios; /* Sequencer */
pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */
u8 res5[0xa00];
pex83xx_t pciexp[2]; /* PCI Express Controller */
u8 res6[0xb000];
tdm83xx_t tdm; /* TDM Controller */
u8 res7[0x1e00];
sata83xx_t sata[2]; /* SATA Controller */
u8 res8[0x9000];
usb83xx_t usb[1]; /* USB DR Controller */
tsec83xx_t tsec[2];
u8 res9[0x6000];
tdmdmac83xx_t tdmdmac; /* TDM DMAC */
u8 res10[0x2000];
security83xx_t security;
u8 res11[0xA3000];
serdes83xx_t serdes[1]; /* SerDes Registers */
u8 res12[0x1CF00];
} immap_t;
#elif defined(CONFIG_MPC837X)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
......
......@@ -102,6 +102,10 @@
#define SPR_8313_REV10 0x80B10010
#define SPR_8311E_REV10 0x80B20010
#define SPR_8311_REV10 0x80B30010
#define SPR_8315E_REV10 0x80B40010
#define SPR_8315_REV10 0x80B50010
#define SPR_8314E_REV10 0x80B60010
#define SPR_8314_REV10 0x80B70010
#define SPR_8379E_REV10 0x80C20010
#define SPR_8379_REV10 0x80C30010
......@@ -220,8 +224,8 @@
#define SICRL_URT_CTPR 0x06000000
#define SICRL_IRQ_CTPR 0x00C00000
#elif defined(CONFIG_MPC831X)
/* SICRL bits - MPC831x specific */
#elif defined(CONFIG_MPC8313)
/* SICRL bits - MPC8313 specific */
#define SICRL_LBC 0x30000000
#define SICRL_UART 0x0C000000
#define SICRL_SPI_A 0x03000000
......@@ -232,7 +236,7 @@
#define SICRL_ETSEC1_A 0x0000000C
#define SICRL_ETSEC2_A 0x00000003
/* SICRH bits - MPC831x specific */
/* SICRH bits - MPC8313 specific */
#define SICRH_INTR_A 0x02000000
#define SICRH_INTR_B 0x00C00000
#define SICRH_IIC 0x00300000
......@@ -249,6 +253,41 @@
#define SICRH_TSOBI1 0x00000002
#define SICRH_TSOBI2 0x00000001
#elif defined(CONFIG_MPC8315)
/* SICRL bits - MPC8315 specific */
#define SICRL_DMA_CH0 0xc0000000
#define SICRL_DMA_SPI 0x30000000
#define SICRL_UART 0x0c000000
#define SICRL_IRQ4 0x02000000
#define SICRL_IRQ5 0x01800000
#define SICRL_IRQ6_7 0x00400000
#define SICRL_IIC1 0x00300000
#define SICRL_TDM 0x000c0000
#define SICRL_TDM_SHARED 0x00030000
#define SICRL_PCI_A 0x0000c000
#define SICRL_ELBC_A 0x00003000
#define SICRL_ETSEC1_A 0x000000c0
#define SICRL_ETSEC1_B 0x00000030
#define SICRL_ETSEC1_C 0x0000000c
#define SICRL_TSEXPOBI 0x00000001
/* SICRH bits - MPC8315 specific */
#define SICRH_GPIO_0 0xc0000000
#define SICRH_GPIO_1 0x30000000
#define SICRH_GPIO_2 0x0c000000
#define SICRH_GPIO_3 0x03000000
#define SICRH_GPIO_4 0x00c00000
#define SICRH_GPIO_5 0x00300000
#define SICRH_GPIO_6 0x000c0000
#define SICRH_GPIO_7 0x00030000
#define SICRH_GPIO_8 0x0000c000
#define SICRH_GPIO_9 0x00003000
#define SICRH_GPIO_10 0x00000c00
#define SICRH_GPIO_11 0x00000300
#define SICRH_ETSEC2_A 0x000000c0
#define SICRH_TSOBI1 0x00000002
#define SICRH_TSOBI2 0x00000001
#elif defined(CONFIG_MPC837X)
/* SICRL bits - MPC837x specific */
#define SICRL_USB_A 0xC0000000
......@@ -447,7 +486,7 @@
#define HRCWL_CE_TO_PLL_1X30 0x0000001E
#define HRCWL_CE_TO_PLL_1X31 0x0000001F
#elif defined(CONFIG_MPC837X)
#elif defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
#define HRCWL_SVCOD 0x30000000
#define HRCWL_SVCOD_SHIFT 28
#define HRCWL_SVCOD_DIV_4 0x00000000
......@@ -556,7 +595,7 @@
/* RSR - Reset Status Register
*/
#if defined(CONFIG_MPC837X)
#if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
#define RSR_RSTSRC 0xF0000000 /* Reset source */
#define RSR_RSTSRC_SHIFT 28
#else
......@@ -677,7 +716,7 @@
#define SCCR_USBCM_2 0x00A00000
#define SCCR_USBCM_3 0x00F00000
#elif defined(CONFIG_MPC831X)
#elif defined(CONFIG_MPC8313)
/* TSEC1 bits are for TSEC2 as well */
#define SCCR_TSEC1CM 0xc0000000
#define SCCR_TSEC1CM_SHIFT 30
......@@ -697,6 +736,48 @@
#define SCCR_USBDRCM_2 0x00200000
#define SCCR_USBDRCM_3 0x00300000
#elif defined(CONFIG_MPC8315)
/* SCCR bits - MPC8315 specific */
#define SCCR_TSEC1CM 0xc0000000
#define SCCR_TSEC1CM_SHIFT 30
#define SCCR_TSEC1CM_0 0x00000000
#define SCCR_TSEC1CM_1 0x40000000
#define SCCR_TSEC1CM_2 0x80000000
#define SCCR_TSEC1CM_3 0xC0000000
#define SCCR_TSEC2CM 0x30000000
#define SCCR_TSEC2CM_SHIFT 28
#define SCCR_TSEC2CM_0 0x00000000
#define SCCR_TSEC2CM_1 0x10000000
#define SCCR_TSEC2CM_2 0x20000000
#define SCCR_TSEC2CM_3 0x30000000
#define SCCR_USBDRCM 0x00300000
#define SCCR_USBDRCM_SHIFT 20
#define SCCR_USBDRCM_0 0x00000000
#define SCCR_USBDRCM_1 0x00100000
#define SCCR_USBDRCM_2 0x00200000
#define SCCR_USBDRCM_3 0x00300000
#define SCCR_PCIEXP1CM 0x00080000
#define SCCR_PCIEXP2CM 0x00040000
#define SCCR_SATA1CM 0x0000c000
#define SCCR_SATA1CM_SHIFT 14
#define SCCR_SATACM 0x0000f000
#define SCCR_SATACM_SHIFT 8
#define SCCR_SATACM_0 0x00000000
#define SCCR_SATACM_1 0x00005000
#define SCCR_SATACM_2 0x0000a000
#define SCCR_SATACM_3 0x0000f000
#define SCCR_TDMCM 0x000000c0
#define SCCR_TDMCM_SHIFT 6
#define SCCR_TDMCM_0 0x00000000
#define SCCR_TDMCM_1 0x00000040
#define SCCR_TDMCM_2 0x00000080
#define SCCR_TDMCM_3 0x000000c0
#elif defined(CONFIG_MPC837X)
/* SCCR bits - MPC837x specific */
#define SCCR_TSEC1CM 0xc0000000
......
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