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Librem5
uboot-imx
Commits
55e8250b
Commit
55e8250b
authored
Jun 08, 2014
by
Tom Rini
Browse files
Options
Browse Files
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Plain Diff
Merge branch 'master' of
git://git.denx.de/u-boot-arm
parents
3e1fa221
5ed28948
Changes
108
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108 changed files
with
1918 additions
and
763 deletions
+1918
-763
arch/arm/cpu/armv7/am33xx/board.c
arch/arm/cpu/armv7/am33xx/board.c
+17
-3
arch/arm/cpu/armv7/am33xx/clock.c
arch/arm/cpu/armv7/am33xx/clock.c
+11
-0
arch/arm/cpu/armv7/am33xx/clock_am43xx.c
arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+9
-0
arch/arm/cpu/armv7/am33xx/emif4.c
arch/arm/cpu/armv7/am33xx/emif4.c
+4
-0
arch/arm/cpu/armv7/exynos/clock.c
arch/arm/cpu/armv7/exynos/clock.c
+12
-33
arch/arm/cpu/armv7/exynos/lowlevel_init.c
arch/arm/cpu/armv7/exynos/lowlevel_init.c
+7
-1
arch/arm/cpu/armv7/exynos/pinmux.c
arch/arm/cpu/armv7/exynos/pinmux.c
+29
-6
arch/arm/cpu/armv7/exynos/power.c
arch/arm/cpu/armv7/exynos/power.c
+6
-0
arch/arm/cpu/armv7/keystone/init.c
arch/arm/cpu/armv7/keystone/init.c
+9
-0
arch/arm/cpu/armv7/omap3/mem.c
arch/arm/cpu/armv7/omap3/mem.c
+0
-12
arch/arm/dts/exynos4.dtsi
arch/arm/dts/exynos4.dtsi
+8
-0
arch/arm/dts/exynos4412-trats2.dts
arch/arm/dts/exynos4412-trats2.dts
+12
-0
arch/arm/dts/exynos5.dtsi
arch/arm/dts/exynos5.dtsi
+4
-4
arch/arm/dts/exynos5250-snow.dts
arch/arm/dts/exynos5250-snow.dts
+59
-2
arch/arm/dts/tegra124-jetson-tk1.dts
arch/arm/dts/tegra124-jetson-tk1.dts
+8
-1
arch/arm/dts/tegra124-venice2.dts
arch/arm/dts/tegra124-venice2.dts
+8
-1
arch/arm/dts/tegra30-beaver.dts
arch/arm/dts/tegra30-beaver.dts
+8
-1
arch/arm/include/asm/arch-am33xx/clock.h
arch/arm/include/asm/arch-am33xx/clock.h
+1
-0
arch/arm/include/asm/arch-am33xx/cpu.h
arch/arm/include/asm/arch-am33xx/cpu.h
+29
-6
arch/arm/include/asm/arch-exynos/clk.h
arch/arm/include/asm/arch-exynos/clk.h
+5
-0
arch/arm/include/asm/arch-exynos/power.h
arch/arm/include/asm/arch-exynos/power.h
+1
-0
arch/arm/include/asm/arch-keystone/hardware-k2hk.h
arch/arm/include/asm/arch-keystone/hardware-k2hk.h
+0
-2
arch/arm/include/asm/arch-keystone/hardware.h
arch/arm/include/asm/arch-keystone/hardware.h
+3
-0
arch/arm/include/asm/arch-omap3/mem.h
arch/arm/include/asm/arch-omap3/mem.h
+0
-8
board/BuR/tseries/board.c
board/BuR/tseries/board.c
+2
-0
board/BuR/tseries/mux.c
board/BuR/tseries/mux.c
+7
-2
board/compulab/cm_t35/cm_t35.c
board/compulab/cm_t35/cm_t35.c
+6
-6
board/samsung/common/board.c
board/samsung/common/board.c
+6
-7
board/samsung/goni/goni.c
board/samsung/goni/goni.c
+8
-0
board/samsung/smdk5250/Makefile
board/samsung/smdk5250/Makefile
+0
-4
board/samsung/smdk5250/exynos5-dt.c
board/samsung/smdk5250/exynos5-dt.c
+237
-1
board/samsung/smdk5250/smdk5250.c
board/samsung/smdk5250/smdk5250.c
+0
-363
board/samsung/smdk5420/smdk5420.c
board/samsung/smdk5420/smdk5420.c
+0
-3
board/ti/am43xx/Makefile
board/ti/am43xx/Makefile
+1
-1
board/ti/am43xx/board.c
board/ti/am43xx/board.c
+46
-9
boards.cfg
boards.cfg
+1
-0
doc/README.nand
doc/README.nand
+60
-0
doc/device-tree-bindings/exynos/dwmmc.txt
doc/device-tree-bindings/exynos/dwmmc.txt
+4
-4
doc/device-tree-bindings/power/tps65090.txt
doc/device-tree-bindings/power/tps65090.txt
+17
-0
doc/device-tree-bindings/regulator/tps65090.txt
doc/device-tree-bindings/regulator/tps65090.txt
+122
-0
drivers/mmc/dw_mmc.c
drivers/mmc/dw_mmc.c
+10
-2
drivers/mmc/exynos_dw_mmc.c
drivers/mmc/exynos_dw_mmc.c
+132
-73
drivers/mmc/mmc.c
drivers/mmc/mmc.c
+13
-3
drivers/mmc/s5p_sdhci.c
drivers/mmc/s5p_sdhci.c
+17
-25
drivers/mtd/nand/am335x_spl_bch.c
drivers/mtd/nand/am335x_spl_bch.c
+1
-1
drivers/mtd/nand/atmel_nand.c
drivers/mtd/nand/atmel_nand.c
+1
-1
drivers/mtd/nand/nand_base.c
drivers/mtd/nand/nand_base.c
+7
-4
drivers/mtd/nand/nand_spl_simple.c
drivers/mtd/nand/nand_spl_simple.c
+1
-1
drivers/mtd/nand/omap_elm.c
drivers/mtd/nand/omap_elm.c
+13
-15
drivers/mtd/nand/omap_gpmc.c
drivers/mtd/nand/omap_gpmc.c
+126
-67
drivers/power/battery/bat_trats.c
drivers/power/battery/bat_trats.c
+2
-2
drivers/power/battery/bat_trats2.c
drivers/power/battery/bat_trats2.c
+1
-1
drivers/power/mfd/pmic_max77693.c
drivers/power/mfd/pmic_max77693.c
+1
-1
drivers/power/pmic/Makefile
drivers/power/pmic/Makefile
+2
-0
drivers/power/pmic/pmic_max8997.c
drivers/power/pmic/pmic_max8997.c
+1
-1
drivers/power/pmic/pmic_tps65090.c
drivers/power/pmic/pmic_tps65090.c
+310
-0
drivers/power/pmic/pmic_tps65218.c
drivers/power/pmic/pmic_tps65218.c
+97
-0
drivers/power/power_fsl.c
drivers/power/power_fsl.c
+3
-3
drivers/power/power_i2c.c
drivers/power/power_i2c.c
+4
-0
drivers/spi/ti_qspi.c
drivers/spi/ti_qspi.c
+1
-0
include/configs/am3517_crane.h
include/configs/am3517_crane.h
+1
-0
include/configs/am43xx_evm.h
include/configs/am43xx_evm.h
+42
-3
include/configs/arndale.h
include/configs/arndale.h
+2
-2
include/configs/beaver.h
include/configs/beaver.h
+2
-0
include/configs/bur_am335x_common.h
include/configs/bur_am335x_common.h
+3
-1
include/configs/cm_t335.h
include/configs/cm_t335.h
+0
-1
include/configs/cm_t35.h
include/configs/cm_t35.h
+0
-1
include/configs/devkit8000.h
include/configs/devkit8000.h
+1
-0
include/configs/dig297.h
include/configs/dig297.h
+1
-0
include/configs/exynos4-dt.h
include/configs/exynos4-dt.h
+4
-0
include/configs/exynos5-dt.h
include/configs/exynos5-dt.h
+1
-0
include/configs/exynos5250-dt.h
include/configs/exynos5250-dt.h
+1
-1
include/configs/jetson-tk1.h
include/configs/jetson-tk1.h
+2
-0
include/configs/k2hk_evm.h
include/configs/k2hk_evm.h
+3
-1
include/configs/mx25pdk.h
include/configs/mx25pdk.h
+1
-1
include/configs/mx35pdk.h
include/configs/mx35pdk.h
+1
-1
include/configs/mx53evk.h
include/configs/mx53evk.h
+1
-1
include/configs/mx53loco.h
include/configs/mx53loco.h
+1
-1
include/configs/omap3_beagle.h
include/configs/omap3_beagle.h
+1
-0
include/configs/omap3_evm_common.h
include/configs/omap3_evm_common.h
+1
-1
include/configs/omap3_igep00x0.h
include/configs/omap3_igep00x0.h
+1
-0
include/configs/omap3_logic.h
include/configs/omap3_logic.h
+1
-0
include/configs/omap3_overo.h
include/configs/omap3_overo.h
+1
-0
include/configs/omap3_zoom1.h
include/configs/omap3_zoom1.h
+1
-0
include/configs/pengwyn.h
include/configs/pengwyn.h
+0
-1
include/configs/s5p_goni.h
include/configs/s5p_goni.h
+78
-35
include/configs/tam3517-common.h
include/configs/tam3517-common.h
+2
-0
include/configs/tao3530.h
include/configs/tao3530.h
+1
-1
include/configs/tegra-common-ums.h
include/configs/tegra-common-ums.h
+26
-0
include/configs/ti_am335x_common.h
include/configs/ti_am335x_common.h
+9
-0
include/configs/ti_armv7_common.h
include/configs/ti_armv7_common.h
+2
-1
include/configs/tseries.h
include/configs/tseries.h
+0
-1
include/configs/venice2.h
include/configs/venice2.h
+2
-0
include/configs/woodburn_common.h
include/configs/woodburn_common.h
+1
-1
include/dwmmc.h
include/dwmmc.h
+5
-0
include/fdtdec.h
include/fdtdec.h
+3
-1
include/initcall.h
include/initcall.h
+1
-1
include/linux/mtd/nand.h
include/linux/mtd/nand.h
+19
-0
include/linux/mtd/omap_elm.h
include/linux/mtd/omap_elm.h
+7
-4
include/linux/mtd/omap_gpmc.h
include/linux/mtd/omap_gpmc.h
+10
-1
include/mmc.h
include/mmc.h
+13
-12
include/power/max77693_pmic.h
include/power/max77693_pmic.h
+0
-2
include/power/max8997_pmic.h
include/power/max8997_pmic.h
+0
-1
include/power/pmic.h
include/power/pmic.h
+5
-0
include/power/tps65090_pmic.h
include/power/tps65090_pmic.h
+73
-0
include/power/tps65218.h
include/power/tps65218.h
+63
-0
lib/fdtdec.c
lib/fdtdec.c
+3
-1
lib/initcall.c
lib/initcall.c
+12
-5
No files found.
arch/arm/cpu/armv7/am33xx/board.c
View file @
55e8250b
...
...
@@ -143,6 +143,19 @@ int arch_misc_init(void)
}
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
/*
* In the case of non-SPL based booting we'll want to call these
* functions a tiny bit later as it will require gd to be set and cleared
* and that's not true in s_init in this case so we cannot do it there.
*/
int
board_early_init_f
(
void
)
{
prcm_init
();
set_mux_conf_regs
();
return
0
;
}
/*
* This function is the place to do per-board things such as ramp up the
* MPU clock frequency.
...
...
@@ -224,7 +237,7 @@ void s_init(void)
set_uart_mux_conf
();
setup_clocks_for_console
();
uart_soft_reset
();
#if
def CONFIG_NOR_BOOT
#if
defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT)
gd
->
baudrate
=
CONFIG_BAUDRATE
;
serial_init
();
gd
->
have_console
=
1
;
...
...
@@ -232,13 +245,14 @@ void s_init(void)
gd
=
&
gdata
;
preloader_console_init
();
#endif
prcm_init
();
set_mux_conf_regs
();
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
/* Enable RTC32K clock */
rtc32k_enable
();
#endif
#ifdef CONFIG_SPL_BUILD
board_early_init_f
();
sdram_init
();
#endif
}
#endif
...
...
arch/arm/cpu/armv7/am33xx/clock.c
View file @
55e8250b
...
...
@@ -170,8 +170,19 @@ void do_enable_clocks(u32 *const *clk_domains,
};
}
/*
* Before scaling up the clocks we need to have the PMIC scale up the
* voltages first. This will be dependent on which PMIC is in use
* and in some cases we may not be scaling things up at all and thus not
* need to do anything here.
*/
__weak
void
scale_vcores
(
void
)
{
}
void
prcm_init
()
{
enable_basic_clocks
();
scale_vcores
();
setup_dplls
();
}
arch/arm/cpu/armv7/am33xx/clock_am43xx.c
View file @
55e8250b
...
...
@@ -53,6 +53,8 @@ const struct dpll_regs dpll_ddr_regs = {
void
setup_clocks_for_console
(
void
)
{
u32
clkctrl
,
idlest
=
MODULE_CLKCTRL_IDLEST_DISABLED
;
/* Do not add any spl_debug prints in this function */
clrsetbits_le32
(
&
cmwkup
->
wkclkstctrl
,
CD_CLKCTRL_CLKTRCTRL_MASK
,
CD_CLKCTRL_CLKTRCTRL_SW_WKUP
<<
...
...
@@ -63,6 +65,13 @@ void setup_clocks_for_console(void)
MODULE_CLKCTRL_MODULEMODE_MASK
,
MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN
<<
MODULE_CLKCTRL_MODULEMODE_SHIFT
);
while
((
idlest
==
MODULE_CLKCTRL_IDLEST_DISABLED
)
||
(
idlest
==
MODULE_CLKCTRL_IDLEST_TRANSITIONING
))
{
clkctrl
=
readl
(
&
cmwkup
->
wkup_uart0ctrl
);
idlest
=
(
clkctrl
&
MODULE_CLKCTRL_IDLEST_MASK
)
>>
MODULE_CLKCTRL_IDLEST_SHIFT
;
}
}
void
enable_basic_clocks
(
void
)
...
...
arch/arm/cpu/armv7/am33xx/emif4.c
View file @
55e8250b
...
...
@@ -21,6 +21,10 @@ DECLARE_GLOBAL_DATA_PTR;
int
dram_init
(
void
)
{
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
sdram_init
();
#endif
/* dram_init must store complete ramsize in gd->ram_size */
gd
->
ram_size
=
get_ram_size
(
(
void
*
)
CONFIG_SYS_SDRAM_BASE
,
...
...
arch/arm/cpu/armv7/exynos/clock.c
View file @
55e8250b
...
...
@@ -869,7 +869,7 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
{
struct
exynos4_clock
*
clk
=
(
struct
exynos4_clock
*
)
samsung_get_base_clock
();
unsigned
int
addr
;
unsigned
int
addr
,
clear_bit
,
set_bit
;
/*
* CLK_DIV_FSYS1
...
...
@@ -877,44 +877,26 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
* CLK_DIV_FSYS2
* MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
* CLK_DIV_FSYS3
* MMC4_
PRE_RATIO [15:8
]
* MMC4_
RATIO [3:0
]
*/
if
(
dev_index
<
2
)
{
addr
=
(
unsigned
int
)
&
clk
->
div_fsys1
;
}
else
if
(
dev_index
==
4
)
{
clear_bit
=
MASK_PRE_RATIO
(
dev_index
);
set_bit
=
SET_PRE_RATIO
(
dev_index
,
div
);
}
else
if
(
dev_index
==
4
)
{
addr
=
(
unsigned
int
)
&
clk
->
div_fsys3
;
dev_index
-=
4
;
/* MMC4 is controlled with the MMC4_RATIO value */
clear_bit
=
MASK_RATIO
(
dev_index
);
set_bit
=
SET_RATIO
(
dev_index
,
div
);
}
else
{
addr
=
(
unsigned
int
)
&
clk
->
div_fsys2
;
dev_index
-=
2
;
clear_bit
=
MASK_PRE_RATIO
(
dev_index
);
set_bit
=
SET_PRE_RATIO
(
dev_index
,
div
);
}
clrsetbits_le32
(
addr
,
0xff
<<
((
dev_index
<<
4
)
+
8
),
(
div
&
0xff
)
<<
((
dev_index
<<
4
)
+
8
));
}
/* exynos4x12: set the mmc clock */
static
void
exynos4x12_set_mmc_clk
(
int
dev_index
,
unsigned
int
div
)
{
struct
exynos4x12_clock
*
clk
=
(
struct
exynos4x12_clock
*
)
samsung_get_base_clock
();
unsigned
int
addr
;
/*
* CLK_DIV_FSYS1
* MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
* CLK_DIV_FSYS2
* MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
*/
if
(
dev_index
<
2
)
{
addr
=
(
unsigned
int
)
&
clk
->
div_fsys1
;
}
else
{
addr
=
(
unsigned
int
)
&
clk
->
div_fsys2
;
dev_index
-=
2
;
}
clrsetbits_le32
(
addr
,
0xff
<<
((
dev_index
<<
4
)
+
8
),
(
div
&
0xff
)
<<
((
dev_index
<<
4
)
+
8
));
clrsetbits_le32
(
addr
,
clear_bit
,
set_bit
);
}
/* exynos5: set the mmc clock */
...
...
@@ -1612,10 +1594,7 @@ void set_mmc_clk(int dev_index, unsigned int div)
else
exynos5_set_mmc_clk
(
dev_index
,
div
);
}
else
{
if
(
proid_is_exynos4412
())
exynos4x12_set_mmc_clk
(
dev_index
,
div
);
else
exynos4_set_mmc_clk
(
dev_index
,
div
);
exynos4_set_mmc_clk
(
dev_index
,
div
);
}
}
...
...
arch/arm/cpu/armv7/exynos/lowlevel_init.c
View file @
55e8250b
...
...
@@ -39,6 +39,7 @@ enum {
DO_CLOCKS
=
1
<<
1
,
DO_MEM_RESET
=
1
<<
2
,
DO_UART
=
1
<<
3
,
DO_POWER
=
1
<<
4
,
};
int
do_lowlevel_init
(
void
)
...
...
@@ -48,6 +49,8 @@ int do_lowlevel_init(void)
arch_cpu_init
();
set_ps_hold_ctrl
();
reset_status
=
get_reset_status
();
switch
(
reset_status
)
{
...
...
@@ -60,9 +63,12 @@ int do_lowlevel_init(void)
break
;
default:
/* This is a normal boot (not a wake from sleep) */
actions
=
DO_CLOCKS
|
DO_MEM_RESET
;
actions
=
DO_CLOCKS
|
DO_MEM_RESET
|
DO_POWER
;
}
if
(
actions
&
DO_POWER
)
set_ps_hold_ctrl
();
if
(
actions
&
DO_CLOCKS
)
{
system_clock_init
();
mem_ctrl_init
(
actions
&
DO_MEM_RESET
);
...
...
arch/arm/cpu/armv7/exynos/pinmux.c
View file @
55e8250b
...
...
@@ -573,15 +573,26 @@ static void exynos4_i2c_config(int peripheral, int flags)
static
int
exynos4_mmc_config
(
int
peripheral
,
int
flags
)
{
int
i
,
start
=
0
,
start_ext
=
0
;
unsigned
int
func
,
ext_func
;
switch
(
peripheral
)
{
case
PERIPH_ID_SDMMC0
:
start
=
EXYNOS4_GPIO_K00
;
start_ext
=
EXYNOS4_GPIO_K13
;
func
=
S5P_GPIO_FUNC
(
0x2
);
ext_func
=
S5P_GPIO_FUNC
(
0x3
);
break
;
case
PERIPH_ID_SDMMC2
:
start
=
EXYNOS4_GPIO_K20
;
start_ext
=
EXYNOS4_GPIO_K33
;
func
=
S5P_GPIO_FUNC
(
0x2
);
ext_func
=
S5P_GPIO_FUNC
(
0x3
);
break
;
case
PERIPH_ID_SDMMC4
:
start
=
EXYNOS4_GPIO_K00
;
start_ext
=
EXYNOS4_GPIO_K13
;
func
=
S5P_GPIO_FUNC
(
0x3
);
ext_func
=
S5P_GPIO_FUNC
(
0x4
);
break
;
default:
return
-
1
;
...
...
@@ -589,13 +600,14 @@ static int exynos4_mmc_config(int peripheral, int flags)
for
(
i
=
start
;
i
<
(
start
+
7
);
i
++
)
{
if
(
i
==
(
start
+
2
))
continue
;
gpio_cfg_pin
(
i
,
S5P_GPIO_FUNC
(
0x2
)
);
gpio_cfg_pin
(
i
,
func
);
gpio_set_pull
(
i
,
S5P_GPIO_PULL_NONE
);
gpio_set_drv
(
i
,
S5P_GPIO_DRV_4X
);
}
/* SDMMC2 do not use 8bit mode at exynos4 */
if
(
flags
&
PINMUX_FLAG_8BIT_MODE
)
{
for
(
i
=
start_ext
;
i
<
(
start_ext
+
4
);
i
++
)
{
gpio_cfg_pin
(
i
,
S5P_GPIO_FUNC
(
0x3
)
);
gpio_cfg_pin
(
i
,
ext_func
);
gpio_set_pull
(
i
,
S5P_GPIO_PULL_NONE
);
gpio_set_drv
(
i
,
S5P_GPIO_DRV_4X
);
}
...
...
@@ -676,15 +688,26 @@ static void exynos4x12_i2c_config(int peripheral, int flags)
static
int
exynos4x12_mmc_config
(
int
peripheral
,
int
flags
)
{
int
i
,
start
=
0
,
start_ext
=
0
;
unsigned
int
func
,
ext_func
;
switch
(
peripheral
)
{
case
PERIPH_ID_SDMMC0
:
start
=
EXYNOS4X12_GPIO_K00
;
start_ext
=
EXYNOS4X12_GPIO_K13
;
func
=
S5P_GPIO_FUNC
(
0x2
);
ext_func
=
S5P_GPIO_FUNC
(
0x3
);
break
;
case
PERIPH_ID_SDMMC2
:
start
=
EXYNOS4X12_GPIO_K20
;
start_ext
=
EXYNOS4X12_GPIO_K33
;
func
=
S5P_GPIO_FUNC
(
0x2
);
ext_func
=
S5P_GPIO_FUNC
(
0x3
);
break
;
case
PERIPH_ID_SDMMC4
:
start
=
EXYNOS4_GPIO_K00
;
start_ext
=
EXYNOS4_GPIO_K13
;
func
=
S5P_GPIO_FUNC
(
0x3
);
ext_func
=
S5P_GPIO_FUNC
(
0x4
);
break
;
default:
return
-
1
;
...
...
@@ -692,13 +715,13 @@ static int exynos4x12_mmc_config(int peripheral, int flags)
for
(
i
=
start
;
i
<
(
start
+
7
);
i
++
)
{
if
(
i
==
(
start
+
2
))
continue
;
gpio_cfg_pin
(
i
,
S5P_GPIO_FUNC
(
0x2
)
);
gpio_cfg_pin
(
i
,
func
);
gpio_set_pull
(
i
,
S5P_GPIO_PULL_NONE
);
gpio_set_drv
(
i
,
S5P_GPIO_DRV_4X
);
}
if
(
flags
&
PINMUX_FLAG_8BIT_MODE
)
{
for
(
i
=
start_ext
;
i
<
(
start_ext
+
4
);
i
++
)
{
gpio_cfg_pin
(
i
,
S5P_GPIO_FUNC
(
0x3
)
);
gpio_cfg_pin
(
i
,
ext_func
);
gpio_set_pull
(
i
,
S5P_GPIO_PULL_NONE
);
gpio_set_drv
(
i
,
S5P_GPIO_DRV_4X
);
}
...
...
@@ -759,10 +782,10 @@ static int exynos4_pinmux_config(int peripheral, int flags)
break
;
case
PERIPH_ID_SDMMC0
:
case
PERIPH_ID_SDMMC2
:
case
PERIPH_ID_SDMMC4
:
return
exynos4_mmc_config
(
peripheral
,
flags
);
case
PERIPH_ID_SDMMC1
:
case
PERIPH_ID_SDMMC3
:
case
PERIPH_ID_SDMMC4
:
debug
(
"SDMMC device %d not implemented
\n
"
,
peripheral
);
return
-
1
;
default:
...
...
@@ -794,10 +817,10 @@ static int exynos4x12_pinmux_config(int peripheral, int flags)
break
;
case
PERIPH_ID_SDMMC0
:
case
PERIPH_ID_SDMMC2
:
case
PERIPH_ID_SDMMC4
:
return
exynos4x12_mmc_config
(
peripheral
,
flags
);
case
PERIPH_ID_SDMMC1
:
case
PERIPH_ID_SDMMC3
:
case
PERIPH_ID_SDMMC4
:
debug
(
"SDMMC device %d not implemented
\n
"
,
peripheral
);
return
-
1
;
default:
...
...
arch/arm/cpu/armv7/exynos/power.c
View file @
55e8250b
...
...
@@ -112,6 +112,12 @@ static void exynos5_set_ps_hold_ctrl(void)
EXYNOS_PS_HOLD_CONTROL_DATA_HIGH
);
}
/*
* Set ps_hold data driving value high
* This enables the machine to stay powered on
* after the initial power-on condition goes away
* (e.g. power button).
*/
void
set_ps_hold_ctrl
(
void
)
{
if
(
cpu_is_exynos5
())
...
...
arch/arm/cpu/armv7/keystone/init.c
View file @
55e8250b
...
...
@@ -8,6 +8,7 @@
*/
#include <common.h>
#include <ns16550.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
...
...
@@ -30,6 +31,14 @@ int arch_cpu_init(void)
share_all_segments
(
11
);
/* PCIE */
#endif
/*
* just initialise the COM2 port so that TI specific
* UART register PWREMU_MGMT is initialized. Linux UART
* driver doesn't handle this.
*/
NS16550_init
((
NS16550_t
)(
CONFIG_SYS_NS16550_COM2
),
CONFIG_SYS_NS16550_CLK
/
16
/
CONFIG_BAUDRATE
);
return
0
;
}
...
...
arch/arm/cpu/armv7/omap3/mem.c
View file @
55e8250b
...
...
@@ -21,17 +21,6 @@
struct
gpmc
*
gpmc_cfg
;
#if defined(CONFIG_CMD_NAND)
#if defined(GPMC_NAND_ECC_SP_x8_LAYOUT) || defined(GPMC_NAND_ECC_LP_x8_LAYOUT)
static
const
u32
gpmc_m_nand
[
GPMC_MAX_REG
]
=
{
SMNAND_GPMC_CONFIG1
,
SMNAND_GPMC_CONFIG2
,
SMNAND_GPMC_CONFIG3
,
SMNAND_GPMC_CONFIG4
,
SMNAND_GPMC_CONFIG5
,
SMNAND_GPMC_CONFIG6
,
0
,
};
#else
static
const
u32
gpmc_m_nand
[
GPMC_MAX_REG
]
=
{
M_NAND_GPMC_CONFIG1
,
M_NAND_GPMC_CONFIG2
,
...
...
@@ -40,7 +29,6 @@ static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
M_NAND_GPMC_CONFIG5
,
M_NAND_GPMC_CONFIG6
,
0
};
#endif
#endif
/* CONFIG_CMD_NAND */
#if defined(CONFIG_CMD_ONENAND)
...
...
arch/arm/dts/exynos4.dtsi
View file @
55e8250b
...
...
@@ -128,6 +128,14 @@
interrupts = <0 78 0>;
};
dwmmc@12550000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos-dwmmc";
reg = <0x12550000 0x1000>;
interrupts = <0 131 0>;
};
gpio: gpio {
gpio-controller;
#gpio-cells = <2>;
...
...
arch/arm/dts/exynos4412-trats2.dts
View file @
55e8250b
...
...
@@ -31,6 +31,7 @@
console = "/serial@13820000";
mmc0 = "sdhci@12510000";
mmc2 = "sdhci@12530000";
mmc4 = "dwmmc@12550000";
};
i2c@138d0000 {
...
...
@@ -416,6 +417,7 @@
samsung,bus-width = <8>;
samsung,timing = <1 3 3>;
pwr-gpios = <&gpio 0xB2 0>;
status = "disabled";
};
sdhci@12520000 {
...
...
@@ -431,4 +433,14 @@
sdhci@12540000 {
status = "disabled";
};
dwmmc@12550000 {
samsung,bus-width = <8>;
samsung,timing = <2 1 0>;
pwr-gpios = <&gpio 0xB2 0>;
fifoth_val = <0x203f0040>;
bus_hz = <400000000>;
div = <0x3>;
index = <4>;
};
};
arch/arm/dts/exynos5.dtsi
View file @
55e8250b
...
...
@@ -136,7 +136,7 @@
mmc@12200000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos
5250
-dwmmc";
compatible = "samsung,exynos-dwmmc";
reg = <0x12200000 0x1000>;
interrupts = <0 75 0>;
};
...
...
@@ -144,7 +144,7 @@
mmc@12210000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos
5250
-dwmmc";
compatible = "samsung,exynos-dwmmc";
reg = <0x12210000 0x1000>;
interrupts = <0 76 0>;
};
...
...
@@ -152,7 +152,7 @@
mmc@12220000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos
5250
-dwmmc";
compatible = "samsung,exynos-dwmmc";
reg = <0x12220000 0x1000>;
interrupts = <0 77 0>;
};
...
...
@@ -160,7 +160,7 @@
mmc@12230000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,exynos
5250
-dwmmc";
compatible = "samsung,exynos-dwmmc";
reg = <0x12230000 0x1000>;
interrupts = <0 78 0>;
};
...
...
arch/arm/dts/exynos5250-snow.dts
View file @
55e8250b
...
...
@@ -44,7 +44,7 @@
reg
=
<
0x1e
>;
compatible
=
"google,cros-ec"
;
i2c
-
max
-
frequency
=
<
100000
>;
ec
-
interrupt
=
<&
gpio
7
82
1
>;
ec
-
interrupt
=
<&
gpio
1
82
1
>;
};
power
-
regulator
@
48
{
...
...
@@ -60,7 +60,7 @@
reg
=
<
0
>;
compatible
=
"google,cros-ec"
;
spi
-
max
-
frequency
=
<
5000000
>;
ec
-
interrupt
=
<&
gpio
7
82
1
>;
ec
-
interrupt
=
<&
gpio
1
82
1
>;
optimise
-
flash
-
write
;
status
=
"disabled"
;
};
...
...
@@ -80,6 +80,19 @@
reg
=
<
0x22
>;
compatible
=
"maxim,max98095-codec"
;
};
ptn3460
-
bridge
@
20
{
compatible
=
"nxp,ptn3460"
;
reg
=
<
0x20
>;
/*
*
TODO
(
sjg
@
chromium
.
org
):
Use
GPIOs
here
*
powerdown
-
gpio
=
<&
gpy2
5
0
>;
*
reset
-
gpio
=
<&
gpx1
5
0
>;
*
edid
-
emulation
=
<
5
>;
*
pinctrl
-
names
=
"default"
;
*
pinctrl
-
0
=
<&
ptn3460_gpios
>;
*/
};
};
i2c
@
12
c60000
{
...
...
@@ -184,4 +197,48 @@
/* UP LEFT */
0x070b0067 0x070c0069>;
};
fimd@14400000 {
samsung,vl-freq = <60>;
samsung,vl-col = <1366>;
samsung,vl-row = <768>;
samsung,vl-width = <1366>;
samsung,vl-height = <768>;
samsung,vl-clkp;
samsung,vl-dp;
samsung,vl-hsp;
samsung,vl-vsp;
samsung,vl-bpix = <4>;
samsung,vl-hspw = <32>;
samsung,vl-hbpd = <80>;
samsung,vl-hfpd = <48>;
samsung,vl-vspw = <5>;
samsung,vl-vbpd = <14>;
samsung,vl-vfpd = <3>;
samsung,vl-cmd-allow-len = <0xf>;
samsung,winid = <0>;
samsung,interface-mode = <1>;
samsung,dp-enabled = <1>;
samsung,dual-lcd-enabled = <0>;
};
dp@145b0000 {
samsung,lt-status = <0>;
samsung,master-mode = <0>;
samsung,bist-mode = <0>;
samsung,bist-pattern = <0>;
samsung,h-sync-polarity = <0>;
samsung,v-sync-polarity = <0>;
samsung,interlaced = <0>;
samsung,color-space = <0>;
samsung,dynamic-range = <0>;
samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
};
};
arch/arm/dts/tegra124-jetson-tk1.dts
View file @
55e8250b
...
...
@@ -17,7 +17,8 @@
sdhci1
=
"/sdhci@700b0400"
;
spi0
=
"/spi@7000d400"
;
spi1
=
"/spi@7000da00"
;
usb0
=
"/usb@7d008000"
;
usb0
=
"/usb@7d000000"
;
usb1
=
"/usb@7d008000"
;
};
memory
{
...
...
@@ -77,6 +78,12 @@
bus
-
width
=
<
8
>;
};
usb
@
7
d000000
{
status
=
"okay"
;
dr_mode
=
"otg"
;
nvidia
,
vbus
-
gpio
=
<&
gpio
108
0
>;
/*
gpio
PN4
,
USB_VBUS_EN0
*/
};
usb
@
7
d008000
{
status
=
"okay"
;
nvidia
,
vbus
-
gpio
=
<&
gpio
109
0
>;
/*
gpio
PN5
,
USB_VBUS_EN1
*/
...
...
arch/arm/dts/tegra124-venice2.dts
View file @
55e8250b
...
...
@@ -17,7 +17,8 @@
sdhci1
=
"/sdhci@700b0400"
;
spi0
=
"/spi@7000d400"
;
spi1
=
"/spi@7000da00"
;
usb0
=
"/usb@7d008000"
;
usb0
=
"/usb@7d000000"
;
usb1
=
"/usb@7d008000"
;
};
memory
{
...
...
@@ -77,6 +78,12 @@
bus
-
width
=
<
8
>;
};
usb
@
7
d000000
{
status
=
"okay"
;
dr_mode
=
"otg"
;
nvidia
,
vbus
-
gpio
=
<&
gpio
108
0
>;
/*
gpio
PN4
,
USB_VBUS_EN0
*/
};
usb
@
7
d008000
{
status
=
"okay"
;
nvidia
,
vbus
-
gpio
=
<&
gpio
109
0
>;
/*
gpio
PN5
,
USB_VBUS_EN1
*/
...
...
arch/arm/dts/tegra30-beaver.dts
View file @
55e8250b
...
...
@@ -14,7 +14,8 @@
i2c4
=
"/i2c@7000c700"
;
sdhci0
=
"/sdhci@78000600"
;
sdhci1
=
"/sdhci@78000000"
;
usb0
=
"/usb@7d008000"
;
usb0
=
"/usb@7d000000"
;
usb1
=
"/usb@7d008000"
;
};
memory
{
...
...
@@ -70,6 +71,12 @@
bus
-
width
=
<
8
>;
};
usb
@
7
d000000
{
status
=
"okay"
;
dr_mode
=
"otg"
;
nvidia
,
vbus
-
gpio
=
<&
gpio
238
0
>;
/*
gpio
DD6
,
PEX_L1_CLKREQ
*/
};
usb
@
7
d008000
{
nvidia
,
vbus
-
gpio
=
<&
gpio
236
0
>;
/*
PDD4
*/
status
=
"okay"
;
...
...
arch/arm/include/asm/arch-am33xx/clock.h
View file @
55e8250b
...
...
@@ -107,6 +107,7 @@ const struct dpll_params *get_dpll_mpu_params(void);
const
struct
dpll_params
*
get_dpll_core_params
(
void
);
const
struct
dpll_params
*
get_dpll_per_params
(
void
);
const
struct
dpll_params
*
get_dpll_ddr_params
(
void
);
void
scale_vcores
(
void
);
void
do_setup_dpll
(
const
struct
dpll_regs
*
,
const
struct
dpll_params
*
);
void
prcm_init
(
void
);
void
enable_basic_clocks
(
void
);
...
...
arch/arm/include/asm/arch-am33xx/cpu.h
View file @
55e8250b
...
...
@@ -26,7 +26,17 @@
#define TCLR_PRE BIT(5)
/* Pre-scaler enable */
#define TCLR_PTV_SHIFT (2)
/* Pre-scaler shift value */
#define TCLR_PRE_DISABLE CL_BIT(5)
/* Pre-scalar disable */
#define TCLR_CE BIT(6)
/* compare mode enable */
#define TCLR_SCPWM BIT(7)
/* pwm outpin behaviour */
#define TCLR_TCM BIT(8)
/* edge detection of input pin*/
#define TCLR_TRG_SHIFT (10)
/* trigmode on pwm outpin */
#define TCLR_PT BIT(12)
/* pulse/toggle mode of outpin*/
#define TCLR_CAPTMODE BIT(13)
/* capture mode */
#define TCLR_GPOCFG BIT(14)
/* 0=output,1=input */
#define TCFG_RESET BIT(0)
/* software reset */
#define TCFG_EMUFREE BIT(1)
/* behaviour of tmr on debug */
#define TCFG_IDLEMOD_SHIFT (2)
/* power management */
/* device type */
#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
#define TST_DEVICE 0x0
...
...
@@ -87,7 +97,8 @@ struct cm_wkuppll {
unsigned
int
wkctrlclkctrl
;
/* offset 0x04 */
unsigned
int
wkgpio0clkctrl
;
/* offset 0x08 */
unsigned
int
wkl4wkclkctrl
;
/* offset 0x0c */
unsigned
int
resv2
[
4
];
unsigned
int
timer0clkctrl
;
/* offset 0x10 */
unsigned
int
resv2
[
3
];
unsigned
int
idlestdpllmpu
;
/* offset 0x20 */
unsigned
int
resv3
[
2
];
unsigned
int
clkseldpllmpu
;
/* offset 0x2c */
...
...
@@ -121,7 +132,9 @@ struct cm_wkuppll {
unsigned
int
wkup_uart0ctrl
;
/* offset 0xB4 */
unsigned
int
wkup_i2c0ctrl
;
/* offset 0xB8 */
unsigned
int
wkup_adctscctrl
;
/* offset 0xBC */
unsigned
int
resv12
[
6
];
unsigned
int
resv12
;
unsigned
int
timer1clkctrl
;
/* offset 0xC4 */
unsigned
int
resv13
[
4
];
unsigned
int
divm6dpllcore
;
/* offset 0xD8 */
};
...
...
@@ -178,7 +191,9 @@ struct cm_perpll {
unsigned
int
epwmss2clkctrl
;
/* offset 0xD8 */
unsigned
int
l3instrclkctrl
;
/* offset 0xDC */
unsigned
int
l3clkctrl
;
/* Offset 0xE0 */
unsigned
int
resv8
[
4
];
unsigned
int
resv8
[
2
];
unsigned
int
timer5clkctrl
;
/* offset 0xEC */
unsigned
int
timer6clkctrl
;
/* offset 0xF0 */
unsigned
int
mmc1clkctrl
;
/* offset 0xF4 */
unsigned
int
mmc2clkctrl
;
/* offset 0xF8 */
unsigned
int
resv9
[
8
];
...
...
@@ -191,9 +206,17 @@ struct cm_perpll {
/* Encapsulating Display pll registers */
struct
cm_dpll
{
unsigned
int
resv1
[
2
];
unsigned
int
resv1
;
unsigned
int
clktimer7clk
;
/* offset 0x04 */
unsigned
int
clktimer2clk
;
/* offset 0x08 */
unsigned
int
resv2
[
10
];
unsigned
int
clktimer3clk
;
/* offset 0x0C */
unsigned
int
clktimer4clk
;
/* offset 0x10 */
unsigned
int
resv2
;
unsigned
int
clktimer5clk
;
/* offset 0x18 */
unsigned
int
clktimer6clk
;
/* offset 0x1C */
unsigned
int
resv3
[
2
];
unsigned
int
clktimer1clk
;
/* offset 0x28 */