Commit 56b50286 authored by Tom Rini's avatar Tom Rini
Browse files

Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx

parents 5b9c79a8 28437154
......@@ -18,6 +18,12 @@
#define REFLECTION_TESTPATTERN 0xdede
#define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0xffff)
#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
#define REFLECTION_TESTREG reflection_low
#else
#define REFLECTION_TESTREG reflection_high
#endif
DECLARE_GLOBAL_DATA_PTR;
int get_fpga_state(unsigned dev)
......@@ -90,23 +96,17 @@ int board_early_init_r(void)
gd405ep_set_fpga_reset(0);
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
struct ihs_fpga *fpga =
(struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k);
#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
u16 *reflection_target = &fpga->reflection_low;
#else
u16 *reflection_target = &fpga->reflection_high;
#endif
/*
* wait for fpga out of reset
*/
ctr = 0;
while (1) {
out_le16(&fpga->reflection_low,
REFLECTION_TESTPATTERN);
u16 val;
FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
if (in_le16(reflection_target) ==
REFLECTION_TESTPATTERN_INV)
FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
if (val == REFLECTION_TESTPATTERN_INV)
break;
udelay(100000);
......
......@@ -55,6 +55,8 @@ enum {
RAM_DDR2_64 = 2,
};
struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
int misc_init_r(void)
{
/* startup fans */
......@@ -79,10 +81,9 @@ static unsigned int get_mc2_present(void)
static void print_fpga_info(unsigned dev)
{
struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(dev);
u16 versions = in_le16(&fpga->versions);
u16 fpga_version = in_le16(&fpga->fpga_version);
u16 fpga_features = in_le16(&fpga->fpga_features);
u16 versions;
u16 fpga_version;
u16 fpga_features;
unsigned unit_type;
unsigned hardware_version;
unsigned feature_rs232;
......@@ -96,6 +97,10 @@ static void print_fpga_info(unsigned dev)
printf("FPGA%d: ", dev);
FPGA_GET_REG(dev, versions, &versions);
FPGA_GET_REG(dev, fpga_version, &fpga_version);
FPGA_GET_REG(dev, fpga_features, &fpga_features);
hardware_version = versions & 0x000f;
if (fpga_state
......@@ -247,8 +252,9 @@ int checkboard(void)
int last_stage_init(void)
{
struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
u16 versions = in_le16(&fpga->versions);
u16 versions;
FPGA_GET_REG(0, versions, &versions);
print_fpga_info(0);
if (get_mc2_present())
......
......@@ -37,6 +37,8 @@ enum {
HWVER_122 = 3,
};
struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
int misc_init_r(void)
{
/* startup fans */
......@@ -101,15 +103,18 @@ int checkboard(void)
static void print_fpga_info(void)
{
struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
u16 versions = in_le16(&fpga->versions);
u16 fpga_version = in_le16(&fpga->fpga_version);
u16 fpga_features = in_le16(&fpga->fpga_features);
u16 versions;
u16 fpga_version;
u16 fpga_features;
unsigned unit_type;
unsigned hardware_version;
unsigned feature_channels;
unsigned feature_expansion;
FPGA_GET_REG(0, versions, &versions);
FPGA_GET_REG(0, fpga_version, &fpga_version);
FPGA_GET_REG(0, fpga_features, &fpga_features);
unit_type = (versions & 0xf000) >> 12;
hardware_version = versions & 0x000f;
feature_channels = fpga_features & 0x007f;
......@@ -163,7 +168,6 @@ static void print_fpga_info(void)
*/
int last_stage_init(void)
{
struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
unsigned int k;
print_fpga_info();
......@@ -175,7 +179,7 @@ int last_stage_init(void)
configure_gbit_phy(k);
/* take fpga serdes blocks out of reset */
out_le16(&fpga->quad_serdes_reset, 0);
FPGA_SET_REG(0, quad_serdes_reset, 0);
return 0;
}
......
......@@ -7,6 +7,7 @@
#include <common.h>
#include <command.h>
#include <errno.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/ppc4xx-gpio.h>
......@@ -15,6 +16,15 @@
#include <gdsys_fpga.h>
#include "../common/osd.h"
#include "../common/mclink.h"
#include <i2c.h>
#include <pca953x.h>
#include <pca9698.h>
#include <miiphy.h>
DECLARE_GLOBAL_DATA_PTR;
#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
......@@ -31,11 +41,20 @@ enum {
HWVER_100 = 0,
HWVER_104 = 1,
HWVER_110 = 2,
HWVER_120 = 3,
HWVER_200 = 4,
HWVER_210 = 5,
};
enum {
FPGA_HWVER_200 = 0,
FPGA_HWVER_210 = 1,
};
enum {
COMPRESSION_NONE = 0,
COMPRESSION_TYPE1_DELTA,
COMPRESSION_TYPE1_DELTA = 1,
COMPRESSION_TYPE1_TYPE2_DELTA = 3,
};
enum {
......@@ -51,8 +70,71 @@ enum {
enum {
RAM_DDR2_32 = 0,
RAM_DDR3_32 = 1,
};
enum {
MCFPGA_DONE = 1 << 0,
MCFPGA_INIT_N = 1 << 1,
MCFPGA_PROGRAM_N = 1 << 2,
MCFPGA_UPDATE_ENABLE_N = 1 << 3,
MCFPGA_RESET_N = 1 << 4,
};
enum {
GPIO_MDC = 1 << 14,
GPIO_MDIO = 1 << 15,
};
unsigned int mclink_fpgacount;
struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
static int setup_88e1518(const char *bus, unsigned char addr);
static int verify_88e1518(const char *bus, unsigned char addr);
int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
{
int res;
switch (fpga) {
case 0:
out_le16(reg, data);
break;
default:
res = mclink_send(fpga - 1, regoff, data);
if (res < 0) {
printf("mclink_send reg %02lx data %04x returned %d\n",
regoff, data, res);
return res;
}
break;
}
return 0;
}
int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
{
int res;
switch (fpga) {
case 0:
*data = in_le16(reg);
break;
default:
if (fpga > mclink_fpgacount)
return -EINVAL;
res = mclink_receive(fpga - 1, regoff, data);
if (res < 0) {
printf("mclink_receive reg %02lx returned %d\n",
regoff, res);
return res;
}
}
return 0;
}
/*
* Check Board Identity:
*/
......@@ -74,12 +156,11 @@ int checkboard(void)
return 0;
}
static void print_fpga_info(void)
static void print_fpga_info(unsigned int fpga)
{
struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
u16 versions = in_le16(&fpga->versions);
u16 fpga_version = in_le16(&fpga->fpga_version);
u16 fpga_features = in_le16(&fpga->fpga_features);
u16 versions;
u16 fpga_version;
u16 fpga_features;
unsigned unit_type;
unsigned hardware_version;
unsigned feature_compression;
......@@ -89,9 +170,13 @@ static void print_fpga_info(void)
unsigned feature_ramconfig;
unsigned feature_carriers;
unsigned feature_video_channels;
int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
FPGA_GET_REG(0, versions, &versions);
FPGA_GET_REG(0, fpga_version, &fpga_version);
FPGA_GET_REG(0, fpga_features, &fpga_features);
unit_type = (versions & 0xf000) >> 12;
hardware_version = versions & 0x000f;
feature_compression = (fpga_features & 0xe000) >> 13;
feature_osd = fpga_features & (1<<11);
feature_audio = (fpga_features & 0x0600) >> 9;
......@@ -100,6 +185,9 @@ static void print_fpga_info(void)
feature_carriers = (fpga_features & 0x000c) >> 2;
feature_video_channels = fpga_features & 0x0003;
if (legacy)
printf("legacy ");
switch (unit_type) {
case UNITTYPE_MAIN_USER:
printf("Mainchannel");
......@@ -114,27 +202,68 @@ static void print_fpga_info(void)
break;
}
switch (hardware_version) {
case HWVER_100:
printf(" HW-Ver 1.00\n");
break;
case HWVER_104:
printf(" HW-Ver 1.04\n");
break;
case HWVER_110:
printf(" HW-Ver 1.10\n");
break;
if (unit_type == UNITTYPE_MAIN_USER) {
if (legacy)
hardware_version =
(in_le16((void *)LATCH2_BASE)>>8) & 0x0f;
else
hardware_version =
(!!pca9698_get_value(0x20, 24) << 0)
| (!!pca9698_get_value(0x20, 25) << 1)
| (!!pca9698_get_value(0x20, 26) << 2)
| (!!pca9698_get_value(0x20, 27) << 3);
switch (hardware_version) {
case HWVER_100:
printf(" HW-Ver 1.00,");
break;
case HWVER_104:
printf(" HW-Ver 1.04,");
break;
case HWVER_110:
printf(" HW-Ver 1.10,");
break;
case HWVER_120:
printf(" HW-Ver 1.20-1.21,");
break;
case HWVER_200:
printf(" HW-Ver 2.00,");
break;
case HWVER_210:
printf(" HW-Ver 2.10,");
break;
default:
printf(" HW-Ver %d(not supported),",
hardware_version);
break;
}
}
default:
printf(" HW-Ver %d(not supported)\n",
hardware_version);
break;
if (unit_type == UNITTYPE_VIDEO_USER) {
hardware_version = versions & 0x000f;
switch (hardware_version) {
case FPGA_HWVER_200:
printf(" HW-Ver 2.00,");
break;
case FPGA_HWVER_210:
printf(" HW-Ver 2.10,");
break;
default:
printf(" HW-Ver %d(not supported),",
hardware_version);
break;
}
}
printf(" FPGA V %d.%02d, features:",
fpga_version / 100, fpga_version % 100);
printf(" FPGA V %d.%02d\n features:",
fpga_version / 100, fpga_version % 100);
switch (feature_compression) {
......@@ -146,6 +275,10 @@ static void print_fpga_info(void)
printf(" type1-deltacompression");
break;
case COMPRESSION_TYPE1_TYPE2_DELTA:
printf(" type1-deltacompression, type2-inlinecompression");
break;
default:
printf(" compression %d(not supported)", feature_compression);
break;
......@@ -192,6 +325,10 @@ static void print_fpga_info(void)
printf(", RAM 32 bit DDR2");
break;
case RAM_DDR3_32:
printf(", RAM 32 bit DDR3");
break;
default:
printf(", RAM %d(not supported)", feature_ramconfig);
break;
......@@ -204,41 +341,117 @@ static void print_fpga_info(void)
int last_stage_init(void)
{
print_fpga_info();
int slaves;
unsigned int k;
unsigned char mclink_controllers[] = { 0x24, 0x25, 0x26 };
int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
print_fpga_info(0);
osd_probe(0);
/* wait for FPGA done */
for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
unsigned int ctr = 0;
if (i2c_probe(mclink_controllers[k]))
continue;
while (!(pca953x_get_val(mclink_controllers[k])
& MCFPGA_DONE)) {
udelay(100000);
if (ctr++ > 5) {
printf("no done for mclink_controller %d\n", k);
break;
}
}
}
if (!legacy) {
miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read,
bb_miiphy_write);
if (!verify_88e1518(bb_miiphy_buses[0].name, 0)) {
printf("Fixup 88e1518 erratum on %s\n",
bb_miiphy_buses[0].name);
setup_88e1518(bb_miiphy_buses[0].name, 0);
}
}
return osd_probe(0);
/* wait for slave-PLLs to be up and running */
udelay(500000);
mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
slaves = mclink_probe();
mclink_fpgacount = 0;
if (slaves <= 0)
return 0;
mclink_fpgacount = slaves;
for (k = 1; k <= slaves; ++k) {
print_fpga_info(k);
osd_probe(k);
miiphy_register(bb_miiphy_buses[k].name,
bb_miiphy_read, bb_miiphy_write);
if (!verify_88e1518(bb_miiphy_buses[k].name, 0)) {
printf("Fixup 88e1518 erratum on %s\n",
bb_miiphy_buses[k].name);
setup_88e1518(bb_miiphy_buses[k].name, 0);
}
}
return 0;
}
/*
* provide access to fpga gpios (for I2C bitbang)
* (these may look all too simple but make iocon.h much more readable)
*/
void fpga_gpio_set(int pin)
void fpga_gpio_set(unsigned int bus, int pin)
{
out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x18), pin);
FPGA_SET_REG(bus, gpio.set, pin);
}
void fpga_gpio_clear(int pin)
void fpga_gpio_clear(unsigned int bus, int pin)
{
out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x16), pin);
FPGA_SET_REG(bus, gpio.clear, pin);
}
int fpga_gpio_get(int pin)
int fpga_gpio_get(unsigned int bus, int pin)
{
return in_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x14)) & pin;
u16 val;
FPGA_GET_REG(bus, gpio.read, &val);
return val & pin;
}
void gd405ep_init(void)
{
unsigned int k;
if (i2c_probe(0x20)) { /* i2c_probe returns 0 on success */
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k)
gd->arch.fpga_state[k] |= FPGA_STATE_PLATFORM;
} else {
pca9698_direction_output(0x20, 4, 1);
}
}
void gd405ep_set_fpga_reset(unsigned state)
{
if (state) {
out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
if (legacy) {
if (state) {
out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
} else {
out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
}
} else {
out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
pca9698_set_value(0x20, 4, state ? 0 : 1);
}
}
......@@ -253,5 +466,200 @@ void gd405ep_setup_hw(void)
int gd405ep_get_fpga_done(unsigned fpga)
{
return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
if (legacy)
return in_le16((void *)LATCH2_BASE)
& CONFIG_SYS_FPGA_DONE(fpga);
else
return pca9698_get_value(0x20, 20);
}
/*
* FPGA MII bitbang implementation
*/
struct fpga_mii {
unsigned fpga;
int mdio;
} fpga_mii[] = {
{ 0, 1},
{ 1, 1},
{ 2, 1},
{ 3, 1},
};
static int mii_dummy_init(struct bb_miiphy_bus *bus)
{
return 0;
}
static int mii_mdio_active(struct bb_miiphy_bus *bus)
{
struct fpga_mii *fpga_mii = bus->priv;
if (fpga_mii->mdio)
FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
else
FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
return 0;
}
static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
{
struct fpga_mii *fpga_mii = bus->priv;
FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
return 0;
}
static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
{
struct fpga_mii *fpga_mii = bus->priv;
if (v)
FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
else
FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
fpga_mii->mdio = v;
return 0;
}
static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
{
u16 gpio;
struct fpga_mii *fpga_mii = bus->priv;
FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
*v = ((gpio & GPIO_MDIO) != 0);
return 0;
}
static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
{
struct fpga_mii *fpga_mii = bus->priv;
if (v)
FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
else
FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
return 0;
}
static int mii_delay(struct bb_miiphy_bus *bus)
{