Commit 595f3e56 authored by Liu Hui-R64343's avatar Liu Hui-R64343 Committed by Albert Aribaud
Browse files

MX5: Add initial support for MX53 processor



Add initial support for Freescale MX53 processor,

- Add the iomux support and the pin definition,
- Add the regs definition, clean up some unused def from mx51,
- Add the low level init support, make use the freq input of setup_pll macro
Signed-off-by: default avatarJason Liu  <r64343@freescale.com>
parent 877eb0f9
......@@ -34,7 +34,7 @@ enum iomux_reg_addr {
IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR,
IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END,
IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START,
IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR,
IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR + INPUT_CTL_START,
};
#define MUX_PIN_NUM_MAX (((MUX_I_END - MUX_I_START) >> 2) + 1)
......@@ -44,11 +44,12 @@ static inline u32 get_mux_reg(iomux_pin_name_t pin)
{
u32 mux_reg = PIN_TO_IOMUX_MUX(pin);
#if defined(CONFIG_MX51)
if (is_soc_rev(CHIP_REV_2_0) < 0) {
/*
* Fixup register address:
* i.MX51 TO1 has offset with the register
* which is define as TO2.
* i.MX51 TO1 has offset with the register
* which is define as TO2.
*/
if ((pin == MX51_PIN_NANDF_RB5) ||
(pin == MX51_PIN_NANDF_RB6) ||
......@@ -59,6 +60,7 @@ static inline u32 get_mux_reg(iomux_pin_name_t pin)
else if (mux_reg >= 0x130)
mux_reg += 0xC;
}
#endif
mux_reg += IOMUXSW_MUX_CTL;
return mux_reg;
}
......@@ -68,11 +70,12 @@ static inline u32 get_pad_reg(iomux_pin_name_t pin)
{
u32 pad_reg = PIN_TO_IOMUX_PAD(pin);
#if defined(CONFIG_MX51)
if (is_soc_rev(CHIP_REV_2_0) < 0) {
/*
* Fixup register address:
* i.MX51 TO1 has offset with the register
* which is define as TO2.
* i.MX51 TO1 has offset with the register
* which is define as TO2.
*/
if ((pin == MX51_PIN_NANDF_RB5) ||
(pin == MX51_PIN_NANDF_RB6) ||
......@@ -91,6 +94,7 @@ static inline u32 get_pad_reg(iomux_pin_name_t pin)
else
pad_reg += 8;
}
#endif
pad_reg += IOMUXSW_PAD_CTL;
return pad_reg;
}
......@@ -98,10 +102,13 @@ static inline u32 get_pad_reg(iomux_pin_name_t pin)
/* Get the last iomux register address */
static inline u32 get_mux_end(void)
{
#if defined(CONFIG_MX51)
if (is_soc_rev(CHIP_REV_2_0) < 0)
return IOMUXC_BASE_ADDR + (0x3F8 - 4);
else
return IOMUXC_BASE_ADDR + (0x3F0 - 4);
#endif
return IOMUXSW_MUX_END;
}
/*
......@@ -164,3 +171,16 @@ unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin)
u32 pad_reg = get_pad_reg(pin);
return readl(pad_reg);
}
/*
* This function configures daisy-chain
*
* @param input index of input select register
* @param config the binary value of elements
*/
void mxc_iomux_set_input(iomux_input_select_t input, u32 config)
{
u32 reg = IOMUXSW_INPUT_CTL + (input << 2);
writel(config, reg);
}
......@@ -70,6 +70,7 @@
/* M4IF setup */
.macro init_m4if
#ifdef CONFIG_MX51
/* VPU and IPU given higher priority (0x4)
* IPU accesses with ID=0x1 given highest priority (=0xA)
*/
......@@ -87,27 +88,31 @@
ldr r1, =0x001901A3
str r1, [r0, #0x48]
#endif
.endm /* init_m4if */
.macro setup_pll pll, freq
ldr r2, =\pll
ldr r0, =\pll
ldr r1, =0x00001232
str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
mov r1, #0x2
str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
str r3, [r2, #PLL_DP_OP]
str r3, [r2, #PLL_DP_HFS_OP]
ldr r1, W_DP_OP_\freq
str r1, [r0, #PLL_DP_OP]
str r1, [r0, #PLL_DP_HFS_OP]
str r4, [r2, #PLL_DP_MFD]
str r4, [r2, #PLL_DP_HFS_MFD]
ldr r1, W_DP_MFD_\freq
str r1, [r0, #PLL_DP_MFD]
str r1, [r0, #PLL_DP_HFS_MFD]
str r5, [r2, #PLL_DP_MFN]
str r5, [r2, #PLL_DP_HFS_MFN]
ldr r1, W_DP_MFN_\freq
str r1, [r0, #PLL_DP_MFN]
str r1, [r0, #PLL_DP_HFS_MFN]
ldr r1, =0x00001232
str r1, [r2, #PLL_DP_CTL]
1: ldr r1, [r2, #PLL_DP_CTL]
str r1, [r0, #PLL_DP_CTL]
1: ldr r1, [r0, #PLL_DP_CTL]
ands r1, r1, #0x1
beq 1b
.endm
......@@ -115,6 +120,7 @@
.macro init_clock
ldr r0, =CCM_BASE_ADDR
#if defined(CONFIG_MX51)
/* Gate of clocks to the peripherals first */
ldr r1, =0x3FFFFFFF
str r1, [r0, #CLKCTL_CCGR0]
......@@ -141,19 +147,16 @@
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
bne 1b
#endif
/* Switch ARM to step clock */
mov r1, #0x4
str r1, [r0, #CLKCTL_CCSR]
mov r3, #DP_OP_800
mov r4, #DP_MFD_800
mov r5, #DP_MFN_800
setup_pll PLL1_BASE_ADDR
mov r3, #DP_OP_665
mov r4, #DP_MFD_665
mov r5, #DP_MFN_665
setup_pll PLL3_BASE_ADDR
setup_pll PLL1_BASE_ADDR, 800
#if defined(CONFIG_MX51)
setup_pll PLL3_BASE_ADDR, 665
/* Switch peripheral to PLL 3 */
ldr r0, =CCM_BASE_ADDR
......@@ -162,10 +165,7 @@
str r1, [r0, #CLKCTL_CBCMR]
ldr r1, =0x13239145
str r1, [r0, #CLKCTL_CBCDR]
mov r3, #DP_OP_665
mov r4, #DP_MFD_665
mov r5, #DP_MFN_665
setup_pll PLL2_BASE_ADDR
setup_pll PLL2_BASE_ADDR, 665
/* Switch peripheral to PLL2 */
ldr r0, =CCM_BASE_ADDR
......@@ -174,12 +174,8 @@
ldr r1, =0x000020C0
orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
mov r3, #DP_OP_216
mov r4, #DP_MFD_216
mov r5, #DP_MFN_216
setup_pll PLL3_BASE_ADDR
#endif
setup_pll PLL3_BASE_ADDR, 216
/* Set the platform clock dividers */
ldr r0, =ARM_BASE_ADDR
......@@ -188,18 +184,23 @@
ldr r0, =CCM_BASE_ADDR
#if defined(CONFIG_MX51)
/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
ldr r1, =0x0
ldr r3, [r1, #ROM_SI_REV]
cmp r3, #0x10
movls r1, #0x1
movhi r1, #0
str r1, [r0, #CLKCTL_CACRR]
#else
mov r1, #0
#endif
str r1, [r0, #CLKCTL_CACRR]
/* Switch ARM back to PLL 1 */
mov r1, #0
str r1, [r0, #CLKCTL_CCSR]
#if defined(CONFIG_MX51)
/* setup the rest */
/* Use lp_apm (24MHz) source for perclk */
ldr r1, =0x000020C2
......@@ -208,6 +209,7 @@
/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
ldr r1, =CONFIG_SYS_CLKTL_CBCDR
str r1, [r0, #CLKCTL_CBCDR]
#endif
/* Restore the default values in the Gate registers */
ldr r1, =0xFFFFFFFF
......@@ -218,13 +220,23 @@
str r1, [r0, #CLKCTL_CCGR4]
str r1, [r0, #CLKCTL_CCGR5]
str r1, [r0, #CLKCTL_CCGR6]
#if defined(CONFIG_MX53)
str r1, [r0, #CLKCTL_CCGR7]
#endif
#if defined(CONFIG_MX51)
/* Use PLL 2 for UART's, get 66.5MHz from it */
ldr r1, =0xA5A2A020
str r1, [r0, #CLKCTL_CSCMR1]
ldr r1, =0x00C30321
str r1, [r0, #CLKCTL_CSCDR1]
#elif defined(CONFIG_MX53)
ldr r1, [r0, #CLKCTL_CSCDR1]
orr r1, r1, #0x3f
eor r1, r1, #0x3f
orr r1, r1, #0x21
str r1, [r0, #CLKCTL_CSCDR1]
#endif
/* make sure divider effective */
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
......@@ -249,6 +261,7 @@
.globl lowlevel_init
lowlevel_init:
#if defined(CONFIG_MX51)
ldr r0, =GPIO1_BASE_ADDR
ldr r1, [r0, #0x0]
orr r1, r1, #(1 << 23)
......@@ -256,6 +269,7 @@ lowlevel_init:
ldr r1, [r0, #0x4]
orr r1, r1, #(1 << 23)
str r1, [r0, #0x4]
#endif
init_l2cc
......@@ -269,9 +283,12 @@ lowlevel_init:
mov pc,lr
/* Board level setting value */
DDR_PERCHARGE_CMD: .word 0x04008008
DDR_REFRESH_CMD: .word 0x00008010
DDR_LMR1_W: .word 0x00338018
DDR_LMR_CMD: .word 0xB2220000
DDR_TIMING_W: .word 0xB02567A9
DDR_MISC_W: .word 0x000A0104
W_DP_OP_800: .word DP_OP_800
W_DP_MFD_800: .word DP_MFD_800
W_DP_MFN_800: .word DP_MFN_800
W_DP_OP_665: .word DP_OP_665
W_DP_MFD_665: .word DP_MFD_665
W_DP_MFN_665: .word DP_MFN_665
W_DP_OP_216: .word DP_OP_216
W_DP_MFD_216: .word DP_MFD_216
W_DP_MFN_216: .word DP_MFN_216
......@@ -33,17 +33,20 @@
#include <fsl_esdhc.h>
#endif
#if defined(CONFIG_MX51)
#define CPU_TYPE 0x51000
#else
#if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
#error "CPU_TYPE not defined"
#endif
u32 get_cpu_rev(void)
{
int system_rev = CPU_TYPE;
#ifdef CONFIG_MX51
int system_rev = 0x51000;
#else
int system_rev = 0x53000;
#endif
int reg = __raw_readl(ROM_SI_REV);
#if defined(CONFIG_MX51)
switch (reg) {
case 0x02:
system_rev |= CHIP_REV_1_1;
......@@ -57,11 +60,20 @@ u32 get_cpu_rev(void)
case 0x20:
system_rev |= CHIP_REV_3_0;
break;
return system_rev;
default:
system_rev |= CHIP_REV_1_0;
break;
}
#else
switch (reg) {
case 0x20:
system_rev |= CHIP_REV_2_0;
break;
default:
system_rev |= CHIP_REV_1_0;
break;
}
#endif
return system_rev;
}
......
......@@ -37,7 +37,12 @@
#define CLKCTL_CCGR4 0x78
#define CLKCTL_CCGR5 0x7C
#define CLKCTL_CCGR6 0x80
#if defined(CONFIG_MX53)
#define CLKCTL_CCGR7 0x84
#define CLKCTL_CMEOR 0x88
#elif defined(CONFIG_MX51)
#define CLKCTL_CMEOR 0x84
#endif
/* DPLL */
#define PLL_DP_CTL 0x00
......
......@@ -20,38 +20,36 @@
* MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_MXC_MX51_H__
#define __ASM_ARCH_MXC_MX51_H__
#ifndef __ASM_ARCH_MX5_IMX_REGS_H__
#define __ASM_ARCH_MX5_IMX_REGS_H__
/*
* IRAM
*/
#if defined(CONFIG_MX51)
#define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
#define IRAM_SIZE 0x00020000 /* 128 KB */
/*
* Graphics Memory of GPU
*/
#define GPU_BASE_ADDR 0x20000000
#define GPU_CTRL_BASE_ADDR 0x30000000
#define IPU_CTRL_BASE_ADDR 0x40000000
/*
* Debug
*/
#define DEBUG_BASE_ADDR 0x60000000
#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000)
#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000)
#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000)
#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000)
#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000)
#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000)
#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000)
#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000)
#define SPBA0_BASE_ADDR 0x70000000
#define AIPS1_BASE_ADDR 0x73F00000
#define AIPS2_BASE_ADDR 0x83F00000
#define CSD0_BASE_ADDR 0x90000000
#define CSD1_BASE_ADDR 0xA0000000
#define NFC_BASE_ADDR_AXI 0xCFFF0000
#elif defined(CONFIG_MX53)
#define IPU_CTRL_BASE_ADDR 0x18000000
#define SPBA0_BASE_ADDR 0x50000000
#define AIPS1_BASE_ADDR 0x53F00000
#define AIPS2_BASE_ADDR 0x63F00000
#define CSD0_BASE_ADDR 0x70000000
#define CSD1_BASE_ADDR 0xB0000000
#define NFC_BASE_ADDR_AXI 0xF7FF0000
#define IRAM_BASE_ADDR 0xF8000000
#else
#error "CPU_TYPE not defined"
#endif
#define IRAM_SIZE 0x00020000 /* 128 KB */
/*
* SPBA global module enabled #0
*/
#define SPBA0_BASE_ADDR 0x70000000
#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
......@@ -68,8 +66,6 @@
/*
* AIPS 1
*/
#define AIPS1_BASE_ADDR 0x73F00000
#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
......@@ -91,11 +87,14 @@
#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
#if defined(CONFIG_MX53)
#define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000)
#define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000)
#define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000)
#endif
/*
* AIPS 2
*/
#define AIPS2_BASE_ADDR 0x83F00000
#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
......@@ -129,30 +128,7 @@
#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000)
#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
#define TZIC_BASE_ADDR 0x8FFFC000
/*
* Memory regions and CS
*/
#define CSD0_BASE_ADDR 0x90000000
#define CSD1_BASE_ADDR 0xA0000000
#define CS0_BASE_ADDR 0xB0000000
#define CS1_BASE_ADDR 0xB8000000
#define CS2_BASE_ADDR 0xC0000000
#define CS3_BASE_ADDR 0xC8000000
#define CS4_BASE_ADDR 0xCC000000
#define CS5_BASE_ADDR 0xCE000000
/*
* NFC
*/
#define NFC_BASE_ADDR_AXI 0xCFFF0000 /* NAND flash AXI */
/*!
* Number of GPIO port as defined in the IC Spec
*/
#define GPIO_PORT_NUM 4
/*!
* Number of GPIO pins per port
*/
#define GPIO_NUM_PIN 32
......@@ -311,4 +287,4 @@ struct fuse_bank1_regs {
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_MXC_MX51_H__ */
#endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */
......@@ -70,108 +70,6 @@ typedef enum iomux_pad_config {
PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,/* High voltage mode */
} iomux_pad_config_t;
/* various IOMUX input select register index */
typedef enum iomux_input_select {
MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0,
MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I,
MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT,
MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,
MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT,
MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT,
MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT,
MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT,
MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT,
MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT,
MUX_IN_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT,
MUX_IN_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT,
MUX_IN_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT,
MUX_IN_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT,
MUX_IN_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT,
MUX_IN_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT,
MUX_IN_CCM_IPP_DI_CLK_SELECT_INPUT,
/* TO2 */
MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT,
MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT,
MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT,
MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT,
MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT,
MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT,
MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT,
MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT,
MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT,
MUX_IN_DPLLIP1_L1T_TOG_EN_SELECT_INPUT,
/* TO2 */
MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT,
MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT,
MUX_IN_EMI_IPP_IND_RDY_INT_SELECT_INPUT,
MUX_IN_ESDHC3_IPP_DAT0_IN_SELECT_INPUT,
MUX_IN_ESDHC3_IPP_DAT1_IN_SELECT_INPUT,
MUX_IN_ESDHC3_IPP_DAT2_IN_SELECT_INPUT,
MUX_IN_ESDHC3_IPP_DAT3_IN_SELECT_INPUT,
MUX_IN_FEC_FEC_COL_SELECT_INPUT,
MUX_IN_FEC_FEC_CRS_SELECT_INPUT,
MUX_IN_FEC_FEC_MDI_SELECT_INPUT,
MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT,
MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT,
MUX_IN_FEC_FEC_RDATA_2_SELECT_INPUT,
MUX_IN_FEC_FEC_RDATA_3_SELECT_INPUT,
MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT,
MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT,
MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT,
MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT,
MUX_IN_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT,
MUX_IN_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT,
MUX_IN_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT,
MUX_IN_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,
MUX_IN_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT,
MUX_IN_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT,
MUX_IN_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT,
MUX_IN_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT,
/* TO2 */
MUX_IN_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT,
MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT,
MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT,
/* TO2 */
MUX_IN_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT,
/* TO2 */
MUX_IN_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT,
MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT,
MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT,
MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT,
MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT,
MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT,
MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT,
MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT,
MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT,
MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT,
MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT,
MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT,
MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT,
MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT,
MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT,
MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT,
MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT,
MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
MUX_IN_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT,
MUX_IN_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT,
MUX_IN_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT,
MUX_IN_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT,
MUX_IN_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT,
MUX_IN_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT,
MUX_IN_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT,
MUX_IN_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT,
MUX_IN_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT,
MUX_IN_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT,
MUX_IN_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT,
MUX_IN_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT,
MUX_INPUT_NUM_MUX,
} iomux_input_select_t;
/* various IOMUX input functions */
typedef enum iomux_input_config {
INPUT_CTL_PATH0 = 0x0,
......
This diff is collapsed.
......@@ -24,8 +24,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
#define CONFIG_MX51 /* in a mx51 */
......@@ -37,6 +35,7 @@
#define CONFIG_L2_OFF
#include <asm/arch/imx-regs.h>
/*
* Disabled for now due to build problems under Debian and a significant
* increase in the final file size: 144260 vs. 109536 Bytes.
......
......@@ -24,11 +24,12 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/arch/imx-regs.h>
#define CONFIG_MX51 /* in a mx51 */
#define CONFIG_L2_OFF
#include <asm/arch/imx-regs.h>
#define CONFIG_SYS_MX5_HCLK 24000000
#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
......
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