Commit 5bb907a4 authored by Ron Madrid's avatar Ron Madrid Committed by Kim Phillips
Browse files

mpc83xx: New board support for SIMPC8313



This patch will create a new board, SIMPC8313, from Sheldon Instruments.  This
board boots from NAND devices and is configureable for either large or small
page devices.  The board supports non-soldered DDR2, one ethernet port, a
Marvell 88E1118 PHY, and PCI host support.  The board also has a FPGA connected
to the eLBC providing glue logic to a TMS320C67xx DSP.
Signed-off-by: default avatarRon Madrid <ron_madrid@sbcglobal.net>
Signed-off-by: default avatarKim Phillips <kim.phillips@freescale.com>
parent 66778761
......@@ -263,6 +263,10 @@ Jon Loeliger <jdl@freescale.com>
MPC8641HPCN MPC8641D
Ron Madrid <info@sheldoninst.com>
SIMPC8313 MPC8313
Dan Malek <dan@embeddedalley.com>
stxgp3 MPC85xx
......
......@@ -353,6 +353,7 @@ LIST_83xx=" \
MPC837XERDB \
MVBLM7 \
sbc8349 \
SIMPC8313_LP \
TQM834x \
"
......
......@@ -2328,6 +2328,21 @@ MVBLM7_config: unconfig
sbc8349_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349
SIMPC8313_LP_config \
SIMPC8313_SP_config: unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)board/sheldon/simpc8313
@if [ "$(findstring _LP_,$@)" ] ; then \
$(XECHO) -n "...Large Page NAND..." ; \
echo "#define CONFIG_NAND_LP" >> $(obj)include/config.h ; \
fi ; \
if [ "$(findstring _SP_,$@)" ] ; then \
$(XECHO) -n "...Small Page NAND..." ; \
echo "#define CONFIG_NAND_SP" >> $(obj)include/config.h ; \
fi ;
@$(MKCONFIG) -a SIMPC8313 ppc mpc83xx simpc8313 sheldon
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
TQM834x_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x tqc
......
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o sdram.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
ifndef NAND_SPL
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
endif
ifndef TEXT_BASE
TEXT_BASE = 0x00100000
endif
ifdef CONFIG_NAND_LP
PAD_TO = 0xFFF20000
else
PAD_TO = 0xFFF04000
endif
/*
* Copyright (C) Freescale Semiconductor, Inc. 2006-2007
* Copyright (C) Sheldon Instruments, Inc. 2008
*
* Author: Ron Madrid <info@sheldoninst.com>
*
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc83xx.h>
#include <spd_sdram.h>
#include <asm/bitops.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/mmu.h>
DECLARE_GLOBAL_DATA_PTR;
static long fixed_sdram(void);
#if defined(CONFIG_NAND_SPL)
void si_wait_i2c(void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
while (!(__raw_readb(&im->i2c[0].sr) & 0x02))
;
__raw_writeb(0x00, &im->i2c[0].sr);
sync();
return;
}
void si_read_i2c(u32 lbyte, int count, u8 *buffer)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 i;
u8 chip = 0x50 << 1; /* boot sequencer I2C */
u32 ubyte = (lbyte & 0xff00) >> 8;
lbyte &= 0xff;
/*
* Set up controller
*/
__raw_writeb(0x3f, &im->i2c[0].fdr);
__raw_writeb(0x00, &im->i2c[0].adr);
__raw_writeb(0x00, &im->i2c[0].sr);
__raw_writeb(0x00, &im->i2c[0].dr);
while (__raw_readb(&im->i2c[0].sr) & 0x20)
;
/*
* Writing address to device
*/
__raw_writeb(0xb0, &im->i2c[0].cr);
sync();
__raw_writeb(chip, &im->i2c[0].dr);
si_wait_i2c();
__raw_writeb(0xb0, &im->i2c[0].cr);
sync();
__raw_writeb(ubyte, &im->i2c[0].dr);
si_wait_i2c();
__raw_writeb(lbyte, &im->i2c[0].dr);
si_wait_i2c();
__raw_writeb(0xb4, &im->i2c[0].cr);
sync();
__raw_writeb(chip + 1, &im->i2c[0].dr);
si_wait_i2c();
__raw_writeb(0xa0, &im->i2c[0].cr);
sync();
/*
* Dummy read
*/
__raw_readb(&im->i2c[0].dr);
si_wait_i2c();
/*
* Read actual data
*/
for (i = 0; i < count; i++)
{
if (i == (count - 2)) /* Reached next to last byte, No ACK */
__raw_writeb(0xa8, &im->i2c[0].cr);
if (i == (count - 1)) /* Reached last byte, STOP */
__raw_writeb(0x88, &im->i2c[0].cr);
/* Read byte of data */
buffer[i] = __raw_readb(&im->i2c[0].dr);
if (i == (count - 1))
break;
si_wait_i2c();
}
return;
}
#endif /* CONFIG_NAND_SPL */
phys_size_t initdram(int board_type)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile fsl_lbus_t *lbc= &im->lbus;
u32 msize;
if ((__raw_readl(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32) im)
return -1;
/* DDR SDRAM - Main SODIMM */
__raw_writel(CONFIG_SYS_DDR_BASE & LAWBAR_BAR, &im->sysconf.ddrlaw[0].bar);
msize = fixed_sdram();
/* Local Bus setup lbcr and mrtpr */
__raw_writel(CONFIG_SYS_LBC_LBCR, &lbc->lbcr);
__raw_writel(CONFIG_SYS_LBC_MRTPR, &lbc->mrtpr);
sync();
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
}
/*************************************************************************
* fixed sdram init -- reads values from boot sequencer I2C
************************************************************************/
static long fixed_sdram(void)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
u32 msizelog2, msize = 1;
#if defined(CONFIG_NAND_SPL)
u32 i;
const u8 bytecount = 135;
u8 buffer[bytecount];
u32 addr, data;
si_read_i2c(0, bytecount, buffer);
for (i = 18; i < bytecount; i += 7){
addr = (u32)buffer[i];
addr <<= 8;
addr |= (u32)buffer[i + 1];
addr <<= 2;
data = (u32)buffer[i + 2];
data <<= 8;
data |= (u32)buffer[i + 3];
data <<= 8;
data |= (u32)buffer[i + 4];
data <<= 8;
data |= (u32)buffer[i + 5];
__raw_writel(data, (u32 *)(CONFIG_SYS_IMMR + addr));
}
sync();
/* enable DDR controller */
__raw_writel((__raw_readl(&im->ddr.sdram_cfg) | SDRAM_CFG_MEM_EN), &im->ddr.sdram_cfg);
#endif /* (CONFIG_NAND_SPL) */
msizelog2 = ((__raw_readl(&im->sysconf.ddrlaw[0].ar) & LAWAR_SIZE) + 1);
msize <<= (msizelog2 - 20);
return msize;
}
/*
* Copyright (C) Freescale Semiconductor, Inc. 2006-2007
* Copyright (C) Sheldon Instruments, Inc. 2008
*
* Author: Ron Madrid <info@sheldoninst.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <libfdt.h>
#include <pci.h>
#include <mpc83xx.h>
#include <ns16550.h>
#include <nand.h>
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
puts("Board: Sheldon Instruments SIMPC8313\n");
return 0;
}
#ifndef CONFIG_NAND_SPL
static struct pci_region pci_regions[] = {
{
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
size: CONFIG_SYS_PCI1_MEM_SIZE,
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
},
{
bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
size: CONFIG_SYS_PCI1_MMIO_SIZE,
flags: PCI_REGION_MEM
},
{
bus_start: CONFIG_SYS_PCI1_IO_BASE,
phys_start: CONFIG_SYS_PCI1_IO_PHYS,
size: CONFIG_SYS_PCI1_IO_SIZE,
flags: PCI_REGION_IO
}
};
void pci_init_board(void)
{
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
struct pci_region *reg[] = { pci_regions };
int warmboot;
/* Enable all 3 PCI_CLK_OUTPUTs. */
clk->occr |= 0xe0000000;
/*
* Configure PCI Local Access Windows
*/
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;
mpc83xx_pci_init(1, reg, warmboot);
}
/*
* Miscellaneous late-boot configurations
*/
int misc_init_r(void)
{
int rc = 0;
return rc;
}
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
}
#endif
#else /* CONFIG_NAND_SPL */
void board_init_f(ulong bootflag)
{
NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
puts("NAND boot... ");
init_timebase();
initdram(0);
relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
CONFIG_SYS_NAND_U_BOOT_RELOC);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
nand_boot();
}
void putc(char c)
{
if (gd->flags & GD_FLG_SILENT)
return;
if (c == '\n')
NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
}
#endif
Sheldon Instruments SIMPC8313 Board
-----------------------------------------
1. Board Switches and Jumpers
S2 is used to set CFG_RESET_SOURCE.
To boot the image in Large page NAND flash, use these DIP
switch settings for S2:
+----------+ ON
| * * **** |
| * * |
+----------+
12345678
To boot the image in Small page NAND flash, use these DIP
switch settings for S2:
+----------+ ON
| *** **** |
| * |
+----------+
12345678
(where the '*' indicates the position of the tab of the switch.)
2. Memory Map
The memory map looks like this:
0x0000_0000 0x1fff_ffff DDR 512M
0x8000_0000 0x8fff_ffff PCI MEM 256M
0x9000_0000 0x9fff_ffff PCI_MMIO 256M
0xe000_0000 0xe00f_ffff IMMR 1M
0xe200_0000 0xe20f_ffff PCI IO 16M
0xe280_0000 0xe280_7fff NAND FLASH (CS0) 32K
or
0xe280_0000 0xe281_ffff NAND FLASH (CS0) 128K
0xff00_0000 0xff00_7fff FPGA (CS1) 1M
3. Compilation
Assuming you're using BASH (or similar) as your shell:
export CROSS_COMPILE=your-cross-compiler-prefix-
make distclean
make SIMPC8313_LP_config
(or make SIMPC8313_SP_config, depending on the page size
of your NAND flash)
make
4. Downloading and Flashing Images
4.1 Reflash U-boot Image using U-boot
=>run update_uboot
You may want to try
=>tftp $loadaddr $uboot
first, to make sure that the TFTP load will succeed before it
goes ahead and wipes out your current firmware. And of course,
if the new u-boot doesn't boot, you can plug the board into
your PCI slot and with the supplied driver and sample app
you can reburn a working u-boot.
4.2 Downloading and Booting Linux Kernel
Ensure that all networking-related environment variables are set
properly (including ipaddr, serverip, gatewayip (if needed),
netmask, ethaddr, eth1addr, fdtfile, and bootfile).
=>tftp $loadaddr uImage
=>nand write $loadaddr kernel $filesize
=>tftp $loadaddr $fdtfile
=>nand write $loadaddr 7e0000 1800
=>boot
5 Notes
The console baudrate for SIMPC8313 is 115200bps.
/*
* Copyright (C) Sheldon Instruments, Inc. 2008
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* simpc8313 board configuration file
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_NAND_U_BOOT
#define CONFIG_E300 1
#define CONFIG_MPC83XX 1
#define CONFIG_MPC831X 1
#define CONFIG_MPC8313 1
#define CONFIG_PCI
#define CONFIG_83XX_GENERIC_PCI
#define CONFIG_MISC_INIT_R
/*
* On-board devices
*
* TSEC1 is Marvell PHY 88E1118
*/
#define CONFIG_SYS_33MHZ
#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
#define CONFIG_SYS_IMMR 0xE0000000
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
#endif
#define CONFIG_SYS_MEMTEST_START 0x00001000
#define CONFIG_SYS_MEMTEST_END 0x07f00000
#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
/*
* Device configurations
*/
#define CONFIG_TSEC1
/*
* DDR Setup
*/
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED (512 << 20)
#define CONFIG_SYS_DDRCDR ( DDRCDR_EN \
| DDRCDR_PZ_NOMZ \
| DDRCDR_NZ_NOMZ \
| DDRCDR_M_ODR )
/* 0x73000002 TODO ODR & DRN ? */
/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
#if !defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */