Commit 5bc48308 authored by Haikun.Wang@freescale.com's avatar Haikun.Wang@freescale.com Committed by Simon Glass
Browse files

dm: spi: Convert Freescale QSPI driver to driver model



Move the Freescale QSPI driver over to driver model.
Signed-off-by: default avatarHaikun Wang <Haikun.Wang@freescale.com>
Signed-off-by: default avatarPeng Fan <Peng.Fan@freescale.com>
Tested-by: default avatarPeng Fan <Peng.Fan@freescale.com>
Acked-by: default avatarSimon Glass <sjg@chromium.org>
parent a8919371
/*
* Copyright 2013-2014 Freescale Semiconductor, Inc.
* Copyright 2013-2015 Freescale Semiconductor, Inc.
*
* Freescale Quad Serial Peripheral Interface (QSPI) driver
*
......@@ -11,8 +11,12 @@
#include <spi.h>
#include <asm/io.h>
#include <linux/sizes.h>
#include <dm.h>
#include <errno.h>
#include "fsl_qspi.h"
DECLARE_GLOBAL_DATA_PTR;
#define RX_BUFFER_SIZE 0x80
#ifdef CONFIG_MX6SX
#define TX_BUFFER_SIZE 0x200
......@@ -63,35 +67,85 @@
#define QSPI_CMD_PP_4B 0x12 /* Page program (up to 256 bytes) */
#define QSPI_CMD_SE_4B 0xdc /* Sector erase (usually 64KiB) */
#ifdef CONFIG_SYS_FSL_QSPI_LE
#define qspi_read32 in_le32
#define qspi_write32 out_le32
#elif defined(CONFIG_SYS_FSL_QSPI_BE)
#define qspi_read32 in_be32
#define qspi_write32 out_be32
#endif
/* fsl_qspi_platdata flags */
#define QSPI_FLAG_REGMAP_ENDIAN_BIG (1 << 0)
static unsigned long spi_bases[] = {
QSPI0_BASE_ADDR,
#ifdef CONFIG_MX6SX
QSPI1_BASE_ADDR,
#endif
};
/* default SCK frequency, unit: HZ */
#define FSL_QSPI_DEFAULT_SCK_FREQ 50000000
static unsigned long amba_bases[] = {
QSPI0_AMBA_BASE,
#ifdef CONFIG_MX6SX
QSPI1_AMBA_BASE,
/* QSPI max chipselect signals number */
#define FSL_QSPI_MAX_CHIPSELECT_NUM 4
#ifdef CONFIG_DM_SPI
/**
* struct fsl_qspi_platdata - platform data for Freescale QSPI
*
* @flags: Flags for QSPI QSPI_FLAG_...
* @speed_hz: Default SCK frequency
* @reg_base: Base address of QSPI registers
* @amba_base: Base address of QSPI memory mapping
* @amba_total_size: size of QSPI memory mapping
* @flash_num: Number of active slave devices
* @num_chipselect: Number of QSPI chipselect signals
*/
struct fsl_qspi_platdata {
u32 flags;
u32 speed_hz;
u32 reg_base;
u32 amba_base;
u32 amba_total_size;
u32 flash_num;
u32 num_chipselect;
};
#endif
/**
* struct fsl_qspi_priv - private data for Freescale QSPI
*
* @flags: Flags for QSPI QSPI_FLAG_...
* @bus_clk: QSPI input clk frequency
* @speed_hz: Default SCK frequency
* @cur_seqid: current LUT table sequence id
* @sf_addr: flash access offset
* @amba_base: Base address of QSPI memory mapping of every CS
* @amba_total_size: size of QSPI memory mapping
* @cur_amba_base: Base address of QSPI memory mapping of current CS
* @flash_num: Number of active slave devices
* @num_chipselect: Number of QSPI chipselect signals
* @regs: Point to QSPI register structure for I/O access
*/
struct fsl_qspi_priv {
u32 flags;
u32 bus_clk;
u32 speed_hz;
u32 cur_seqid;
u32 sf_addr;
u32 amba_base[FSL_QSPI_MAX_CHIPSELECT_NUM];
u32 amba_total_size;
u32 cur_amba_base;
u32 flash_num;
u32 num_chipselect;
struct fsl_qspi_regs *regs;
};
#ifndef CONFIG_DM_SPI
struct fsl_qspi {
struct spi_slave slave;
unsigned long reg_base;
unsigned long amba_base;
u32 sf_addr;
u8 cur_seqid;
struct fsl_qspi_priv priv;
};
#endif
static u32 qspi_read32(u32 flags, u32 *addr)
{
return flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
in_be32(addr) : in_le32(addr);
}
static void qspi_write32(u32 flags, u32 *addr, u32 val)
{
flags & QSPI_FLAG_REGMAP_ENDIAN_BIG ?
out_be32(addr, val) : out_le32(addr, val);
}
/* QSPI support swapping the flash read/write data
* in hardware for LS102xA, but not for VF610 */
......@@ -104,131 +158,135 @@ static inline u32 qspi_endian_xchg(u32 data)
#endif
}
static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave)
{
return container_of(slave, struct fsl_qspi, slave);
}
static void qspi_set_lut(struct fsl_qspi *qspi)
static void qspi_set_lut(struct fsl_qspi_priv *priv)
{
struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
struct fsl_qspi_regs *regs = priv->regs;
u32 lut_base;
/* Unlock the LUT */
qspi_write32(&regs->lutkey, LUT_KEY_VALUE);
qspi_write32(&regs->lckcr, QSPI_LCKCR_UNLOCK);
qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_UNLOCK);
/* Write Enable */
lut_base = SEQID_WREN * 4;
qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_WREN) |
qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREN) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
qspi_write32(&regs->lut[lut_base + 1], 0);
qspi_write32(&regs->lut[lut_base + 2], 0);
qspi_write32(&regs->lut[lut_base + 3], 0);
qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
/* Fast Read */
lut_base = SEQID_FAST_READ * 4;
#ifdef CONFIG_SPI_FLASH_BAR
qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_FAST_READ) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
qspi_write32(priv->flags, &regs->lut[lut_base],
OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
#else
if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_FAST_READ) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
qspi_write32(priv->flags, &regs->lut[lut_base],
OPRND0(QSPI_CMD_FAST_READ) | PAD0(LUT_PAD1) |
INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
else
qspi_write32(&regs->lut[lut_base],
qspi_write32(priv->flags, &regs->lut[lut_base],
OPRND0(QSPI_CMD_FAST_READ_4B) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) |
OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) |
INSTR1(LUT_ADDR));
#endif
qspi_write32(&regs->lut[lut_base + 1], OPRND0(8) | PAD0(LUT_PAD1) |
INSTR0(LUT_DUMMY) | OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) |
INSTR1(LUT_READ));
qspi_write32(&regs->lut[lut_base + 2], 0);
qspi_write32(&regs->lut[lut_base + 3], 0);
qspi_write32(priv->flags, &regs->lut[lut_base + 1],
OPRND0(8) | PAD0(LUT_PAD1) | INSTR0(LUT_DUMMY) |
OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) |
INSTR1(LUT_READ));
qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
/* Read Status */
lut_base = SEQID_RDSR * 4;
qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_RDSR) |
qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDSR) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
PAD1(LUT_PAD1) | INSTR1(LUT_READ));
qspi_write32(&regs->lut[lut_base + 1], 0);
qspi_write32(&regs->lut[lut_base + 2], 0);
qspi_write32(&regs->lut[lut_base + 3], 0);
qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
/* Erase a sector */
lut_base = SEQID_SE * 4;
#ifdef CONFIG_SPI_FLASH_BAR
qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_SE) |
qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_SE) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
#else
if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_SE) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
qspi_write32(priv->flags, &regs->lut[lut_base],
OPRND0(QSPI_CMD_SE) | PAD0(LUT_PAD1) |
INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
else
qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_SE_4B) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
qspi_write32(priv->flags, &regs->lut[lut_base],
OPRND0(QSPI_CMD_SE_4B) | PAD0(LUT_PAD1) |
INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
#endif
qspi_write32(&regs->lut[lut_base + 1], 0);
qspi_write32(&regs->lut[lut_base + 2], 0);
qspi_write32(&regs->lut[lut_base + 3], 0);
qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
/* Erase the whole chip */
lut_base = SEQID_CHIP_ERASE * 4;
qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_CHIP_ERASE) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
qspi_write32(&regs->lut[lut_base + 1], 0);
qspi_write32(&regs->lut[lut_base + 2], 0);
qspi_write32(&regs->lut[lut_base + 3], 0);
qspi_write32(priv->flags, &regs->lut[lut_base],
OPRND0(QSPI_CMD_CHIP_ERASE) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
/* Page Program */
lut_base = SEQID_PP * 4;
#ifdef CONFIG_SPI_FLASH_BAR
qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_PP) |
qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_PP) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
#else
if (FSL_QSPI_FLASH_SIZE <= SZ_16M)
qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_PP) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
qspi_write32(priv->flags, &regs->lut[lut_base],
OPRND0(QSPI_CMD_PP) | PAD0(LUT_PAD1) |
INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
else
qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_PP_4B) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
qspi_write32(priv->flags, &regs->lut[lut_base],
OPRND0(QSPI_CMD_PP_4B) | PAD0(LUT_PAD1) |
INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
#endif
#ifdef CONFIG_MX6SX
/*
* To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
* So, Use IDATSZ in IPCR to determine the size and here set 0.
*/
qspi_write32(&regs->lut[lut_base + 1], OPRND0(0) |
qspi_write32(priv->flags, &regs->lut[lut_base + 1], OPRND0(0) |
PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
#else
qspi_write32(&regs->lut[lut_base + 1], OPRND0(TX_BUFFER_SIZE) |
PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
qspi_write32(priv->flags, &regs->lut[lut_base + 1],
OPRND0(TX_BUFFER_SIZE) |
PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
#endif
qspi_write32(&regs->lut[lut_base + 2], 0);
qspi_write32(&regs->lut[lut_base + 3], 0);
qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
/* READ ID */
lut_base = SEQID_RDID * 4;
qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_RDID) |
qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDID) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(8) |
PAD1(LUT_PAD1) | INSTR1(LUT_READ));
qspi_write32(&regs->lut[lut_base + 1], 0);
qspi_write32(&regs->lut[lut_base + 2], 0);
qspi_write32(&regs->lut[lut_base + 3], 0);
qspi_write32(priv->flags, &regs->lut[lut_base + 1], 0);
qspi_write32(priv->flags, &regs->lut[lut_base + 2], 0);
qspi_write32(priv->flags, &regs->lut[lut_base + 3], 0);
/* SUB SECTOR 4K ERASE */
lut_base = SEQID_BE_4K * 4;
qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) |
qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BE_4K) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
......@@ -239,28 +297,28 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
* initialization.
*/
lut_base = SEQID_BRRD * 4;
qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_BRRD) |
qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRRD) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
PAD1(LUT_PAD1) | INSTR1(LUT_READ));
lut_base = SEQID_BRWR * 4;
qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_BRWR) |
qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_BRWR) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
lut_base = SEQID_RDEAR * 4;
qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) |
qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_RDEAR) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
PAD1(LUT_PAD1) | INSTR1(LUT_READ));
lut_base = SEQID_WREAR * 4;
qspi_write32(&regs->lut[lut_base], OPRND0(QSPI_CMD_WREAR) |
qspi_write32(priv->flags, &regs->lut[lut_base], OPRND0(QSPI_CMD_WREAR) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
PAD1(LUT_PAD1) | INSTR1(LUT_WRITE));
#endif
/* Lock the LUT */
qspi_write32(&regs->lutkey, LUT_KEY_VALUE);
qspi_write32(&regs->lckcr, QSPI_LCKCR_LOCK);
qspi_write32(priv->flags, &regs->lutkey, LUT_KEY_VALUE);
qspi_write32(priv->flags, &regs->lckcr, QSPI_LCKCR_LOCK);
}
#if defined(CONFIG_SYS_FSL_QSPI_AHB)
......@@ -270,14 +328,14 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
* the wrong data. The spec tells us reset the AHB domain and Serial Flash
* domain at the same time.
*/
static inline void qspi_ahb_invalid(struct fsl_qspi *q)
static inline void qspi_ahb_invalid(struct fsl_qspi_priv *priv)
{
struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)q->reg_base;
struct fsl_qspi_regs *regs = priv->regs;
u32 reg;
reg = qspi_read32(&regs->mcr);
reg = qspi_read32(priv->flags, &regs->mcr);
reg |= QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK;
qspi_write32(&regs->mcr, reg);
qspi_write32(priv->flags, &regs->mcr, reg);
/*
* The minimum delay : 1 AHB + 2 SFCK clocks.
......@@ -286,46 +344,48 @@ static inline void qspi_ahb_invalid(struct fsl_qspi *q)
udelay(1);
reg &= ~(QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK);
qspi_write32(&regs->mcr, reg);
qspi_write32(priv->flags, &regs->mcr, reg);
}
/* Read out the data from the AHB buffer. */
static inline void qspi_ahb_read(struct fsl_qspi *q, u8 *rxbuf, int len)
static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len)
{
struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)q->reg_base;
struct fsl_qspi_regs *regs = priv->regs;
u32 mcr_reg;
mcr_reg = qspi_read32(&regs->mcr);
mcr_reg = qspi_read32(priv->flags, &regs->mcr);
qspi_write32(&regs->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
qspi_write32(priv->flags, &regs->mcr,
QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
/* Read out the data directly from the AHB buffer. */
memcpy(rxbuf, (u8 *)(q->amba_base + q->sf_addr), len);
memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len);
qspi_write32(&regs->mcr, mcr_reg);
qspi_write32(priv->flags, &regs->mcr, mcr_reg);
}
static void qspi_enable_ddr_mode(struct fsl_qspi_regs *regs)
static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv)
{
u32 reg, reg2;
struct fsl_qspi_regs *regs = priv->regs;
reg = qspi_read32(&regs->mcr);
reg = qspi_read32(priv->flags, &regs->mcr);
/* Disable the module */
qspi_write32(&regs->mcr, reg | QSPI_MCR_MDIS_MASK);
qspi_write32(priv->flags, &regs->mcr, reg | QSPI_MCR_MDIS_MASK);
/* Set the Sampling Register for DDR */
reg2 = qspi_read32(&regs->smpr);
reg2 = qspi_read32(priv->flags, &regs->smpr);
reg2 &= ~QSPI_SMPR_DDRSMP_MASK;
reg2 |= (2 << QSPI_SMPR_DDRSMP_SHIFT);
qspi_write32(&regs->smpr, reg2);
qspi_write32(priv->flags, &regs->smpr, reg2);
/* Enable the module again (enable the DDR too) */
reg |= QSPI_MCR_DDR_EN_MASK;
/* Enable bit 29 for imx6sx */
reg |= (1 << 29);
qspi_write32(&regs->mcr, reg);
qspi_write32(priv->flags, &regs->mcr, reg);
}
/*
......@@ -341,180 +401,103 @@ static void qspi_enable_ddr_mode(struct fsl_qspi_regs *regs)
* causes the controller to clear the buffer, and use the sequence pointed
* by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
*/
static void qspi_init_ahb_read(struct fsl_qspi_regs *regs)
static void qspi_init_ahb_read(struct fsl_qspi_priv *priv)
{
struct fsl_qspi_regs *regs = priv->regs;
/* AHB configuration for access buffer 0/1/2 .*/
qspi_write32(&regs->buf0cr, QSPI_BUFXCR_INVALID_MSTRID);
qspi_write32(&regs->buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
qspi_write32(&regs->buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
qspi_write32(&regs->buf3cr, QSPI_BUF3CR_ALLMST_MASK |
qspi_write32(priv->flags, &regs->buf0cr, QSPI_BUFXCR_INVALID_MSTRID);
qspi_write32(priv->flags, &regs->buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
qspi_write32(priv->flags, &regs->buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
qspi_write32(priv->flags, &regs->buf3cr, QSPI_BUF3CR_ALLMST_MASK |
(0x80 << QSPI_BUF3CR_ADATSZ_SHIFT));
/* We only use the buffer3 */
qspi_write32(&regs->buf0ind, 0);
qspi_write32(&regs->buf1ind, 0);
qspi_write32(&regs->buf2ind, 0);
qspi_write32(priv->flags, &regs->buf0ind, 0);
qspi_write32(priv->flags, &regs->buf1ind, 0);
qspi_write32(priv->flags, &regs->buf2ind, 0);
/*
* Set the default lut sequence for AHB Read.
* Parallel mode is disabled.
*/
qspi_write32(&regs->bfgencr,
qspi_write32(priv->flags, &regs->bfgencr,
SEQID_FAST_READ << QSPI_BFGENCR_SEQID_SHIFT);
/*Enable DDR Mode*/
qspi_enable_ddr_mode(regs);
qspi_enable_ddr_mode(priv);
}
#endif
void spi_init()
{
/* do nothing */
}
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
struct fsl_qspi *qspi;
struct fsl_qspi_regs *regs;
u32 smpr_val;
u32 total_size;
if (bus >= ARRAY_SIZE(spi_bases))
return NULL;
if (cs >= FSL_QSPI_FLASH_NUM)
return NULL;
qspi = spi_alloc_slave(struct fsl_qspi, bus, cs);
if (!qspi)
return NULL;
qspi->reg_base = spi_bases[bus];
/*
* According cs, use different amba_base to choose the
* corresponding flash devices.
*
* If not, only one flash device is used even if passing
* different cs using `sf probe`
*/
qspi->amba_base = amba_bases[bus] + cs * FSL_QSPI_FLASH_SIZE;
qspi->slave.max_write_size = TX_BUFFER_SIZE;
regs = (struct fsl_qspi_regs *)qspi->reg_base;
qspi_write32(&regs->mcr, QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK);
smpr_val = qspi_read32(&regs->smpr);
qspi_write32(&regs->smpr, smpr_val & ~(QSPI_SMPR_FSDLY_MASK |
QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK));
qspi_write32(&regs->mcr, QSPI_MCR_RESERVED_MASK);
total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM;
/*
* Any read access to non-implemented addresses will provide
* undefined results.
*
* In case single die flash devices, TOP_ADDR_MEMA2 and
* TOP_ADDR_MEMB2 should be initialized/programmed to
* TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
* setting the size of these devices to 0. This would ensure
* that the complete memory map is assigned to only one flash device.
*/
qspi_write32(&regs->sfa1ad, FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
qspi_write32(&regs->sfa2ad, FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
qspi_write32(&regs->sfb1ad, total_size | amba_bases[bus]);
qspi_write32(&regs->sfb2ad, total_size | amba_bases[bus]);
qspi_set_lut(qspi);
smpr_val = qspi_read32(&regs->smpr);
smpr_val &= ~QSPI_SMPR_DDRSMP_MASK;
qspi_write32(&regs->smpr, smpr_val);
qspi_write32(&regs->mcr, QSPI_MCR_RESERVED_MASK);
#ifdef CONFIG_SYS_FSL_QSPI_AHB
qspi_init_ahb_read(regs);
#endif
return &qspi->slave;
}
void spi_free_slave(struct spi_slave *slave)
{
struct fsl_qspi *qspi = to_qspi_spi(slave);
free(qspi);
}
int spi_claim_bus(struct spi_slave *slave)
{
return 0;
}
#ifdef CONFIG_SPI_FLASH_BAR
/* Bank register read/write, EAR register read/write */
static void qspi_op_rdbank(struct fsl_qspi *qspi, u8 *rxbuf, u32 len)
static void qspi_op_rdbank(struct fsl_qspi_priv *priv, u8 *rxbuf, u32 len)
{
struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi->reg_base;
struct fsl_qspi_regs *regs = priv->regs;
u32 reg, mcr_reg, data, seqid;
mcr_reg = qspi_read32(&regs->mcr);
qspi_write32(&regs->mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
mcr_reg = qspi_read32(priv->flags, &regs->mcr);
qspi_write32(priv->flags, &regs->mcr,
QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
qspi_write32(&regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
qspi_write32(priv->flags, &regs->rbct, QSPI_RBCT_RXBRD_USEIPS);
qspi_write32(&regs->sfar, qspi->amba_base);
qspi_write32(priv->flags, &regs->sfar, priv->cur_amba_base);
if (qspi->cur_seqid == QSPI_CMD_BRRD)
if (priv->cur_seqid == QSPI_CMD_BRRD)
seqid = SEQID_BRRD;
else
seqid = SEQID_RDEAR;
qspi_write32(&regs->ipcr, (seqid << QSPI_IPCR_SEQID_SHIFT) | len);
qspi_write32(priv->flags, &regs->ipcr,
(seqid << QSPI_IPCR_SEQID_SHIFT) | len);
/* Wait previous command complete */
while (qspi_read32(&regs->sr) & QSPI_SR_BUSY_MASK)
while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)
;