Commit 5bf0f7f6 authored by Bin Meng's avatar Bin Meng Committed by Simon Glass

x86: galileo: Add PCIe root port IRQ routing

Now we have enabled PCIe root port on Quark SoC, add its PIRQ
routing information in the device tree as well.
Signed-off-by: default avatarBin Meng <bmeng.cn@gmail.com>
Acked-by: default avatarSimon Glass <sjg@chromium.org>
parent 554778c2
......@@ -92,6 +92,18 @@
PCI_BDF(0, 21, 0) INTA PIRQE
PCI_BDF(0, 21, 1) INTB PIRQF
PCI_BDF(0, 21, 2) INTC PIRQG
PCI_BDF(0, 23, 0) INTA PIRQA
PCI_BDF(0, 23, 1) INTB PIRQB
/* PCIe root ports downstream interrupts */
PCI_BDF(1, 0, 0) INTA PIRQA
PCI_BDF(1, 0, 0) INTB PIRQB
PCI_BDF(1, 0, 0) INTC PIRQC
PCI_BDF(1, 0, 0) INTD PIRQD
PCI_BDF(2, 0, 0) INTA PIRQB
PCI_BDF(2, 0, 0) INTB PIRQC
PCI_BDF(2, 0, 0) INTC PIRQD
PCI_BDF(2, 0, 0) INTD PIRQA
>;
};
};
......
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