Commit 5ffa88ec authored by Liu Gang's avatar Liu Gang Committed by Andy Fleming
Browse files

powerpc/corenet_ds: Master module for boot from SRIO



For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.

The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:

master:
	1. NOR flash for its own u-boot image, ucode and ENV space.
	2. Slave's u-boot image in master NOR flash.
	3. Normally boot from local NOR flash.
	4. Configure SRIO switch system if needed.
slave:
	1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
	2. Boot location should be set to SRIO1 or SRIO2 by RCW.
	3. RCW should configure the SerDes, SRIO interfaces correctly.
	4. Slave must be powered on after master's boot.

For the master module, need to finish these processes:
	1. Initialize the SRIO port and address space.
	2. Set inbound SRIO windows covered slave's u-boot image stored in
	   master's NOR flash.
	3. Master's u-boot image should be generated specifically by
	   make xxxx_SRIOBOOT_MASTER_config
	4. Master must boot first, and then slave can be powered on.
Signed-off-by: default avatarLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: default avatarShaohui Xie <Shaohui.Xie@freescale.com>
parent 006f37f6
......@@ -37,6 +37,7 @@
#include <asm/mmu.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_srio.h>
#include <linux/compiler.h>
#include "mp.h"
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
......@@ -48,8 +49,6 @@
DECLARE_GLOBAL_DATA_PTR;
extern void srio_init(void);
#ifdef CONFIG_QE
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
......@@ -443,6 +442,9 @@ skip_l2:
#ifdef CONFIG_SYS_SRIO
srio_init();
#ifdef CONFIG_SRIOBOOT_MASTER
srio_boot_master();
#endif
#endif
#if defined(CONFIG_MP)
......
......@@ -21,6 +21,10 @@
#include <config.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_srio.h>
#define SRIO_PORT_ACCEPT_ALL 0x10000001
#define SRIO_IB_ATMU_AR 0x80f55000
#if defined(CONFIG_FSL_CORENET)
#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
......@@ -84,3 +88,50 @@ void srio_init(void)
setbits_be32(&gur->devdisr, _DEVDISR_RMU);
}
}
#ifdef CONFIG_SRIOBOOT_MASTER
void srio_boot_master(void)
{
struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
/* set port accept-all */
out_be32((void *)&srio->impl.port[CONFIG_SRIOBOOT_MASTER_PORT].ptaacr,
SRIO_PORT_ACCEPT_ALL);
debug("SRIOBOOT - MASTER: Master port [ %d ] for srio boot.\n",
CONFIG_SRIOBOOT_MASTER_PORT);
/* configure inbound window5 for slave's u-boot image */
debug("SRIOBOOT - MASTER: Inbound window 5 for slave's image; "
"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1,
(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1,
CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwtar,
CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 >> 12);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwbar,
CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 >> 12);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[0].riwar,
SRIO_IB_ATMU_AR
| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE));
/* configure inbound window4 for slave's u-boot image */
debug("SRIOBOOT - MASTER: Inbound window 4 for slave's image; "
"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2,
(u64)CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2,
CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwtar,
CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 >> 12);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwbar,
CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 >> 12);
out_be32((void *)&srio->atmu
.port[CONFIG_SRIOBOOT_MASTER_PORT].inbw[1].riwar,
SRIO_IB_ATMU_AR
| atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE));
}
#endif
/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _FSL_SRIO_H_
#define _FSL_SRIO_H_
enum atmu_size {
ATMU_SIZE_4K = 0xb,
ATMU_SIZE_8K,
ATMU_SIZE_16K,
ATMU_SIZE_32K,
ATMU_SIZE_64K,
ATMU_SIZE_128K,
ATMU_SIZE_256K,
ATMU_SIZE_512K,
ATMU_SIZE_1M,
ATMU_SIZE_2M,
ATMU_SIZE_4M,
ATMU_SIZE_8M,
ATMU_SIZE_16M,
ATMU_SIZE_32M,
ATMU_SIZE_64M,
ATMU_SIZE_128M,
ATMU_SIZE_256M,
ATMU_SIZE_512M,
ATMU_SIZE_1G,
ATMU_SIZE_2G,
ATMU_SIZE_4G,
ATMU_SIZE_8G,
ATMU_SIZE_16G,
ATMU_SIZE_32G,
ATMU_SIZE_64G,
};
#define atmu_size_mask(sz) (__ilog2_u64(sz) - 1)
#define atmu_size_bytes(x) (1ULL << ((x & 0x3f) + 1))
extern void srio_init(void);
#ifdef CONFIG_SRIOBOOT_MASTER
extern void srio_boot_master(void);
#endif
#endif
......@@ -2507,6 +2507,7 @@ struct ccsr_rman {
#define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000
#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
#define CONFIG_SYS_FSL_CPC_ADDR \
(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
......@@ -2580,6 +2581,8 @@ struct ccsr_rman {
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
#define CONFIG_SYS_FSL_FM2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
#define CONFIG_SYS_FSL_SRIO_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
#define CONFIG_SYS_PCI1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
......
......@@ -751,6 +751,7 @@ P3041DS_NAND powerpc mpc85xx corenet_ds freescale -
P3041DS_SDCARD powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
P3041DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P3041DS:SECURE_BOOT
P3041DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
P3041DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P3041DS:SRIOBOOT_MASTER
P3060QDS powerpc mpc85xx p3060qds freescale
P3060QDS_NAND powerpc mpc85xx p3060qds freescale - P3060QDS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
P3060QDS_SECURE_BOOT powerpc mpc85xx p3060qds freescale - P3060QDS:SECURE_BOOT
......@@ -758,11 +759,13 @@ P4080DS powerpc mpc85xx corenet_ds freesca
P4080DS_SDCARD powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
P4080DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P4080DS:SECURE_BOOT
P4080DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
P4080DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P4080DS:SRIOBOOT_MASTER
P5020DS powerpc mpc85xx corenet_ds freescale
P5020DS_NAND powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
P5020DS_SDCARD powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
P5020DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SECURE_BOOT
P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
P5020DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P5020DS:SRIOBOOT_MASTER
stxgp3 powerpc mpc85xx stxgp3 stx
stxssa powerpc mpc85xx stxssa stx - stxssa
stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M
......
......@@ -374,6 +374,24 @@
#endif
#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
/*
* SRIOBOOT - MASTER
*/
#ifdef CONFIG_SRIOBOOT_MASTER
/* master port for srioboot*/
#define CONFIG_SRIOBOOT_MASTER_PORT 0
/* #define CONFIG_SRIOBOOT_MASTER_PORT 1 */
/*
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
#define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 0xfef080000ull
#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 0xfff80000ull
#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE 0x80000 /* 512K */
#define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 0xfef080000ull
#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 0x3fff80000ull
#endif
/*
* eSPI - Enhanced SPI
*/
......
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