Fix coding style issues; update CHANGELOG.

Signed-off-by: Wolfgang Denk <wd@denx.de>

MAINTAINERS

@@ -634,7 +634,7 @@ Haavard Skinnemoen <hskinnemoen@atmel.com>
 	ATSTK1002		AT32AP7000
 	ATSTK1003		AT32AP7001
 	ATSTK1004		AT32AP7002
- 
+
 #########################################################################
 # SuperH Systems:							#
 #									#

board/ms7722se/Makefile

 #
 # Copyright (C) 2007
 # Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-#     
+#
 # Copyright (C) 2007
 # Kenati Technologies, Inc.
 #

board/ms7722se/config.mk

@@ -29,4 +29,3 @@
 #
 
 TEXT_BASE = 0x8FFC0000
-

board/ms7722se/lowlevel_init.S

 /*
  * Copyright (C) 2007
  * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *    
+ *
  * Copyright (C) 2007
  * Kenati Technologies, Inc.
  *
@@ -52,19 +52,19 @@ lowlevel_init:
 	mov.l	r0, @r1
 
 	mov.l	MSTPCR0_A, r1	! Address of Power Control Register 0
-	mov.l	MSTPCR0_D, r0	! 
+	mov.l	MSTPCR0_D, r0	!
 	mov.l	r0, @r1
 
 	mov.l	MSTPCR2_A, r1	! Address of Power Control Register 2
-	mov.l	MSTPCR2_D, r0	! 
+	mov.l	MSTPCR2_D, r0	!
 	mov.l	r0, @r1
 
-	mov.l	SBSCR_A, r1	! 
-	mov.w	SBSCR_D, r0	! 
+	mov.l	SBSCR_A, r1	!
+	mov.w	SBSCR_D, r0	!
 	mov.w	r0, @r1
 
-	mov.l	PSCR_A, r1	! 
-	mov.w	PSCR_D, r0	! 
+	mov.l	PSCR_A, r1	!
+	mov.w	PSCR_D, r0	!
 	mov.w	r0, @r1
 
 !	mov.l	RWTCSR_A, r1	! 0xA4520004 (Watchdog Control / Status Register)
@@ -80,7 +80,7 @@ lowlevel_init:
 	mov.w	r0, @r1
 
 	mov.l	FRQCR_A, r1		! 0xA4150000 Frequency control register
-	mov.l	FRQCR_D, r0	! 
+	mov.l	FRQCR_D, r0	!
 	mov.l	r0, @r1
 
 	mov.l	CCR_A, r1		! Address of Cache Control Register
@@ -200,11 +200,9 @@ bsc_init:
 	rts
 	mov	#0, r0
 
-
-
 	.align	2
 
-CCR_A:		.long	CCR			
+CCR_A:		.long	CCR
 MMUCR_A:	.long	MMUCR
 MSTPCR0_A:	.long	MSTPCR0
 MSTPCR2_A:	.long	MSTPCR2
@@ -223,7 +221,7 @@ FRQCR_D:	.long	0x07022538
 
 PSELA_A:	.long   0xa405014E
 PSELA_D:	.word   0x0A10
-        .align 2
+	.align 2
 
 DRVCR_A:	.long   0xa405018A
 DRVCR_D:	.word   0x0554

board/ms7722se/ms7722se.c

@@ -4,7 +4,7 @@
  *
  * Copyright (C) 2007
  * Kenati Technologies, Inc.
- * 
+ *
  * board/ms7722se/ms7722se.c
  *
  * This program is free software; you can redistribute it and/or
@@ -57,4 +57,3 @@ void led_set_state (unsigned short value)
 {
 	*((volatile unsigned short *) LED_BASE) = (value & 0xFF);
 }
-

board/ms7722se/u-boot.lds

@@ -32,19 +32,19 @@ SECTIONS
 	   Although size of SDRAM can be either 16 or 32 MBytes,
 	   we assume 16 MBytes (ie ignore upper half if the full
 	   32 MBytes is present).
-	   
+
 	   NOTE: This address must match with the definition of
 	   TEXT_BASE in config.mk (in this directory).
-	   
+
 	*/
 	. = 0x8C000000 + (64*1024*1024) - (256*1024);
-	
+
 	PROVIDE (reloc_dst = .);
 
 	PROVIDE (_ftext = .);
 	PROVIDE (_fcode = .);
 	PROVIDE (_start = .);
-	
+
 	.text :
 	{
 		cpu/sh4/start.o		(.text)
@@ -89,7 +89,7 @@ SECTIONS
 	}
 	PROVIDE (__u_boot_cmd_end = .);
 
-	PROVIDE (reloc_dst_end = .); 
+	PROVIDE (reloc_dst_end = .);
 	/* _reloc_dst_end = .; */
 
 	PROVIDE (bss_start = .);
@@ -103,4 +103,3 @@ SECTIONS
 
 	PROVIDE (_end = .);
 }
-

board/ms7750se/lowlevel_init.S

@@ -2,8 +2,8 @@
  modified from SH-IPL+g
  Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting.
 
- Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R 
- 
+ Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R
+
  Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org>
 
  * See file CREDITS for list of people who contributed to this
@@ -102,7 +102,7 @@ init_bsc:
 	mov	#0,r0
 	mov.b	r0,@r1
 
-	! Do you need PCMCIA setting?	
+	! Do you need PCMCIA setting?
 	! If so, please add the lines here...
 
 	mov.l	RTCNT_A,r1	/* RTCNT Address */
@@ -165,7 +165,7 @@ WCR2_A:		.long	WCR2
 WCR2_D:		.long	WCR2_D_VALUE	/* Per-area access and burst wait states */
 WCR3_A:		.long	WCR3
 WCR3_D:		.long	WCR3_D_VALUE	/* Address setup and data hold cycles */
-RTCSR_A:	.long	RTCSR	
+RTCSR_A:	.long	RTCSR
 RTCSR_D:	.long	0xA518		/* RTCSR Write Code A5h Data 18h */
 RTCNT_A:	.long	RTCNT
 RTCNT_D:	.long	0xA500		/* RTCNT Write Code A5h Data 00h */
@@ -177,4 +177,3 @@ MCR_D1:		.long	MCR_D1_VALUE
 MCR_D2:		.long	MCR_D2_VALUE
 RFCR_A:		.long	RFCR
 RFCR_D:		.long	0xA400		/* RFCR Write Code A4h Data 00h */
-

board/ms7750se/ms7750se.c

 /*
- * Copyright (C) 2007 
+ * Copyright (C) 2007
  * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
  *
  * See file CREDITS for list of people who contributed to this

board/ms7750se/u-boot.lds

@@ -32,19 +32,19 @@ SECTIONS
 	   Although size of SDRAM can be either 16 or 32 MBytes,
 	   we assume 16 MBytes (ie ignore upper half if the full
 	   32 MBytes is present).
-	   
+
 	   NOTE: This address must match with the definition of
 	   TEXT_BASE in config.mk (in this directory).
-	   
+
 	*/
 	. = 0x8C000000 + (64*1024*1024) - (256*1024);
-	
+
 	PROVIDE (reloc_dst = .);
 
 	PROVIDE (_ftext = .);
 	PROVIDE (_fcode = .);
 	PROVIDE (_start = .);
-	
+
 	.text :
 	{
 		cpu/sh4/start.o		(.text)
@@ -89,7 +89,7 @@ SECTIONS
 	}
 	PROVIDE (__u_boot_cmd_end = .);
 
-	PROVIDE (reloc_dst_end = .); 
+	PROVIDE (reloc_dst_end = .);
 	/* _reloc_dst_end = .; */
 
 	PROVIDE (bss_start = .);
@@ -103,4 +103,3 @@ SECTIONS
 
 	PROVIDE (_end = .);
 }
-

cpu/sh4/cache.c

@@ -30,36 +30,36 @@
  * Jump to P2 area.
  * When handling TLB or caches, we need to do it from P2 area.
  */
-#define jump_to_P2()                    \
-  do {                                    \
+#define jump_to_P2()			\
+  do {					\
     unsigned long __dummy;		\
-    __asm__ __volatile__(			\
-                "mov.l  1f, %0\n\t"     \
-                "or     %1, %0\n\t"     \
-                "jmp    @%0\n\t"        \
-                " nop\n\t"              \
-                ".balign 4\n"           \
-                "1:     .long 2f\n"     \
-                "2:"                    \
-                : "=&r" (__dummy)       \
-                : "r" (0x20000000));    \
+    __asm__ __volatile__(		\
+		"mov.l	1f, %0\n\t"	\
+		"or	%1, %0\n\t"	\
+		"jmp	@%0\n\t"	\
+		" nop\n\t"		\
+		".balign 4\n"		\
+		"1:	.long 2f\n"	\
+		"2:"			\
+		: "=&r" (__dummy)	\
+		: "r" (0x20000000));	\
   } while (0)
 
 /*
  * Back to P1 area.
  */
-#define back_to_P1()                                    \
-  do {                                                    \
-    unsigned long __dummy;                          \
-    __asm__ __volatile__(                           \
-                "nop;nop;nop;nop;nop;nop;nop\n\t"       \
-                "mov.l  1f, %0\n\t"                     \
-                "jmp    @%0\n\t"                        \
-                " nop\n\t"                              \
-                ".balign 4\n"                           \
-                "1:     .long 2f\n"                     \
-                "2:"                                    \
-                : "=&r" (__dummy));                     \
+#define back_to_P1()					\
+  do {							\
+    unsigned long __dummy;				\
+    __asm__ __volatile__(				\
+		"nop;nop;nop;nop;nop;nop;nop\n\t"	\
+		"mov.l	1f, %0\n\t"			\
+		"jmp	@%0\n\t"			\
+		" nop\n\t"				\
+		".balign 4\n"				\
+		"1:	.long 2f\n"			\
+		"2:"					\
+		: "=&r" (__dummy));			\
   } while (0)
 
 #define CACHE_VALID       1

cpu/sh4/config.mk

@@ -4,7 +4,7 @@
 #
 # (C) Copyright 2007
 # Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-#   
+#
 # See file CREDITS for list of people who contributed to this
 # project.
 #

cpu/sh4/cpu.c

@@ -66,7 +66,7 @@ void icache_disable (void)
 
 int icache_status (void)
 {
-	return 0; 
+	return 0;
 }
 
 void dcache_enable (void)

cpu/sh4/interrupts.c

@@ -25,7 +25,7 @@
 
 int interrupt_init (void)
 {
-	return 0; 
+	return 0;
 }
 
 void enable_interrupts (void)
@@ -33,7 +33,6 @@ void enable_interrupts (void)
 
 }
 
-int disable_interrupts (void){ 
-	return 0; 
+int disable_interrupts (void){
+	return 0;
 }
-

cpu/sh4/start.S

@@ -33,21 +33,21 @@ _start:
 	bsr	1f
 	nop
 1:	sts	pr, r5
-	mov.l	._reloc_dst, r4	
-	add	#(_start-1b), r5	
-	mov.l	._reloc_dst_end, r6	
+	mov.l	._reloc_dst, r4
+	add	#(_start-1b), r5
+	mov.l	._reloc_dst_end, r6
 
 2:	mov.l	@r5+, r1
 	mov.l	r1, @r4
 	add	#4, r4
 	cmp/hs	r6, r4
 	bf	2b
-	
-	mov.l	._bss_start, r4	
-	mov.l	._bss_end, r5		
+
+	mov.l	._bss_start, r4
+	mov.l	._bss_end, r5
 	mov	#0, r1
 
-3:	mov.l	r1, @r4			/* bss clear */	
+3:	mov.l	r1, @r4			/* bss clear */
 	add	#4, r4
 	cmp/hs	r5, r4
 	bf	3b
@@ -56,8 +56,8 @@ _start:
 	mov.l	._stack_init, r15	/* stack */
 
 	mov.l	._sh_generic_init, r0
-	jsr	@r0			
-	nop				
+	jsr	@r0
+	nop
 
 loop:
 	bra	loop
@@ -72,4 +72,3 @@ loop:
 ._gd_init:		.long	(_start - CFG_GBL_DATA_SIZE)
 ._stack_init:		.long	(_start - CFG_GBL_DATA_SIZE - CFG_MALLOC_LEN - 16)
 ._sh_generic_init:	.long	sh_generic_init
-

cpu/sh4/watchdog.c

@@ -32,12 +32,12 @@ static void cnt_write (unsigned char value){
 	while (csr_read() & (1 << 5)) {
 		/* delay */
 	}
-	*((volatile unsigned short *)(WDT_BASE + 0x00)) 
+	*((volatile unsigned short *)(WDT_BASE + 0x00))
 		= ((unsigned short) value) | 0x5A00;
 }
 
 static void csr_write (unsigned char value){
-	*((volatile unsigned short *)(WDT_BASE + 0x04)) 
+	*((volatile unsigned short *)(WDT_BASE + 0x04))
 		= ((unsigned short) value) | 0xA500;
 }
 
@@ -48,5 +48,3 @@ void reset_cpu (unsigned long ignored)
 {
 	while(1);
 }
-
-

doc/README.marubun-pcmcia

 
 U-Boot MARUBUN MR-SHPC-01 PCMCIA controller driver
 	Last update 21/11/2007 by Nobuhiro Iwamatsu
-	
+
 ========================================================================================
 
-0. What's this? 
+0. What's this?
     This driver supports MARUBUN MR-SHPC-01.
 	url: http://www.marubun.co.jp/product/semicon/devices/qgc18e0000002n2z.html
 	(Sorry Japanese only.)
 
-    This chip is used with SuperH well, and adopted by the 
-    reference board. 
+    This chip is used with SuperH well, and adopted by the
+    reference board.
 	ex. * MS7750SE01
 		* MS7722SE01
-		* other 
-		
+		* other
+
     This chip doesn't support CardBus.
 
-1. base source code 
+1. base source code
     The code is based on sources from the Linux kernel
-    	( arch/sh/kernel/cf-enabler.c ). 
+    	( arch/sh/kernel/cf-enabler.c ).
 
-2. How to use 
+2. How to use
     The options you have to specify in the config file are (with the
     value for my board as an example):
 
     * CONFIG_MARUBUN_PCCARD
 	If you want to use this device driver, should define CONFIG_MARUBUN_PCCARD.
 	ex. 	#define CONFIG_MARUBUN_PCCARD
-		
+
     * CONFIG_PCMCIA_SLOT_A
     	Most devices have only one slot. You should define CONFIG_PCMCIA_SLOT_A .
 	ex.	#define CONFIG_PCMCIA_SLOT_A    1
 
     * CFG_MARUBUN_MRSHPC
     	This is MR-SHPC-01 PCMCIA controler base address.
-	You should do the setting matched to your environment. 
-	ex.  #define CFG_MARUBUN_MRSHPC 0xb03fffe0 
+	You should do the setting matched to your environment.
+	ex.  #define CFG_MARUBUN_MRSHPC 0xb03fffe0
 	     ( for MS7722SE01 environment )
 
     * CFG_MARUBUN_MW1
 	This is MR-SHPC-01 memory window base address.
-	You should do the setting matched to your environment. 
+	You should do the setting matched to your environment.
 	ex. #define CFG_MARUBUN_MW1 0xb0400000
 	     ( for MS7722SE01 environment )
-	
+
     * CFG_MARUBUN_MW1
 	This is MR-SHPC-01 attribute window base address.
-	You should do the setting matched to your environment. 
+	You should do the setting matched to your environment.
 	ex. #define CFG_MARUBUN_MW2 0xb0500000
 	     ( for MS7722SE01 environment )
-	     
+
     * CFG_MARUBUN_MW1
 	This is MR-SHPC-01 I/O window base address.
-	You should do the setting matched to your environment. 
+	You should do the setting matched to your environment.
 	ex. #define CFG_MARUBUN_IO  0xb0600000
 	     ( for MS7722SE01 environment )
 

doc/README.sh

 
-U-Boot for Renesas SuperH 
+U-Boot for Renesas SuperH
 	Last update 08/10/2007 by Nobuhiro Iwamatsu
 
 ================================================================================
@@ -9,10 +9,10 @@ U-Boot for Renesas SuperH
 
 ================================================================================
 1. Overview
-	SuperH has an original boot loader. However, source code is dirty, and 
+	SuperH has an original boot loader. However, source code is dirty, and
 	maintenance is not done.
-	To improve sharing and the maintenance of the code, Nobuhiro Iwamatsu 
-	started the porting to u-boot in 2007. 
+	To improve sharing and the maintenance of the code, Nobuhiro Iwamatsu
+	started the porting to u-boot in 2007.
 
 ================================================================================
 2. Supported CPUs
@@ -33,13 +33,13 @@ U-Boot for Renesas SuperH
 
 	** README **
 		In SuperH, S-record and binary of made u-boot work on the memory.
-		When u-boot is written in the flash, it is necessary to change the 
-		address by using 'objcopy'.  
+		When u-boot is written in the flash, it is necessary to change the
+		address by using 'objcopy'.
 		ex) shX-linux-objcopy -Ibinary -Osrec u-boot.bin u-boot.flash.srec
-	
+
 ================================================================================
 4. Compiler
-	You can use the following of u-boot to compile. 
+	You can use the following of u-boot to compile.
 		- SuperH Linux Open site
 			http://www.superh-linux.org/
 		- KPIT GNU tools
@@ -52,11 +52,10 @@ U-Boot for Renesas SuperH
 			- SH7710/SH7712 (SH3)
 			- SH7780(SH4)
 			- SH7785(SH4)
-		
+
 		5.2. Boards
 			- Many boards ;-)
 
 ================================================================================
 Copyright (c) 2007
     Nobuhiro Iwamatsu <iwamatsu@nigaur.org>
-

drivers/pcmcia/marubun_pcmcia.c

@@ -17,8 +17,8 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
- *              
- */ 
+ *
+ */
 
 #include <common.h>
 #include <config.h>
@@ -34,7 +34,7 @@
 #endif
 
 #if	defined(CONFIG_PCMCIA)  \
-	        && (defined(CONFIG_MARUBUN_PCCARD)) 
+	        && (defined(CONFIG_MARUBUN_PCCARD))
 
 /* MR-SHPC-01 register */
 #define MRSHPC_MODE   	(CFG_MARUBUN_MRSHPC + 4)
@@ -79,14 +79,14 @@ int pcmcia_on (void)
 		outw(0x0b00,MRSHPC_MW0CR2); /* common mode & bus width 16bit SWAP = 1 */
 	else
 		outw(0x0300,MRSHPC_MW0CR2); /* common mode & bus width 16bit SWAP = 0 */
-	
+
 	/* attribute window open */
 	outw(0x8a85,MRSHPC_MW1CR1); /* window 0xb8500000 */
 	if ((inw(MRSHPC_CSR) & 0x4000) != 0)
 		outw(0x0a00,MRSHPC_MW1CR2); /* attribute mode & bus width 16bit SWAP = 1 */
 	else
 		outw(0x0200,MRSHPC_MW1CR2); /* attribute mode & bus width 16bit SWAP = 0 */
-	
+
 	/* I/O window open */
 	outw(0x8a86,MRSHPC_IOWCR1); /* I/O window 0xb8600000 */
 	outw(0x0008,MRSHPC_CDCR);   /* I/O card mode */
@@ -94,7 +94,7 @@ int pcmcia_on (void)
 		outw(0x0a00,MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1 */
 	else
 		outw(0x0200,MRSHPC_IOWCR2); /* bus width 16bit SWAP = 0 */
-	
+
 	outw(0x0000,MRSHPC_ISR);
 	outw(0x2000,MRSHPC_ICR);
 	outb(0x00,(CFG_MARUBUN_MW2 + 0x206));

drivers/serial/serial_sh.c

 /*
  * SuperH SCIF device driver.
  * Copyright (c) 2007 Nobuhiro Iwamatsu
- * 
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
@@ -31,7 +31,7 @@
 #endif
 
 #define SCSMR 	(vu_short *)(SCIF_BASE + 0x0)
-#define SCBRR 	(vu_char  *)(SCIF_BASE + 0x4) 
+#define SCBRR 	(vu_char  *)(SCIF_BASE + 0x4)
 #define SCSCR 	(vu_short *)(SCIF_BASE + 0x8)
 #define SCFTDR 	(vu_char  *)(SCIF_BASE + 0xC)
 #define SCFSR 	(vu_short *)(SCIF_BASE + 0x10)
@@ -51,7 +51,7 @@
 #endif
 
 #define SCR_RE 		(1 << 4)
-#define SCR_TE 		(1 << 5) 
+#define SCR_TE 		(1 << 5)
 #define FCR_RFRST	(1 << 1) /* RFCL */
 #define FCR_TFRST	(1 << 2) /* TFCL */
 #define FSR_DR   	(1 << 0)
@@ -69,7 +69,7 @@ void serial_setbrg (void)
 	DECLARE_GLOBAL_DATA_PTR;
 	int divisor = gd->baudrate * 32;
 
-	*SCBRR = (CONFIG_SYS_CLK_FREQ + (divisor / 2)) / 
+	*SCBRR = (CONFIG_SYS_CLK_FREQ + (divisor / 2)) /
 						(gd->baudrate * 32) - 1;
 }
 

examples/stubs.c

@@ -132,7 +132,7 @@ gd_t *global_data;
  */
 #define EXPORT_FUNC(x)			\
 	asm volatile (			\
-"       .globl _" #x "\n_"		\
+"	.globl _" #x "\n_"		\
 #x ":\n"				\
 "	P0 = [P5 + %0]\n"		\
 "	P0 = [P0 + %1]\n"		\
@@ -155,17 +155,17 @@ gd_t *global_data;
 /*
  * r13 holds the pointer to the global_data. r1 is a call clobbered.
  */
-#define EXPORT_FUNC(x)                  \
-        asm volatile (                  \
-		"       .align  2\n"                    \
-		"       .globl " #x "\n"                \
-		#x ":\n"                                \
-		"       mov     r13, r1\n"              \
-		"       add     %0, r1\n"               \
-		"       add     %1, r1\n"               \
-		"       jmp     @r1\n"                  \
-		"       nop\n"                          \
-		"       nop\n"                          \
+#define EXPORT_FUNC(x)					\
+	asm volatile (					\
+		"	.align	2\n"			\
+		"	.globl " #x "\n"		\
+		#x ":\n"				\
+		"	mov	r13, r1\n"		\
+		"	add	%0, r1\n"		\
+		"	add	%1, r1\n"		\
+		"	jmp	@r1\n"			\
+		"	nop\n"				\
+		"	nop\n"				\
 		: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r1");
 #else
 #error stubs definition missing for this architecture

include/asm-sh/bitops.h

@@ -2,7 +2,6 @@
 #define __ASM_SH_BITOPS_H
 
 #ifdef __KERNEL__
-//#include <asm/system.h>