Commit 62d206dc authored by Committed by Jagannadha Sutradharudu TekiBrowse files
armv7: hw_data: change clock divider setting.
Clock requirement for qspi clk is 192 Mhz. According to the below formulae, f dpll = f ref * 2 * m /(n + 1) clockoutx2_Hmn = f dpll / (hmn+ 1) fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz For clockoutx2_Hmn to be 768, hmn + 1 should be 4. Signed-off-by: Sourav Poddar <email@example.com> Reviewed-by: Jagannadha Sutradharudu Teki <firstname.lastname@example.org>
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