Commit 62ddcf05 authored by Heiko Schocher's avatar Heiko Schocher Committed by Wolfgang Denk
Browse files

mpc832x: add support for the mpc8321 based suvd3 board



- serial console on UART1
- Ethernet RMII over UCC4
- PHY SMSC LAN8700
- 64MB Flash
- 128 MB DDR2 RAM
- I2C
- bootcount

This board is similiar to the kmeter1 (8360) board,
so common config options are extracted into the
include/configs/km83xx-common.h file.
Signed-off-by: default avatarHeiko Schocher <hs@denx.de>
Acked-by: default avatarKim Phillips <kim.phillips@freescale.com>
cc: Kim Phillips <kim.phillips@freescale.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
parent de3ad13d
......@@ -433,6 +433,7 @@ Heiko Schocher <hs@denx.de>
municse MPC5200
sc3 PPC405GP
suen3 ARM926EJS (Kirkwood SoC)
suvd3 MPC8321
uc101 MPC5200
ve8313 MPC8313
......
......@@ -32,7 +32,8 @@ extern void ft_qe_setup(void *blob);
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_BOOTCOUNT_LIMIT) && defined(CONFIG_MPC8360)
#if defined(CONFIG_BOOTCOUNT_LIMIT) && \
(defined(CONFIG_QE))
#include <asm/immap_qe.h>
void fdt_fixup_muram (void *blob)
......
......@@ -51,7 +51,7 @@
#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR)
#endif /* defined(CONFIG_MPC8260) */
#if defined(CONFIG_MPC8360)
#if defined(CONFIG_QE)
#include <asm/immap_qe.h>
#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + 0x110000 + \
......
......@@ -29,6 +29,7 @@
#include <malloc.h>
#include <hush.h>
#include <net.h>
#include <netdev.h>
#include <asm/io.h>
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
......@@ -402,7 +403,7 @@ static void setports(int gpio)
#endif
#endif
#if !defined(CONFIG_KMETER1)
#if !defined(CONFIG_MPC83xx)
static void writeStartSeq(void)
{
set_sda(1);
......@@ -461,7 +462,7 @@ static int i2c_make_abort(void)
*/
void i2c_init_board(void)
{
#if defined(CONFIG_KMETER1)
#if defined(CONFIG_MPC83xx)
struct fsl_i2c *dev;
dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
uchar dummy;
......@@ -573,6 +574,7 @@ int board_eth_init(bd_t *bis)
(void)keymile_hdlc_enet_initialize(bis);
#endif
if (ethernet_present())
return -1;
return 0;
return cpu_eth_init(bis);
return -1;
}
......@@ -8,7 +8,7 @@
* Copyright (C) 2007 MontaVista Software, Inc.
* Anton Vorontsov <avorontsov@ru.mvista.com>
*
* (C) Copyright 2008
* (C) Copyright 2008 - 2010
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* This program is free software; you can redistribute it and/or
......@@ -32,7 +32,7 @@
const qe_iop_conf_t qe_iop_conf_tab[] = {
/* port pin dir open_drain assign */
#if defined(CONFIG_KMETER1)
/* MDIO */
{0, 1, 3, 0, 2}, /* MDIO */
{0, 2, 1, 0, 1}, /* MDC */
......@@ -55,6 +55,40 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
{5, 2, 1, 0, 1}, /* UART2_RTS */
{5, 3, 2, 0, 2}, /* UART2_SIN */
{5, 1, 2, 0, 3}, /* UART2_CTS */
#else
/* Local Bus */
{0, 16, 1, 0, 3}, /* LA00 */
{0, 17, 1, 0, 3}, /* LA01 */
{0, 18, 1, 0, 3}, /* LA02 */
{0, 19, 1, 0, 3}, /* LA03 */
{0, 20, 1, 0, 3}, /* LA04 */
{0, 21, 1, 0, 3}, /* LA05 */
{0, 22, 1, 0, 3}, /* LA06 */
{0, 23, 1, 0, 3}, /* LA07 */
{0, 24, 1, 0, 3}, /* LA08 */
{0, 25, 1, 0, 3}, /* LA09 */
{0, 26, 1, 0, 3}, /* LA10 */
{0, 27, 1, 0, 3}, /* LA11 */
{0, 28, 1, 0, 3}, /* LA12 */
{0, 29, 1, 0, 3}, /* LA13 */
{0, 30, 1, 0, 3}, /* LA14 */
{0, 31, 1, 0, 3}, /* LA15 */
/* MDIO */
{3, 4, 3, 0, 2}, /* MDIO */
{3, 5, 1, 0, 2}, /* MDC */
/* UCC4 - UEC */
{1, 18, 1, 0, 1}, /* TxD0 */
{1, 19, 1, 0, 1}, /* TxD1 */
{1, 22, 2, 0, 1}, /* RxD0 */
{1, 23, 2, 0, 1}, /* RxD1 */
{1, 26, 2, 0, 1}, /* RxER */
{1, 28, 2, 0, 1}, /* Rx_DV */
{1, 30, 1, 0, 1}, /* TxEN */
{1, 31, 2, 0, 1}, /* CRS */
{3, 10, 2, 0, 3}, /* TxCLK->CLK17 */
#endif
/* END of table */
{0, 0, 0, 0, QE_IOP_TAB_END},
......@@ -77,11 +111,38 @@ static int board_init_i2c_busses(void)
return 0;
}
#if defined(CONFIG_SUVD3)
const uint upma_table[] = {
0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04, /* Words 0 to 3 */
0x0ffcdc00, 0xffffcc00, 0xffffcc01, 0xfffffc01, /* Words 4 to 7 */
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 8 to 11 */
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 12 to 15 */
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 16 to 19 */
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 20 to 23 */
0x9cfffc00, 0x00fffc80, 0x00fffc80, 0x00fffc00, /* Words 24 to 27 */
0xffffec04, 0xffffec01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 32 to 35 */
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 36 to 39 */
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 40 to 43 */
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 44 to 47 */
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 48 to 51 */
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 52 to 55 */
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 56 to 59 */
0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01 /* Words 60 to 63 */
};
#endif
int board_early_init_r(void)
{
struct km_bec_fpga *base = (struct km_bec_fpga *)CONFIG_SYS_PIGGY_BASE;
unsigned short svid;
#if defined(CONFIG_SUVD3)
immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
fsl_lbc_t *lbc = &immap->im_lbc;
u32 *mxmr = &lbc->mamr;
#endif
#if defined(CONFIG_MPC8360)
unsigned short svid;
/*
* Because of errata in the UCCs, we have to write to the reserved
* registers to slow the clocks down.
......@@ -105,13 +166,19 @@ int board_early_init_r(void)
0x00000050, 0x000000a0);
break;
}
#endif
/* enable the PHY on the PIGGY */
setbits_8(&base->pgy_eth, 0x01);
/* enable the Unit LED (green) */
setbits_8(&base->oprth, WRL_BOOT);
/* take FE/GbE PHYs out of reset */
setbits_8(&base->prst, 0x1c);
#if defined(CONFIG_SUVD3)
/* configure UPMA for APP1 */
upmconfig(UPMA, (uint *) upma_table,
sizeof(upma_table) / sizeof(uint));
out_be32(mxmr, CONFIG_SYS_MAMR);
#endif
return 0;
}
......@@ -185,12 +252,13 @@ phys_size_t initdram(int board_type)
#endif
/* return total bus SDRAM size(bytes) -- DDR */
return (msize * 1024 * 1024);
return msize * 1024 * 1024;
}
int checkboard(void)
{
puts("Board: Keymile kmeter1");
puts("Board: Keymile " CONFIG_KM_BOARD_NAME);
if (ethernet_present())
puts(" with PIGGY.");
puts("\n");
......@@ -198,19 +266,9 @@ int checkboard(void)
}
#if defined(CONFIG_OF_BOARD_SETUP)
/*
* update property in the blob
*/
void ft_blob_update(void *blob, bd_t *bd)
{
/* no board specific update */
}
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup (blob, bd);
ft_blob_update (blob, bd);
ft_cpu_setup(blob, bd);
}
#endif
......
......@@ -486,10 +486,11 @@ MPC8360ERDK_66 powerpc mpc83xx mpc8360erdk freesca
MPC837XEMDS powerpc mpc83xx mpc837xemds freescale - MPC837XEMDS
MPC837XEMDS_HOST powerpc mpc83xx mpc837xemds freescale - MPC837XEMDS:PCI
MPC837XERDB powerpc mpc83xx mpc837xerdb freescale
kmeter1 powerpc mpc83xx kmeter1 keymile
kmeter1 powerpc mpc83xx km83xx keymile
MVBLM7 powerpc mpc83xx mvblm7 matrix_vision
SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_LP
SIMPC8313_SP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_SP
suvd3 powerpc mpc83xx km83xx keymile
TQM834x powerpc mpc83xx tqm834x tqc
sbc8540 powerpc mpc85xx sbc8560 - - SBC8540
sbc8540_33 powerpc mpc85xx sbc8560 - - SBC8540
......
/*
* (C) Copyright 2010
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
#ifndef __CONFIG_KM83XX_H
#define __CONFIG_KM83XX_H
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
#include "km-powerpc.h"
#define MTDIDS_DEFAULT "nor0=boot"
#define MTDPARTS_DEFAULT "mtdparts=" \
"boot:" \
"768k(u-boot)," \
"128k(env)," \
"128k(envred)," \
"-(" CONFIG_KM_UBI_PARTITION_NAME ")"
#define CONFIG_MISC_INIT_R
/*
* System Clock Setup
*/
#define CONFIG_83XX_CLKIN 66000000
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000
/*
* IMMR new address
*/
#define CONFIG_SYS_IMMR 0xE0000000
/*
* Bus Arbitration Configuration Register (ACR)
*/
#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
/*
* DDR Setup
*/
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
#define CFG_83XX_DDR_USES_CS0
/*
* Manually set up DDR parameters
*/
#define CONFIG_DDR_II
#define CONFIG_SYS_DDR_SIZE 2048 /* MB */
/*
* The reserved memory
*/
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_SYS_FLASH_BASE 0xF0000000
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#endif
/* Reserve 768 kB for Mon */
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
/*
* Initial RAM Base Address Setup
*/
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
/*
* Init Local Bus Memory Controller:
*
* Bank Bus Machine PortSz Size Device
* ---- --- ------- ------ ----- ------
* 0 Local GPCM 16 bit 256MB FLASH
* 1 Local GPCM 8 bit 128MB GPIO/PIGGY
*
*/
/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
BR_V)
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_5 | \
OR_GPCM_TRLX | OR_GPCM_EAD)
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
/*
* PRIO1/PIGGY on the local bus CS1
*/
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001A /* 128MB window size */
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_PIGGY_BASE | \
(1 << BR_PS_SHIFT) | /* 8 bit port size */ \
BR_V)
#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | \
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_2 | \
OR_GPCM_TRLX | OR_GPCM_EAD)
/*
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
/* Pass open firmware flat tree */
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_OF_STDOUT_VIA_ALIAS
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI
#endif
/*
* QE UEC ethernet configuration
*/
#define CONFIG_UEC_ETH
#define CONFIG_ETHPRIME "UEC0"
#define CONFIG_UEC_ETH1 /* GETH1 */
#define UEC_VERBOSE_DEBUG 1
#ifdef CONFIG_UEC_ETH1
#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 0
#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
#endif
/*
* Environment
*/
#ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
/* Address and size of Redundant Environment Sector */
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#else /* CFG_SYS_RAMBOOT */
#define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif /* CFG_SYS_RAMBOOT */
/* I2C */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_FSL_I2C
#define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x3000
/* I2C SYSMON (LM75, AD7414 is almost compatible) */
#define CONFIG_DTT_LM75 /* ON Semi's LM75 */
#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */
#define CONFIG_SYS_DTT_MAX_TEMP 70
#define CONFIG_SYS_DTT_LOW_TEMP -30
#define CONFIG_SYS_DTT_HYSTERESIS 3
#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
#if defined(CONFIG_CMD_NAND)
#define CONFIG_NAND_KMETER1
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE CONFIG_SYS_PIGGY_BASE
#endif
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#endif
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
/*
* Core HID Setup
*/
#define CONFIG_SYS_HID0_INIT 0x000000000
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2 HID2_HBE
/*
* MMU Setup
*/
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
/* DDR: cache cacheable */
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
/* IMMRBAR & PCI IO: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | \
BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
/* Stack in dcache: cacheable, no memory coherence */
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define BOOTFLASH_START 0xF0000000
#define CONFIG_KM_CONSOLE_TTY "ttyS0"
/*
* Environment Configuration
*/
#define CONFIG_ENV_OVERWRITE
#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
#define CONFIG_KM_DEF_ENV "km-common=empty\0"
#endif
#ifndef CONFIG_KM_DEF_ROOTPATH
#define CONFIG_KM_DEF_ROOTPATH \
"rootpath=/opt/eldk/ppc_82xx\0"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_KM_DEF_ENV \
CONFIG_KM_DEF_ROOTPATH \
"dtt_bus=pca9547:70:a\0" \
"EEprom_ivm=pca9547:70:9\0" \
"newenv=" \
"prot off 0xF00C0000 +0x40000 && " \
"era 0xF00C0000 +0x40000\0" \
"unlock=yes\0" \
""
#if defined(CONFIG_UEC_ETH)
#define CONFIG_HAS_ETH0
#endif
#endif /* __CONFIG_KM83XX_H */
......@@ -27,30 +27,20 @@
#define CONFIG_MPC8360 /* MPC8360 CPU specific */
#define CONFIG_KMETER1 /* KMETER1 board specific */
#define CONFIG_HOSTNAME kmeter1
#define CONFIG_KM_BOARD_NAME "kmeter1"
#define CONFIG_SYS_TEXT_BASE 0xF0000000
#define CONFIG_KM_DEF_NETDEV \
"netdev=eth2\0" \
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
#include "km-powerpc.h"
#define MTDIDS_DEFAULT "nor0=boot"
#define MTDPARTS_DEFAULT "mtdparts=" \
"boot:" \
"768k(u-boot)," \
"128k(env)," \
"128k(envred)," \
"-(" CONFIG_KM_UBI_PARTITION_NAME ")"
/* include common defines/options for all 83xx Keymile boards */
#include "km83xx-common.h"
#define CONFIG_MISC_INIT_R
/*
* System Clock Setup
* System IO Setup
*/
#define CONFIG_83XX_CLKIN 66000000
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000
#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
/*
* Hardware Reset Configuration Word
......@@ -71,55 +61,7 @@
HRCWH_LALE_EARLY | \
HRCWH_LDP_CLEAR )
/*
* System IO Config
*/
#define CONFIG_SYS_SICRH 0x00000006
#define CONFIG_SYS_SICRL 0x00000000
/*
* IMMR new address
*/
#define CONFIG_SYS_IMMR 0xE0000000
/*
* Bus Arbitration Configuration Register (ACR)
*/
#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */
#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */
#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */
/*
* DDR Setup
*/
#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
#define CFG_83XX_DDR_USES_CS0
#undef CONFIG_DDR_ECC
/*
* DDRCDR - DDR Control Driver Register
*/
<