Commit 63f34912 authored by wdenk's avatar wdenk
Browse files

* Patch by Andr Schwarz, 8 Dec 2003:

  fixes for Davicom DM9102A Ethernet Chip (#define CONFIG_TULIP_FIX_DAVICOM):
  - TX and RX deskriptors must be quad-word aligned
  - does not work with only one TX deskriptor
  - standard reset method does not work

* Patch by Masami Komiya, 08 Dec 2003:
  add RTL8139 ethernet driver

* Patches by Ed Okerson, 07 Dec 2003:
  - fix ethernet for the AU1x00 processors in little-endian mode.
  - extend memsetup.S for the AU1x00 processors in BE and LE modes
parent d4ca31c4
......@@ -2,6 +2,19 @@
Changes since U-Boot 1.0.0:
======================================================================
* Patch by Andr Schwarz, 8 Dec 2003:
fixes for Davicom DM9102A Ethernet Chip (#define CONFIG_TULIP_FIX_DAVICOM):
- TX and RX deskriptors must be quad-word aligned
- does not work with only one TX deskriptor
- standard reset method does not work
* Patch by Masami Komiya, 08 Dec 2003:
add RTL8139 ethernet driver
* Patches by Ed Okerson, 07 Dec 2003:
- fix ethernet for the AU1x00 processors in little-endian mode.
- extend memsetup.S for the AU1x00 processors in BE and LE modes
* Minor code cleanup (coding style)
* Patch by Reinhard Meyer, 30 Dec 2003:
......
......@@ -4,114 +4,358 @@
#include <version.h>
#include <asm/regdef.h>
#include <asm/au1x00.h>
#include <asm/mipsregs.h>
#define AU1500_SYS_ADDR 0xB1900000
#define sys_endian 0x0038
#define CP0_Config0 $16
#define MEM_1MS ((396000000/1000000) * 1000)
.text
.set noreorder
.set mips32
.globl memsetup
memsetup:
/*
* Step 1) Establish CPU endian mode.
* Db1500-specific:
* Switch S1.1 Off(bit7 reads 1) is Little Endian
* Switch S1.1 On (bit7 reads 0) is Big Endian
*/
li t0, MEM_STCFG1
li t1, 0x00000080
sw t1, 0(t0)
li t0, MEM_STTIME1
li t1, 0x22080a20
sw t1, 0(t0)
li t0, MEM_STADDR1
li t1, 0x10c03f00
sw t1, 0(t0)
li t0, 0xAE000008
lw t1,0(t0)
andi t1,t1,0x80
beq zero,t1,big_endian
nop
little_endian:
/* Change Au1 core to little endian */
li t0, AU1500_SYS_ADDR
li t1, 1
sw t1, sys_endian(t0)
mfc0 t2, CP0_CONFIG
mtc0 t2, CP0_CONFIG
nop
nop
/* Big Endian is default so nothing to do but fall through */
big_endian:
/*
* Step 2) Establish Status Register
* (set BEV, clear ERL, clear EXL, clear IE)
*/
li t1, 0x00400000
mtc0 t1, CP0_STATUS
/*
* Step 3) Establish CP0 Config0
* (set OD, set K0=3)
*/
li t1, 0x00080003
mtc0 t1, CP0_CONFIG
/*
* Step 4) Disable Watchpoint facilities
*/
li t1, 0x00000000
mtc0 t1, CP0_WATCHLO
mtc0 t1, CP0_IWATCHLO
/*
* Step 5) Disable the performance counters
*/
mtc0 zero, CP0_PERFORMANCE
nop
/*
* Step 6) Establish EJTAG Debug register
*/
mtc0 zero, CP0_DEBUG
nop
/*
* Step 7) Establish Cause
* (set IV bit)
*/
li t1, 0x00800000
mtc0 t1, CP0_CAUSE
/* Establish Wired (and Random) */
mtc0 zero, CP0_WIRED
nop
/* First setup pll:s to make serial work ok */
/* We have a 12 MHz crystal */
li t0, SYS_CPUPLL
li t1, 0x21 /* 396 MHz */
sw t1, 0(t0)
li t0, SYS_CPUPLL
li t1, 0x21 /* 396 MHz */
sw t1, 0(t0)
sync
nop
nop
/* wait 1mS for clocks to settle */
li t1, MEM_1MS
1: add t1, -1
bne t1, zero, 1b
nop
/* Setup AUX PLL */
li t0, SYS_AUXPLL
li t1, 8 /* 96 MHz */
sw t1, 0(t0) /* aux pll */
li t0, SYS_AUXPLL
li t1, 0x20 /* 96 MHz */
sw t1, 0(t0) /* aux pll */
sync
/* SDCS 0,1 SDRAM */
li t0, MEM_SDMODE0
li t1, 0x005522AA
sw t1, 0(t0)
/* Static memory controller */
li t0, MEM_SDMODE1
li t1, 0x005522AA
sw t1, 0(t0)
/* RCE0 AMD 29LV640M MirrorBit Flash */
li t0, MEM_STCFG0
li t1, 0x00000013
sw t1, 0(t0)
li t0, MEM_SDADDR0
li t1, 0x001003F8
sw t1, 0(t0)
li t0, MEM_STTIME0
li t1, 0x040181D7
sw t1, 0(t0)
li t0, MEM_STADDR0
li t1, 0x11E03F80
sw t1, 0(t0)
li t0, MEM_SDADDR1
li t1, 0x001023F8
sw t1, 0(t0)
sync
/* RCE1 CPLD Board Logic */
li t0, MEM_STCFG1
li t1, 0x00000080
sw t1, 0(t0)
li t0, MEM_SDREFCFG
li t1, 0x64000C24 /* Disable */
sw t1, 0(t0)
sync
li t0, MEM_STTIME1
li t1, 0x22080a20
sw t1, 0(t0)
li t0, MEM_SDPRECMD
sw zero, 0(t0)
sync
li t0, MEM_STADDR1
li t1, 0x10c03f00
sw t1, 0(t0)
/* RCE2 CPLD Board Logic */
li t0, MEM_STCFG2
li t1, 0x00000000
sw t1, 0(t0)
li t0, MEM_STTIME2
li t1, 0x00000000
sw t1, 0(t0)
li t0, MEM_STADDR2
li t1, 0x00000000
sw t1, 0(t0)
/* RCE3 PCMCIA 250ns */
li t0, MEM_STCFG3
li t1, 0x00000002
sw t1, 0(t0)
li t0, MEM_STTIME3
li t1, 0x280E3E07
sw t1, 0(t0)
li t0, MEM_STADDR3
li t1, 0x10000000
sw t1, 0(t0)
li t0, MEM_SDAUTOREF
sw zero, 0(t0)
sync
sw zero, 0(t0)
sync
li t0, MEM_SDREFCFG
li t1, 0x66000C24 /* Enable */
sw t1, 0(t0)
/* Set peripherals to a known state */
li t0, IC0_CFG0CLR
li t1, 0xFFFFFFFF
sw t1, 0(t0)
li t0, IC0_CFG0CLR
sw t1, 0(t0)
li t0, IC0_CFG1CLR
sw t1, 0(t0)
li t0, IC0_CFG2CLR
sw t1, 0(t0)
li t0, IC0_SRCSET
sw t1, 0(t0)
li t0, IC0_ASSIGNSET
sw t1, 0(t0)
li t0, IC0_WAKECLR
sw t1, 0(t0)
li t0, IC0_RISINGCLR
sw t1, 0(t0)
li t0, IC0_FALLINGCLR
sw t1, 0(t0)
li t0, IC0_TESTBIT
li t1, 0x00000000
sw t1, 0(t0)
sync
li t0, MEM_SDWRMD0
li t1, 0x00000033
sw t1, 0(t0)
li t0, IC1_CFG0CLR
li t1, 0xFFFFFFFF
sw t1, 0(t0)
li t0, IC1_CFG0CLR
sw t1, 0(t0)
li t0, IC1_CFG1CLR
sw t1, 0(t0)
li t0, IC1_CFG2CLR
sw t1, 0(t0)
li t0, IC1_SRCSET
sw t1, 0(t0)
li t0, IC1_ASSIGNSET
sw t1, 0(t0)
li t0, IC1_WAKECLR
sw t1, 0(t0)
li t0, IC1_RISINGCLR
sw t1, 0(t0)
li t0, IC1_FALLINGCLR
sw t1, 0(t0)
li t0, IC1_TESTBIT
li t1, 0x00000000
sw t1, 0(t0)
sync
li t0, MEM_SDWRMD1
li t1, 0x00000033
sw t1, 0(t0)
li t0, SYS_FREQCTRL0
li t1, 0x00000000
sw t1, 0(t0)
li t0, SYS_FREQCTRL1
li t1, 0x00000000
sw t1, 0(t0)
li t0, SYS_CLKSRC
li t1, 0x00000000
sw t1, 0(t0)
li t0, SYS_PININPUTEN
li t1, 0x00000000
sw t1, 0(t0)
sync
/* Static memory controller */
li t0, 0xB1100100
li t1, 0x00000000
sw t1, 0(t0)
/* RCE0 AMD 29LV640M MirrorBit Flash */
li t0, MEM_STCFG0
li t1, 0x00000003
sw t1, 0(t0)
li t0, 0xB1400100
li t1, 0x00000000
sw t1, 0(t0)
li t0, MEM_STTIME0
li t1, 0x22080b20
sw t1, 0(t0)
li t0, MEM_STADDR0
li t1, 0x11E03F80
sw t1, 0(t0)
li t0, SYS_WAKEMSK
li t1, 0x00000000
sw t1, 0(t0)
/* RCE1 CPLD Board Logic */
li t0, MEM_STCFG1
li t1, 0x00000080
sw t1, 0(t0)
li t0, SYS_WAKESRC
li t1, 0x00000000
sw t1, 0(t0)
li t0, MEM_STTIME1
li t1, 0x22080a20
sw t1, 0(t0)
/* wait 1mS before setup */
li t1, MEM_1MS
1: add t1, -1
bne t1, zero, 1b
nop
li t0, MEM_STADDR1
li t1, 0x10c03f00
sw t1, 0(t0)
/* SDCS 0,1 SDRAM */
li t0, MEM_SDMODE0
li t1, 0x005522AA
sw t1, 0(t0)
/* RCE3 PCMCIA 250ns */
li t0, MEM_STCFG3
li t1, 0x00000002
sw t1, 0(t0)
li t0, MEM_SDMODE1
li t1, 0x005522AA
sw t1, 0(t0)
li t0, MEM_SDMODE2
li t1, 0x00000000
sw t1, 0(t0)
li t0, MEM_SDADDR0
li t1, 0x001003F8
sw t1, 0(t0)
li t0, MEM_SDADDR1
li t1, 0x001023F8
sw t1, 0(t0)
li t0, MEM_SDADDR2
li t1, 0x00000000
sw t1, 0(t0)
sync
li t0, MEM_SDREFCFG
li t1, 0x64000C24 /* Disable */
sw t1, 0(t0)
sync
li t0, MEM_SDPRECMD
sw zero, 0(t0)
sync
li t0, MEM_SDAUTOREF
sw zero, 0(t0)
sync
sw zero, 0(t0)
sync
li t0, MEM_SDREFCFG
li t1, 0x66000C24 /* Enable */
sw t1, 0(t0)
sync
li t0, MEM_SDWRMD0
li t1, 0x00000033
sw t1, 0(t0)
sync
li t0, MEM_SDWRMD1
li t1, 0x00000033
sw t1, 0(t0)
sync
/* wait 1mS after setup */
li t1, MEM_1MS
1: add t1, -1
bne t1, zero, 1b
nop
li t0, MEM_STTIME3
li t1, 0x280E3E07
sw t1, 0(t0)
li t0, SYS_PINFUNC
li t1, 0x00008080
sw t1, 0(t0)
li t0, MEM_STADDR3
li t1, 0x10000000
sw t1, 0(t0)
li t0, SYS_TRIOUTCLR
li t1, 0x00001FFF
sw t1, 0(t0)
li t0, SYS_OUTPUTCLR
li t1, 0x00008000
sw t1, 0(t0)
sync
j ra
......
......@@ -187,19 +187,24 @@ static int au1x00_init(struct eth_device* dev, bd_t * bd){
}
/* Put mac addr in little endian */
/* FIXME Check this for little endian mode */
#define ea eth_get_dev()->enetaddr
*mac_addr_high = (ea[5] << 8) | (ea[4] ) ;
*mac_addr_low = (ea[3] << 24) | (ea[2] << 16) |
(ea[1] << 8) | (ea[0] ) ;
#undef ea
*mac_mcast_low = 0;
*mac_mcast_high = 0;
/* Make sure the MAC buffer is in the correct endian mode */
#ifdef __LITTLE_ENDIAN
*mac_ctrl = MAC_FULL_DUPLEX;
udelay(1);
*mac_ctrl = MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
#else
*mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX;
udelay(1);
*mac_ctrl = MAC_BIG_ENDIAN|MAC_FULL_DUPLEX|MAC_RX_ENABLE|MAC_TX_ENABLE;
#endif
return(1);
}
......
......@@ -36,7 +36,7 @@ OBJS = 3c589.o 5701rls.o ali512x.o \
ns16550.o ns8382x.o ns87308.o \
pci.o pci_auto.o pci_indirect.o \
pcnet.o plb2800_eth.o \
rtl8019.o \
rtl8019.o rtl8139.o \
s3c24x0_i2c.o sed13806.o serial.o \
serial_max3100.o \
smc91111.o smiLynxEM.o sym53c8xx.o \
......
......@@ -98,6 +98,15 @@
#define POLL_DEMAND 1
#ifdef CONFIG_TULIP_FIX_DAVICOM
#define RESET_DM9102(dev) {\
unsigned long i;\
i=INL(dev, 0x0);\
udelay(1000);\
OUTL(dev, i | BMR_SWR, DE4X5_BMR);\
udelay(1000);\
}
#else
#define RESET_DE4X5(dev) {\
int i;\
i=INL(dev, DE4X5_BMR);\
......@@ -109,6 +118,7 @@
for (i=0;i<5;i++) {INL(dev, DE4X5_BMR); udelay(10000);}\
udelay(1000);\
}
#endif
#define START_DE4X5(dev) {\
s32 omr; \
......@@ -125,7 +135,11 @@
}
#define NUM_RX_DESC PKTBUFSRX
#define NUM_TX_DESC 1 /* Number of TX descriptors */
#ifndef CONFIG_TULIP_FIX_DAVICOM
#define NUM_TX_DESC 1 /* Number of TX descriptors */
#else
#define NUM_TX_DESC 4
#endif
#define RX_BUFF_SZ PKTSIZE_ALIGN
#define TOUT_LOOP 1000000
......@@ -133,7 +147,6 @@
#define SETUP_FRAME_LEN 192
#define ETH_ALEN 6
struct de4x5_desc {
volatile s32 status;
u32 des1;
......@@ -141,8 +154,8 @@ struct de4x5_desc {
u32 next;
};
static struct de4x5_desc rx_ring[NUM_RX_DESC]; /* RX descriptor ring */
static struct de4x5_desc tx_ring[NUM_TX_DESC]; /* TX descriptor ring */
static struct de4x5_desc rx_ring[NUM_RX_DESC] __attribute__ ((aligned(32))); /* RX descriptor ring */
static struct de4x5_desc tx_ring[NUM_TX_DESC] __attribute__ ((aligned(32))); /* TX descriptor ring */
static int rx_new; /* RX descriptor ring pointer */
static int tx_new; /* TX descriptor ring pointer */
......@@ -188,6 +201,9 @@ static void OUTL(struct eth_device* dev, int command, u_long addr)
static struct pci_device_id supported[] = {
{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST },
{ PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 },
#ifdef CONFIG_TULIP_FIX_DAVICOM
{ PCI_VENDOR_ID_DAVICOM, PCI_DEVICE_ID_DAVICOM_DM9102A },
#endif
{ }
};
......@@ -211,10 +227,12 @@ int dc21x4x_initialize(bd_t *bis)
/* Get the chip configuration revision register. */
pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv);
#ifndef CONFIG_TULIP_FIX_DAVICOM
if ((cfrv & CFRV_RN) < DC2114x_BRK ) {
printf("Error: The chip is not DC21143.\n");
continue;
}
#endif
pci_read_config_word(devbusfn, PCI_COMMAND, &status);
status |=
......@@ -265,7 +283,12 @@ int dc21x4x_initialize(bd_t *bis)
dev = (struct eth_device*) malloc(sizeof *dev);
sprintf(dev->name, "dc21x4x#%d", card_number);
#ifdef CONFIG_TULIP_FIX_DAVICOM
sprintf(dev->name, "Davicom#%d", card_number);
#else
sprintf(dev->name, "dc21x4x#%d", card_number);
#endif
#ifdef CONFIG_TULIP_USE_IO
dev->iobase = pci_io_to_phys(devbusfn, iobase);
#else
......@@ -282,8 +305,9 @@ int dc21x4x_initialize(bd_t *bis)
udelay(10 * 1000);
read_hw_addr(dev, bis);
#ifndef CONFIG_TULIP_FIX_DAVICOM
read_hw_addr(dev, bis);
#endif
eth_register(dev);
card_number++;
......@@ -300,7 +324,11 @@ static int dc21x4x_init(struct eth_device* dev, bd_t* bis)
/* Ensure we're not sleeping. */
pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
#ifdef CONFIG_TULIP_FIX_DAVICOM
RESET_DM9102(dev);
#else
RESET_DE4X5(dev);
#endif
if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
printf("Error: Cannot reset ethernet controller.\n");
......@@ -317,14 +345,23 @@ static int dc21x4x_init(struct eth_device* dev, bd_t* bis)
rx_ring[i].status = cpu_to_le32(R_OWN);
rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
rx_ring[i].buf = cpu_to_le32(phys_to_bus((u32) NetRxPackets[i]));
#ifdef CONFIG_TULIP_FIX_DAVICOM
rx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &rx_ring[(i+1) % NUM_RX_DESC]));
#else
rx_ring[i].next = 0;
#endif
}
for (i=0; i < NUM_TX_DESC; i++) {
tx_ring[i].status = 0;
tx_ring[i].des1 = 0;
tx_ring[i].buf = 0;
#ifdef CONFIG_TULIP_FIX_DAVICOM
tx_ring[i].next = cpu_to_le32(phys_to_bus((u32) &tx_ring[(i+1) % NUM_TX_DESC]));
#else
tx_ring[i].next = 0;
#endif
}
rxRingSize = NUM_RX_DESC;
......@@ -383,12 +420,14 @@ static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int lengt
printf("TX error status = 0x%08X\n",
le32_to_cpu(tx_ring[tx_new].status));
#endif
tx_ring[tx_new].status = 0x0;
goto Done;