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Librem5
uboot-imx
Commits
66b33569
Commit
66b33569
authored
Jun 18, 2018
by
Dmitry Konyshev
Browse files
RM2614 Add support for Kingston LPDDR4 2GiB module at 800MHz
parent
ae6dfb4a
Changes
9
Expand all
Hide whitespace changes
Inline
Side-by-side
arch/arm/cpu/armv8/imx8m/Kconfig
View file @
66b33569
...
...
@@ -49,6 +49,11 @@ config TARGET_EMCRAFT_IMX8M_LPDDR4_3GB_SOM
select IMX8M
select SUPPORT_SPL
config TARGET_EMCRAFT_IMX8M_LPDDR4_800MHZ_2GB_SOM
bool "emcraft_imx8m_lpddr4_800mhz_2gb_som"
select IMX8M
select SUPPORT_SPL
endchoice
config SYS_SOC
...
...
arch/arm/dts/emcraft-imx8m-som.dts
View file @
66b33569
...
...
@@ -13,8 +13,10 @@
/
{
#
if
defined
(
CONFIG_TARGET_EMCRAFT_IMX8M_SOM
)
model
=
"Emcraft i.MX8M SOM DDR3L"
;
#
elif
defined
(
CONFIG_TARGET_EMCRAFT_IMX8M_LPDDR4_800MHZ_2GB_SOM
)
model
=
"Emcraft i.MX8M SOM LPDDR4-800"
;
#
else
model
=
"Emcraft i.MX8M SOM LPDDR4"
;
model
=
"Emcraft i.MX8M SOM LPDDR4
-1600
"
;
#
endif
compatible
=
"emcraft,imx8m-som"
,
"fsl,imx8mq"
;
...
...
board/emcraft/imx8m_som/Makefile
View file @
66b33569
...
...
@@ -20,6 +20,9 @@ obj-y += ddr/lpddr4_2gb/ddr_init.o ddr/lpddr4_2gb/ddrphy_train.o \
else
ifdef
CONFIG_TARGET_EMCRAFT_IMX8M_LPDDR4_3GB_SOM
obj-y
+=
ddr/lpddr4_3gb/ddr_init.o ddr/lpddr4_3gb/ddrphy_train.o
\
ddr/lpddr4/helper.o
else
ifdef
CONFIG_TARGET_EMCRAFT_IMX8M_LPDDR4_800MHZ_2GB_SOM
obj-y
+=
ddr/lpddr4_800mhz_2gb/ddr_init.o ddr/lpddr4_800mhz_2gb/ddrphy_train.o
\
ddr/lpddr4/helper.o
else
obj-y
+=
ddr/lpddr4/ddr_init.o ddr/lpddr4/ddrphy_train.o
\
ddr/lpddr4/helper.o
...
...
board/emcraft/imx8m_som/ddr/lpddr4_800mhz_2gb/ddr.h
0 → 100644
View file @
66b33569
/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
enum
fw_type
{
FW_1D_IMAGE
,
FW_2D_IMAGE
,
};
void
ddr_init
(
void
);
void
ddr_load_train_code
(
enum
fw_type
type
);
void
lpddr4_800M_cfg_phy
(
void
);
static
inline
void
reg32_write
(
unsigned
long
addr
,
u32
val
)
{
writel
(
val
,
addr
);
}
static
inline
uint32_t
reg32_read
(
unsigned
long
addr
)
{
return
readl
(
addr
);
}
static
void
inline
dwc_ddrphy_apb_wr
(
unsigned
long
addr
,
u32
val
)
{
writel
(
val
,
addr
);
}
static
inline
void
reg32setbit
(
unsigned
long
addr
,
u32
bit
)
{
setbits_le32
(
addr
,
(
1
<<
bit
));
}
board/emcraft/imx8m_som/ddr/lpddr4_800mhz_2gb/ddr_init.c
0 → 100644
View file @
66b33569
/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
* Generated code from MX8_DDR_tool
*/
#include
<common.h>
#include
<errno.h>
#include
<asm/io.h>
#include
<asm/arch/ddr_memory_map.h>
#include
<asm/arch/clock.h>
#include
"ddr.h"
#ifdef CONFIG_ENABLE_DDR_TRAINING_DEBUG
#define ddr_printf(args...) printf(args)
#else
#define ddr_printf(args...)
#endif
#include
"wait_ddrphy_training_complete.c"
#ifndef SRC_DDRC_RCR_ADDR
#define SRC_DDRC_RCR_ADDR SRC_IPS_BASE_ADDR +0x1000
#endif
#ifndef DDR_CSD1_BASE_ADDR
#define DDR_CSD1_BASE_ADDR 0x40000000
#endif
#define SILICON_TRAIN
void
ddr_cfg_phy
(
void
);
volatile
unsigned
int
tmp
,
tmp_t
,
i
;
void
ddr_init
(
void
)
{
/** Initialize DDR clock and DDRC registers **/
reg32_write
(
0x3038a088
,
0x7070000
);
reg32_write
(
0x3038a084
,
0x4030000
);
reg32_write
(
0x303a00ec
,
0xffff
);
tmp
=
reg32_read
(
0x303a00f8
);
tmp
|=
0x20
;
reg32_write
(
0x303a00f8
,
tmp
);
reg32_write
(
0x30391000
,
0x8f000000
);
reg32_write
(
0x30391004
,
0x8f000000
);
reg32_write
(
0x30360068
,
0xac0784
);
tmp
=
reg32_read
(
0x30360060
);
tmp
&=
~
0x80
;
reg32_write
(
0x30360060
,
tmp
);
tmp
=
reg32_read
(
0x30360060
);
tmp
|=
0x200
;
reg32_write
(
0x30360060
,
tmp
);
tmp
=
reg32_read
(
0x30360060
);
tmp
&=
~
0x20
;
reg32_write
(
0x30360060
,
tmp
);
tmp
=
reg32_read
(
0x30360060
);
tmp
&=
~
0x10
;
reg32_write
(
0x30360060
,
tmp
);
do
{
tmp
=
reg32_read
(
0x30360060
);
if
(
tmp
&
0x80000000
)
break
;
}
while
(
1
);
reg32_write
(
0x30391000
,
0x8f000006
);
reg32_write
(
0x3d400304
,
0x1
);
reg32_write
(
0x3d400030
,
0x1
);
reg32_write
(
0x3d400000
,
0xa3080020
);
reg32_write
(
0x3d400028
,
0x0
);
reg32_write
(
0x3d400020
,
0x101
);
reg32_write
(
0x3d400024
,
0xc35000
);
reg32_write
(
0x3d400064
,
0x300070
);
reg32_write
(
0x3d4000d0
,
0xc002030f
);
reg32_write
(
0x3d4000d4
,
0x500000
);
reg32_write
(
0x3d4000dc
,
0xa40012
);
reg32_write
(
0x3d4000e0
,
0x310008
);
reg32_write
(
0x3d4000e8
,
0x66004a
);
reg32_write
(
0x3d4000ec
,
0x16004a
);
reg32_write
(
0x3d400100
,
0x10100d11
);
reg32_write
(
0x3d400104
,
0x3041a
);
reg32_write
(
0x3d40010c
,
0x606000
);
reg32_write
(
0x3d400110
,
0x8040408
);
reg32_write
(
0x3d400114
,
0x2030606
);
reg32_write
(
0x3d400118
,
0x1010004
);
reg32_write
(
0x3d40011c
,
0x301
);
reg32_write
(
0x3d400130
,
0x20300
);
reg32_write
(
0x3d400134
,
0xa100002
);
reg32_write
(
0x3d400138
,
0x73
);
reg32_write
(
0x3d400144
,
0x500028
);
reg32_write
(
0x3d400180
,
0x190000c
);
reg32_write
(
0x3d400184
,
0x14030d4
);
reg32_write
(
0x3d400188
,
0x0
);
reg32_write
(
0x3d400190
,
0x4898204
);
reg32_write
(
0x3d400194
,
0x80303
);
reg32_write
(
0x3d4001a0
,
0xe0400018
);
reg32_write
(
0x3d4001a4
,
0xdf00e4
);
reg32_write
(
0x3d4001a8
,
0x80000000
);
reg32_write
(
0x3d4001b0
,
0x11
);
reg32_write
(
0x3d4001b4
,
0x904
);
reg32_write
(
0x3d4001c0
,
0x1
);
reg32_write
(
0x3d4001c4
,
0x1
);
reg32_write
(
0x3d4000f4
,
0x639
);
reg32_write
(
0x3d400108
,
0x4070b0d
);
reg32_write
(
0x3d400200
,
0x16
);
reg32_write
(
0x3d40020c
,
0x0
);
reg32_write
(
0x3d400210
,
0x1f1f
);
reg32_write
(
0x3d400204
,
0x80808
);
reg32_write
(
0x3d400214
,
0x7070707
);
reg32_write
(
0x3d400218
,
0xf070707
);
reg32_write
(
0x3d402020
,
0x1
);
reg32_write
(
0x3d402024
,
0x518b00
);
reg32_write
(
0x3d402050
,
0x20d040
);
reg32_write
(
0x3d402064
,
0x14002f
);
reg32_write
(
0x3d4020dc
,
0x940009
);
reg32_write
(
0x3d4020e0
,
0x310000
);
reg32_write
(
0x3d4020e8
,
0x66004a
);
reg32_write
(
0x3d4020ec
,
0x16004a
);
reg32_write
(
0x3d402100
,
0xb070508
);
reg32_write
(
0x3d402104
,
0x3040b
);
reg32_write
(
0x3d402108
,
0x305090c
);
reg32_write
(
0x3d40210c
,
0x505000
);
reg32_write
(
0x3d402110
,
0x4040204
);
reg32_write
(
0x3d402114
,
0x2030303
);
reg32_write
(
0x3d402118
,
0x1010004
);
reg32_write
(
0x3d40211c
,
0x301
);
reg32_write
(
0x3d402130
,
0x20300
);
reg32_write
(
0x3d402134
,
0xa100002
);
reg32_write
(
0x3d402138
,
0x31
);
reg32_write
(
0x3d402144
,
0x220011
);
reg32_write
(
0x3d402180
,
0xa70006
);
reg32_write
(
0x3d402190
,
0x3858202
);
reg32_write
(
0x3d402194
,
0x80303
);
reg32_write
(
0x3d4021b4
,
0x502
);
reg32_write
(
0x3d400244
,
0x0
);
reg32_write
(
0x3d400250
,
0x29001505
);
reg32_write
(
0x3d400254
,
0x2c
);
reg32_write
(
0x3d40025c
,
0x5900575b
);
reg32_write
(
0x3d400264
,
0x9
);
reg32_write
(
0x3d40026c
,
0x2005574
);
reg32_write
(
0x3d400300
,
0x16
);
reg32_write
(
0x3d400304
,
0x0
);
reg32_write
(
0x3d40030c
,
0x0
);
reg32_write
(
0x3d400320
,
0x1
);
reg32_write
(
0x3d40036c
,
0x11
);
reg32_write
(
0x3d400400
,
0x111
);
reg32_write
(
0x3d400404
,
0x10f3
);
reg32_write
(
0x3d400408
,
0x72ff
);
reg32_write
(
0x3d400490
,
0x1
);
reg32_write
(
0x3d400494
,
0x1110d00
);
reg32_write
(
0x3d400498
,
0x620790
);
reg32_write
(
0x3d40049c
,
0x100001
);
reg32_write
(
0x3d4004a0
,
0x41f
);
reg32_write
(
0x30391000
,
0x8f000004
);
reg32_write
(
0x30391000
,
0x8f000000
);
reg32_write
(
0x3d400030
,
0xa8
);
do
{
tmp
=
reg32_read
(
0x3d400004
);
if
(
tmp
&
0x223
)
break
;
}
while
(
1
);
reg32_write
(
0x3d400320
,
0x0
);
reg32_write
(
0x3d000000
,
0x1
);
reg32_write
(
0x3d4001b0
,
0x10
);
reg32_write
(
0x3c040280
,
0x0
);
reg32_write
(
0x3c040284
,
0x1
);
reg32_write
(
0x3c040288
,
0x2
);
reg32_write
(
0x3c04028c
,
0x3
);
reg32_write
(
0x3c040290
,
0x4
);
reg32_write
(
0x3c040294
,
0x5
);
reg32_write
(
0x3c040298
,
0x6
);
reg32_write
(
0x3c04029c
,
0x7
);
reg32_write
(
0x3c044280
,
0x0
);
reg32_write
(
0x3c044284
,
0x1
);
reg32_write
(
0x3c044288
,
0x2
);
reg32_write
(
0x3c04428c
,
0x3
);
reg32_write
(
0x3c044290
,
0x4
);
reg32_write
(
0x3c044294
,
0x5
);
reg32_write
(
0x3c044298
,
0x6
);
reg32_write
(
0x3c04429c
,
0x7
);
reg32_write
(
0x3c048280
,
0x0
);
reg32_write
(
0x3c048284
,
0x1
);
reg32_write
(
0x3c048288
,
0x2
);
reg32_write
(
0x3c04828c
,
0x3
);
reg32_write
(
0x3c048290
,
0x4
);
reg32_write
(
0x3c048294
,
0x5
);
reg32_write
(
0x3c048298
,
0x6
);
reg32_write
(
0x3c04829c
,
0x7
);
reg32_write
(
0x3c04c280
,
0x0
);
reg32_write
(
0x3c04c284
,
0x1
);
reg32_write
(
0x3c04c288
,
0x2
);
reg32_write
(
0x3c04c28c
,
0x3
);
reg32_write
(
0x3c04c290
,
0x4
);
reg32_write
(
0x3c04c294
,
0x5
);
reg32_write
(
0x3c04c298
,
0x6
);
reg32_write
(
0x3c04c29c
,
0x7
);
/* Configure DDR PHY's registers */
ddr_cfg_phy
();
reg32_write
(
DDRC_RFSHCTL3
(
0
),
0x00000000
);
reg32_write
(
DDRC_SWCTL
(
0
),
0x0000
);
/*
* ------------------- 9 -------------------
* Set DFIMISC.dfi_init_start to 1
* -----------------------------------------
*/
reg32_write
(
DDRC_DFIMISC
(
0
),
0x00000030
);
reg32_write
(
DDRC_SWCTL
(
0
),
0x0001
);
/* wait DFISTAT.dfi_init_complete to 1 */
tmp_t
=
0
;
while
(
tmp_t
==
0
){
tmp
=
reg32_read
(
DDRC_DFISTAT
(
0
));
tmp_t
=
tmp
&
0x01
;
tmp
=
reg32_read
(
DDRC_MRSTAT
(
0
));
}
reg32_write
(
DDRC_SWCTL
(
0
),
0x0000
);
/* clear DFIMISC.dfi_init_complete_en */
reg32_write
(
DDRC_DFIMISC
(
0
),
0x00000010
);
reg32_write
(
DDRC_DFIMISC
(
0
),
0x00000011
);
reg32_write
(
DDRC_PWRCTL
(
0
),
0x00000088
);
tmp
=
reg32_read
(
DDRC_CRCPARSTAT
(
0
));
/*
* set SWCTL.sw_done to enable quasi-dynamic register
* programming outside reset.
*/
reg32_write
(
DDRC_SWCTL
(
0
),
0x00000001
);
/* wait SWSTAT.sw_done_ack to 1 */
while
((
reg32_read
(
DDRC_SWSTAT
(
0
))
&
0x1
)
==
0
)
;
/* wait STAT.operating_mode([1:0] for ddr3) to normal state */
while
((
reg32_read
(
DDRC_STAT
(
0
))
&
0x3
)
!=
0x1
)
;
reg32_write
(
DDRC_PWRCTL
(
0
),
0x00000088
);
/* reg32_write(DDRC_PWRCTL(0), 0x018a); */
tmp
=
reg32_read
(
DDRC_CRCPARSTAT
(
0
));
/* enable port 0 */
reg32_write
(
DDRC_PCTRL_0
(
0
),
0x00000001
);
tmp
=
reg32_read
(
DDRC_CRCPARSTAT
(
0
));
reg32_write
(
DDRC_RFSHCTL3
(
0
),
0x00000000
);
}
\ No newline at end of file
board/emcraft/imx8m_som/ddr/lpddr4_800mhz_2gb/ddrphy_train.c
0 → 100644
View file @
66b33569
This diff is collapsed.
Click to expand it.
board/emcraft/imx8m_som/ddr/lpddr4_800mhz_2gb/wait_ddrphy_training_complete.c
0 → 100644
View file @
66b33569
/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
static
inline
void
poll_pmu_message_ready
(
void
)
{
unsigned
int
reg
;
do
{
reg
=
reg32_read
(
IP2APB_DDRPHY_IPS_BASE_ADDR
(
0
)
+
4
*
0xd0004
);
}
while
(
reg
&
0x1
);
}
static
inline
void
ack_pmu_message_recieve
(
void
)
{
unsigned
int
reg
;
reg32_write
(
IP2APB_DDRPHY_IPS_BASE_ADDR
(
0
)
+
4
*
0xd0031
,
0x0
);
do
{
reg
=
reg32_read
(
IP2APB_DDRPHY_IPS_BASE_ADDR
(
0
)
+
4
*
0xd0004
);
}
while
(
!
(
reg
&
0x1
));
reg32_write
(
IP2APB_DDRPHY_IPS_BASE_ADDR
(
0
)
+
4
*
0xd0031
,
0x1
);
}
static
inline
unsigned
int
get_mail
(
void
)
{
unsigned
int
reg
;
poll_pmu_message_ready
();
reg
=
reg32_read
(
IP2APB_DDRPHY_IPS_BASE_ADDR
(
0
)
+
4
*
0xd0032
);
ack_pmu_message_recieve
();
return
reg
;
}
static
inline
unsigned
int
get_stream_message
(
void
)
{
unsigned
int
reg
,
reg2
;
poll_pmu_message_ready
();
reg
=
reg32_read
(
IP2APB_DDRPHY_IPS_BASE_ADDR
(
0
)
+
4
*
0xd0032
);
reg2
=
reg32_read
(
IP2APB_DDRPHY_IPS_BASE_ADDR
(
0
)
+
4
*
0xd0034
);
reg2
=
(
reg2
<<
16
)
|
reg
;
ack_pmu_message_recieve
();
return
reg2
;
}
static
inline
void
decode_major_message
(
unsigned
int
mail
)
{
ddr_printf
(
"[PMU Major message = 0x%08x]
\n
"
,
mail
);
}
static
inline
void
decode_streaming_message
(
void
)
{
unsigned
int
string_index
,
arg
__maybe_unused
;
int
i
=
0
;
string_index
=
get_stream_message
();
ddr_printf
(
" PMU String index = 0x%08x
\n
"
,
string_index
);
while
(
i
<
(
string_index
&
0xffff
)){
arg
=
get_stream_message
();
ddr_printf
(
" arg[%d] = 0x%08x
\n
"
,
i
,
arg
);
i
++
;
}
ddr_printf
(
"
\n
"
);
}
void
wait_ddrphy_training_complete
(
void
)
{
unsigned
int
mail
;
while
(
1
)
{
mail
=
get_mail
();
decode_major_message
(
mail
);
if
(
mail
==
0x08
)
{
decode_streaming_message
();
}
else
if
(
mail
==
0x07
)
{
/* Training PASS */
break
;
}
else
if
(
mail
==
0xff
)
{
printf
(
"Training FAILED
\n
"
);
break
;
}
}
}
configs/imx8m_lpddr4_800mhz_2gb_som_defconfig
0 → 100644
View file @
66b33569
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_EMCRAFT_IMX8M_LPDDR4_800MHZ_2GB_SOM=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg"
CONFIG_DEFAULT_FDT_FILE="emcraft-imx8m-som.dtb"
CONFIG_SPL=y
CONFIG_HUSH_PARSER=y
CONFIG_OF_LIBFDT=y
CONFIG_CMD_CACHE=y
CONFIG_DEFAULT_DEVICE_TREE="emcraft-imx8m-som"
CONFIG_OF_CONTROL=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_SYS_I2C_MXC=y
CONFIG_CMD_I2C=y
CONFIG_DM_I2C=y
CONFIG_DM_GPIO=y
CONFIG_CMD_GPIO=y
CONFIG_DM_MMC=y
# CONFIG_DM_MMC_OPS is not set
# CONFIG_BLK is not set
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_REGULATOR=y
CONFIG_DM_PMIC=y
CONFIG_POWER_BD71837=y
CONFIG_POWER_BD71837_I2C_BUS=0
CONFIG_POWER_BD71837_I2C_ADDR=0x4B
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_ETH=y
CONFIG_CMD_PMIC=y
CONFIG_NXP_TMU=y
CONFIG_DM_THERMAL=y
CONFIG_FIT=y
CONFIG_SPL_FIT=y
CONFIG_SPL_LOAD_FIT=y
include/configs/imx8m_som.h
View file @
66b33569
...
...
@@ -243,9 +243,11 @@
#elif defined(CONFIG_TARGET_EMCRAFT_IMX8M_LPDDR4_2GB_SOM)
#define PHYS_SDRAM_SIZE 0x80000000
/* 2GB LPDDR4 one Rank */
#elif defined(CONFIG_TARGET_EMCRAFT_IMX8M_LPDDR4_3GB_SOM)
#define PHYS_SDRAM_SIZE 0xc0000000
/*
2
GB LPDDR4 one Rank */
#define PHYS_SDRAM_SIZE 0xc0000000
/*
3
GB LPDDR4 one Rank */
#elif defined(CONFIG_TARGET_EMCRAFT_IMX8M_SOM)
#define PHYS_SDRAM_SIZE 0x20000000
/* 512MB DDR3L one Rank */
#elif defined(CONFIG_TARGET_EMCRAFT_IMX8M_LPDDR4_800MHZ_2GB_SOM)
#define PHYS_SDRAM_SIZE 0x80000000
/* 2GB LPDDR4 one Rank */
#else
#error "i.MX8M-SOM installed DDR size is not defined"
#endif
...
...
@@ -254,7 +256,7 @@
#define CONFIG_SYS_MEMTEST_START 0x40000000
/* Save upper 2MB for U-Boot code and data */
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
PHYS_SDRAM_SIZE - 2*1024*1024)
PHYS_SDRAM_SIZE -
3
2*1024*1024)
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_BAUDRATE 115200
...
...
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