Commit 682011ff authored by wdenk's avatar wdenk
Browse files

* Patches by Udi Finkelstein, 2 June 2003:

  - Added support for custom keyboards, initialized by defining a
    board-specific drv_keyboard_init as well as defining CONFIG_KEYBOARD .
  - Added support for the RBC823 board.
  - cpu/mpc8xx/lcd.c now automatically calculates the
    Horizontal Pixel Count field.

* Fix alignment problem in BOOTP (dhcp_leasetime option)
  [pointed out by Nicolas Lacressonnire, 2 Jun 2003]

* Patch by Mark Rakes, 14 May 2003:
  add support for Intel e1000 gig cards.

* Patch by Nye Liu, 3 Jun 2003:
  fix critical typo in MAMR definition (include/mpc8xx.h)

* Fix requirement to align U-Boot image on 16 kB boundaries on PPC.

* Patch by Klaus Heydeck, 2 Jun 2003
  Minor changes for KUP4K configuration
parent 7a8e9bed
...@@ -2,6 +2,27 @@ ...@@ -2,6 +2,27 @@
Changes since U-Boot 0.3.1: Changes since U-Boot 0.3.1:
====================================================================== ======================================================================
* Patches by Udi Finkelstein, 2 June 2003:
- Added support for custom keyboards, initialized by defining a
board-specific drv_keyboard_init as well as defining CONFIG_KEYBOARD .
- Added support for the RBC823 board.
- cpu/mpc8xx/lcd.c now automatically calculates the
Horizontal Pixel Count field.
* Fix alignment problem in BOOTP (dhcp_leasetime option)
[pointed out by Nicolas Lacressonnire, 2 Jun 2003]
* Patch by Mark Rakes, 14 May 2003:
add support for Intel e1000 gig cards.
* Patch by Nye Liu, 3 Jun 2003:
fix critical typo in MAMR definition (include/mpc8xx.h)
* Fix requirement to align U-Boot image on 16 kB boundaries on PPC.
* Patch by Klaus Heydeck, 2 Jun 2003
Minor changes for KUP4K configuration
* Patch by Marc Singer, 29 May 2003: * Patch by Marc Singer, 29 May 2003:
Fixed rarp boot method for IA32 and other little-endian CPUs. Fixed rarp boot method for IA32 and other little-endian CPUs.
......
...@@ -32,11 +32,11 @@ LIST_8xx=" \ ...@@ -32,11 +32,11 @@ LIST_8xx=" \
IVMS8 IVMS8_128 IVMS8_256 KUP4K \ IVMS8 IVMS8_128 IVMS8_256 KUP4K \
LANTEC lwmon MBX MBX860T \ LANTEC lwmon MBX MBX860T \
MHPC MVS1 NETVIA NX823 \ MHPC MVS1 NETVIA NX823 \
pcu_e R360MPI RPXClassic RPXlite \ pcu_e R360MPI RBC823 RPXClassic \
RRvision SM850 SPD823TS svm_sc8xx \ RPXlite RRvision SM850 SPD823TS \
SXNI855T TOP860 TQM823L TQM823L_LCD \ svm_sc8xx SXNI855T TOP860 TQM823L \
TQM850L TQM855L TQM860L TTTech \ TQM823L_LCD TQM850L TQM855L TQM860L \
v37 \ TTTech v37 \
" "
######################################################################### #########################################################################
......
...@@ -314,6 +314,9 @@ pcu_e_config: unconfig ...@@ -314,6 +314,9 @@ pcu_e_config: unconfig
R360MPI_config: unconfig R360MPI_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx r360mpi @./mkconfig $(@:_config=) ppc mpc8xx r360mpi
RBC823_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx rbc823
RPXClassic_config: unconfig RPXClassic_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx RPXClassic @./mkconfig $(@:_config=) ppc mpc8xx RPXClassic
......
...@@ -344,7 +344,7 @@ The following options need to be configured: ...@@ -344,7 +344,7 @@ The following options need to be configured:
CONFIG_IAD210, CONFIG_RPXlite, CONFIG_sbc8260, CONFIG_IAD210, CONFIG_RPXlite, CONFIG_sbc8260,
CONFIG_EBONY, CONFIG_sacsng, CONFIG_FPS860L, CONFIG_EBONY, CONFIG_sacsng, CONFIG_FPS860L,
CONFIG_V37, CONFIG_ELPT860, CONFIG_CMI, CONFIG_V37, CONFIG_ELPT860, CONFIG_CMI,
CONFIG_NETVIA CONFIG_NETVIA, CONFIG_RBC823
ARM based boards: ARM based boards:
----------------- -----------------
...@@ -688,6 +688,9 @@ The following options need to be configured: ...@@ -688,6 +688,9 @@ The following options need to be configured:
CFG_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz) CFG_SCSI_SYM53C8XX_CCF to fix clock timing (80Mhz)
- NETWORK Support (PCI): - NETWORK Support (PCI):
CONFIG_E1000
Support for Intel 8254x gigabit chips.
CONFIG_EEPRO100 CONFIG_EEPRO100
Support for Intel 82557/82559/82559ER chips. Support for Intel 82557/82559/82559ER chips.
Optional CONFIG_EEPRO100_SROM_WRITE enables eeprom Optional CONFIG_EEPRO100_SROM_WRITE enables eeprom
...@@ -766,6 +769,13 @@ The following options need to be configured: ...@@ -766,6 +769,13 @@ The following options need to be configured:
and 16bpp modes defined by CONFIG_VIDEO_SED13806_8BPP and 16bpp modes defined by CONFIG_VIDEO_SED13806_8BPP
or CONFIG_VIDEO_SED13806_16BPP or CONFIG_VIDEO_SED13806_16BPP
- Keyboard Support:
CONFIG_KEYBOARD
Define this to enable a custom keyboard support.
This simply calls drv_keyboard_init() which must be
defined in your board-specific files.
The only board using this so far is RBC823.
- LCD Support: CONFIG_LCD - LCD Support: CONFIG_LCD
......
...@@ -172,6 +172,9 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) ...@@ -172,6 +172,9 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
value = value|(value<<16); value = value|(value<<16);
switch (value) { switch (value) {
case AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
case FUJ_MANUFACT: case FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ; info->flash_id = FLASH_MAN_FUJ;
break; break;
...@@ -191,6 +194,16 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info) ...@@ -191,6 +194,16 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
info->sector_count = 19; info->sector_count = 19;
info->size = 0x00100000; info->size = 0x00100000;
break; /* => 1 MB */ break; /* => 1 MB */
case AMD_ID_LV800T:
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
info->size = 0x00200000;
break; /* => 2 MB */
case AMD_ID_LV800B:
info->flash_id += FLASH_AM800B;
info->sector_count = 19;
info->size = 0x00200000;
break; /* => 2 MB */
default: default:
info->flash_id = FLASH_UNKNOWN; info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */ return (0); /* => no or unknown flash */
......
...@@ -54,10 +54,7 @@ const uint sdram_table[] = ...@@ -54,10 +54,7 @@ const uint sdram_table[] =
/* /*
* Single Read. (Offset 0 in UPMA RAM) * Single Read. (Offset 0 in UPMA RAM)
*/ */
0x1F07FC04, 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
0xEEAEFC04,
0x11ADFC04,
0xEFBBBC00,
0x1FF77C47, /* last */ 0x1FF77C47, /* last */
/* /*
...@@ -68,57 +65,37 @@ const uint sdram_table[] = ...@@ -68,57 +65,37 @@ const uint sdram_table[] =
* sequence, which is executed by a RUN command. * sequence, which is executed by a RUN command.
* *
*/ */
0x1FF77C35, 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
0xEFEABC34,
0x1FB57C35, /* last */
/* /*
* Burst Read. (Offset 8 in UPMA RAM) * Burst Read. (Offset 8 in UPMA RAM)
*/ */
0x1F07FC04, 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
0xEEAEFC04, 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
0x10ADFC04,
0xF0AFFC00,
0xF0AFFC00,
0xF1AFFC00,
0xEFBBBC00,
0x1FF77C47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* /*
* Single Write. (Offset 18 in UPMA RAM) * Single Write. (Offset 18 in UPMA RAM)
*/ */
0x1F27FC04, 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
0xEEAEBC00,
0x01B93C04,
0x1FF77C47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* /*
* Burst Write. (Offset 20 in UPMA RAM) * Burst Write. (Offset 20 in UPMA RAM)
*/ */
0x1F07FC04, 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
0xEEAEBC00, 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
0x10AD7C00, _NOT_USED_,
0xF0AFFC00,
0xF0AFFC00,
0xE1BBBC04,
0x1FF77C47, /* last */
_NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* /*
* Refresh (Offset 30 in UPMA RAM) * Refresh (Offset 30 in UPMA RAM)
*/ */
0x1FF5FC84, 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
0xFFFFFC04, 0xFFFFFC84, 0xFFFFFC07, /* last */
0xFFFFFC04, _NOT_USED_, _NOT_USED_,
0xFFFFFC04,
0xFFFFFC84,
0xFFFFFC07, /* last */
_NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* /*
...@@ -146,89 +123,96 @@ int checkboard (void) ...@@ -146,89 +123,96 @@ int checkboard (void)
long int initdram (int board_type) long int initdram (int board_type)
{ {
volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl; volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size_b0 = 0; long int size_b0 = 0;
long int size_b1 = 0; long int size_b1 = 0;
long int size_b2 = 0; long int size_b2 = 0;
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
/*
* Preliminary prescaler for refresh (depends on number of
* banks): This value is selected for four cycles every 62.4 us
* with two SDRAM banks or four cycles every 31.2 us with one
* bank. It will be adjusted after memory sizing.
*/
memctl->memc_mptpr = CFG_MPTPR;
memctl->memc_mar = 0x00000088;
/*
* Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at
* preliminary addresses - these have to be modified after the
* SDRAM size has been determined.
*/
/* memctl->memc_or1 = CFG_OR1_PRELIM; */
/* memctl->memc_br1 = CFG_BR1_PRELIM; */
/* memctl->memc_or2 = CFG_OR2_PRELIM; */
/* memctl->memc_br2 = CFG_BR2_PRELIM; */
upmconfig (UPMA, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint));
memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ /*
* Preliminary prescaler for refresh (depends on number of
* banks): This value is selected for four cycles every 62.4 us
* with two SDRAM banks or four cycles every 31.2 us with one
* bank. It will be adjusted after memory sizing.
*/
memctl->memc_mptpr = CFG_MPTPR;
udelay(200); memctl->memc_mar = 0x00000088;
/* perform SDRAM initializsation sequence */ /*
* Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at
* preliminary addresses - these have to be modified after the
* SDRAM size has been determined.
*/
/* memctl->memc_or1 = CFG_OR1_PRELIM; */
/* memctl->memc_br1 = CFG_BR1_PRELIM; */
/* memctl->memc_or2 = CFG_OR2_PRELIM; */
/* memctl->memc_br2 = CFG_BR2_PRELIM; */
memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
udelay(1);
memctl->memc_mcr = 0x80002830; /* SDRAM bank 0 - execute twice */
udelay(1);
memctl->memc_mcr = 0x80002106; /* SDRAM bank 0 - RUN MRS Pattern from loc 6 */
udelay(1);
memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */ memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
udelay(1);
memctl->memc_mcr = 0x80004830; /* SDRAM bank 1 - execute twice */
udelay(1);
memctl->memc_mcr = 0x80004106; /* SDRAM bank 1 - RUN MRS Pattern from loc 6 */
udelay(1);
memctl->memc_mcr = 0x80006105; /* SDRAM bank 2 */ udelay (200);
udelay(1);
memctl->memc_mcr = 0x80006830; /* SDRAM bank 2 - execute twice */
udelay(1);
memctl->memc_mcr = 0x80006106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
udelay(1);
/* perform SDRAM initializsation sequence */
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
udelay (1);
memctl->memc_mcr = 0x80002830; /* SDRAM bank 0 - execute twice */
udelay (1);
memctl->memc_mcr = 0x80002106; /* SDRAM bank 0 - RUN MRS Pattern from loc 6 */
udelay (1);
udelay (1000); memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */
udelay (1);
memctl->memc_mcr = 0x80004830; /* SDRAM bank 1 - execute twice */
udelay (1);
memctl->memc_mcr = 0x80004106; /* SDRAM bank 1 - RUN MRS Pattern from loc 6 */
udelay (1);
size_b0 = 0x00800000; memctl->memc_mcr = 0x80006105; /* SDRAM bank 2 */
size_b1 = 0x00800000; udelay (1);
size_b2 = 0x00800000; memctl->memc_mcr = 0x80006830; /* SDRAM bank 2 - execute twice */
udelay (1);
memctl->memc_mcr = 0x80006106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
udelay (1);
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
udelay (1000);
#if 0 /* 3 x 8MB */
size_b0 = 0x00800000;
size_b1 = 0x00800000;
size_b2 = 0x00800000;
memctl->memc_mptpr = CFG_MPTPR; memctl->memc_mptpr = CFG_MPTPR;
udelay(1000); udelay (1000);
memctl->memc_or1 = 0xFF800A00; memctl->memc_or1 = 0xFF800A00;
memctl->memc_br1 = 0x00000081; memctl->memc_br1 = 0x00000081;
memctl->memc_or2 = 0xFF000A00;
memctl->memc_or2 = 0xFF000A00; memctl->memc_br2 = 0x00800081;
memctl->memc_br2 = 0x00800081;
memctl->memc_or3 = 0xFE000A00; memctl->memc_or3 = 0xFE000A00;
memctl->memc_br3 = 0x01000081; memctl->memc_br3 = 0x01000081;
#else /* 3 x 16 MB */
size_b0 = 0x01000000;
size_b1 = 0x01000000;
size_b2 = 0x01000000;
memctl->memc_mptpr = CFG_MPTPR;
udelay (1000);
memctl->memc_or1 = 0xFF000A00;
memctl->memc_br1 = 0x00000081;
memctl->memc_or2 = 0xFE000A00;
memctl->memc_br2 = 0x01000081;
memctl->memc_or3 = 0xFC000A00;
memctl->memc_br3 = 0x02000081;
#endif
udelay(10000); udelay (10000);
return (size_b0 + size_b1 + size_b2); return (size_b0 + size_b1 + size_b2);
} }
/* ------------------------------------------------------------------------- */ /* ------------------------------------------------------------------------- */
...@@ -241,46 +225,47 @@ long int initdram (int board_type) ...@@ -241,46 +225,47 @@ long int initdram (int board_type)
* - short between data lines * - short between data lines
*/ */
#if 0 #if 0
static long int dram_size (long int mamr_value, long int *base, long int maxsize) static long int dram_size (long int mamr_value, long int *base,
long int maxsize)
{ {
volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl; volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr; volatile long int *addr;
ulong cnt, val; ulong cnt, val;
ulong save[32]; /* to make test non-destructive */ ulong save[32]; /* to make test non-destructive */
unsigned char i = 0; unsigned char i = 0;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) { memctl->memc_mamr = mamr_value;
addr = base + cnt; /* pointer arith! */
val = *addr; for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
*addr = save[--i]; addr = base + cnt; /* pointer arith! */
if (val != (~cnt)) { save[i++] = *addr;
return (cnt * sizeof(long)); *addr = ~cnt;
} }
}
return (maxsize); /* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof (long));
}
}
return (maxsize);
} }
#endif #endif
...@@ -289,155 +274,175 @@ int misc_init_r (void) ...@@ -289,155 +274,175 @@ int misc_init_r (void)
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_STATUS_LED #ifdef CONFIG_STATUS_LED
volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile immap_t *immap = (immap_t *) CFG_IMMR;
#endif #endif
#ifdef CONFIG_KUP4K_LOGO #ifdef CONFIG_KUP4K_LOGO
bd_t *bd = gd->bd; bd_t *bd = gd->bd;
lcd_logo(bd); lcd_logo (bd);
#endif /* CONFIG_KUP4K_LOGO */ #endif /* CONFIG_KUP4K_LOGO */
#ifdef CONFIG_IDE_LED #ifdef CONFIG_IDE_LED
/* Configure PA8 as output port */ /* Configure PA8 as output port */
immap->im_ioport.iop_padir |= 0x80; immap->im_ioport.iop_padir |= 0x80;
immap->im_ioport.iop_paodr |= 0x80; immap->im_ioport.iop_paodr |= 0x80;
immap->im_ioport.iop_papar &= ~0x80; immap->im_ioport.iop_papar &= ~0x80;
immap->im_ioport.iop_padat |= 0x80; /* turn it off */ immap->im_ioport.iop_padat |= 0x80; /* turn it off */
#endif #endif
return(0); return (0);
} }
#ifdef CONFIG_KUP4K_LOGO #ifdef CONFIG_KUP4K_LOGO
void lcd_logo(bd_t *bd){
FB_INFO_S1D13xxx fb_info;
S1D_INDEX s1dReg; #define PB_LCD_PWM ((uint)0x00004000) /* PB 17 */
S1D_VALUE s1dValue;
volatile immap_t *immr = (immap_t *)CFG_IMMR; void lcd_logo (bd_t * bd)
volatile memctl8xx_t *memctl; {
volatile immap_t *immap = (immap_t *) CFG_IMMR;
FB_INFO_S1D13xxx fb_info;
S1D_INDEX s1dReg;
S1D_VALUE s1dValue;
volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl;
ushort i; ushort i;
uchar *fb; uchar *fb;
int rs, gs, bs; int rs, gs, bs;
int r = 8, g = 8, b = 4; int r = 8, g = 8, b = 4;
int r1,g1,b1; int r1, g1, b1;
immr->im_cpm.cp_pbpar &= ~PB_LCD_PWM;
immr->im_cpm.cp_pbodr &= ~PB_LCD_PWM;
immr->im_cpm.cp_pbdat &= ~PB_LCD_PWM; /* set to 0 = enabled */
immr->im_cpm.cp_pbdir |= PB_LCD_PWM;
/*----------------------------------------------------------------------------- */ /*----------------------------------------------------------------------------- */
/**/ /**/
/* Initialize the chip and the frame buffer driver. */ /* Initialize the chip and the frame buffer driver. */
/**/ /**/
/*----------------------------------------------------------------------------- */ /*----------------------------------------------------------------------------- */
memctl = &immr->im_memctl; memctl = &immr->im_memctl;
/* memctl->memc_or5 = 0xFFC007F0; / * 4 MB 17 WS or externel TA */ /* memctl->memc_or5 = 0xFFC007F0; / * 4 MB 17 WS or externel TA */
/* memctl->memc_br5 = 0x80000801; / * Start at 0x80000000 */ /* memctl->memc_br5 = 0x80000801; / * Start at 0x80000000 */
memctl->memc_or5 = 0xFFC00708; /* 4 MB 17 WS or externel TA */ memctl->memc_or5 = 0xFFC00708; /* 4 MB 17 WS or externel TA */
memctl->memc_br5 = 0x80080801; /* Start at 0x80080000 */ memctl->memc_br5 = 0x80080801; /* Start at 0x80080000 */