Commit 68cebb80 authored by Shinya Kuribayashi's avatar Shinya Kuribayashi
Browse files

MIPS: Move timer code to arch/mips/cpu/$(CPU)/



Current timer routines (arch/mips/lib/timer.c) are implemented assuming
that MIPS32 coprocessor (CP0) resources, Counter and Compare registers
in this case, are available.  But this doesn't always work.

We need to make sure that all MIPS-based systems don't necessarily use
CP0 counter/compare registers as time keeping resources.  And some MIPS
variant processors might come with different hardware specs with genuine
MIPS32 CP0 registers.

With this change, each $(CPU)/ directory can have its own timer code.
Signed-off-by: default avatarShinya Kuribayashi <skuribay@pobox.com>
parent 660da094
......@@ -27,7 +27,7 @@ LIB = $(obj)lib$(CPU).o
START = start.o
SOBJS-y = cache.o
COBJS-y = cpu.o interrupts.o
COBJS-y = cpu.o interrupts.o time.o
SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
......
......@@ -33,7 +33,6 @@ COBJS-y += bootm_qemu_mips.o
else
COBJS-y += bootm.o
endif
COBJS-y += time.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
......
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