Commit 6bb5b412 authored by Kumar Gala's avatar Kumar Gala
Browse files

85xx: Report which "bank" of NOR flash we are booting from on FSL boards



The p2020DS, MPC8536DS, MPC8572DS, MPC8544DS boards are capable of
swizzling the upper address bits of the NOR flash we boot out of which
creates the concept of "virtual" banks.  This is useful in that we can
flash a test of image of u-boot and reset to one of the virtual banks
while still maintaining a working image in "bank 0".

The PIXIS FPGA exposes registers on LBC which we can use to determine
which "bank" we are booting out of (as well as setting which bank to
boot out of).
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 9af9c6bd
......@@ -60,10 +60,41 @@ int board_early_init_f (void)
int checkboard (void)
{
printf ("Board: MPC8536DS, System ID: 0x%02x, "
"System Version: 0x%02x, FPGA Version: 0x%02x\n",
in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
in8(PIXIS_BASE + PIXIS_PVER));
u8 vboot;
u8 *pixis_base = (u8 *)PIXIS_BASE;
puts("Board: MPC8536DS ");
#ifdef CONFIG_PHYS_64BIT
puts("(36-bit addrmap) ");
#endif
printf ("Sys ID: 0x%02x, "
"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
in_8(pixis_base + PIXIS_PVER));
vboot = in_8(pixis_base + PIXIS_VBOOT);
switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
case PIXIS_VBOOT_LBMAP_NOR0:
puts ("vBank: 0\n");
break;
case PIXIS_VBOOT_LBMAP_NOR1:
puts ("vBank: 1\n");
break;
case PIXIS_VBOOT_LBMAP_NOR2:
puts ("vBank: 2\n");
break;
case PIXIS_VBOOT_LBMAP_NOR3:
puts ("vBank: 3\n");
break;
case PIXIS_VBOOT_LBMAP_PJET:
puts ("Promjet\n");
break;
case PIXIS_VBOOT_LBMAP_NAND:
puts ("NAND\n");
break;
}
return 0;
}
......
......@@ -43,14 +43,22 @@ int checkboard (void)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
u8 vboot;
u8 *pixis_base = (u8 *)PIXIS_BASE;
if ((uint)&gur->porpllsr != 0xe00e0000) {
printf("immap size error %lx\n",(ulong)&gur->porpllsr);
}
printf ("Board: MPC8544DS, System ID: 0x%02x, "
"System Version: 0x%02x, FPGA Version: 0x%02x\n",
in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
in8(PIXIS_BASE + PIXIS_PVER));
printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
in_8(pixis_base + PIXIS_PVER));
vboot = in_8(pixis_base + PIXIS_VBOOT);
if (vboot & PIXIS_VBOOT_FMAP)
printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
else
puts ("Promjet\n");
lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
......
......@@ -42,14 +42,34 @@ long int fixed_sdram(void);
int checkboard (void)
{
u8 vboot;
u8 *pixis_base = (u8 *)PIXIS_BASE;
puts ("Board: MPC8572DS ");
#ifdef CONFIG_PHYS_64BIT
puts ("(36-bit addrmap) ");
#endif
printf ("Sys ID: 0x%02x, "
"Sys Ver: 0x%02x, FPGA Ver: 0x%02x\n",
in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
in8(PIXIS_BASE + PIXIS_PVER));
"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
in_8(pixis_base + PIXIS_PVER));
vboot = in_8(pixis_base + PIXIS_VBOOT);
switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) {
case PIXIS_VBOOT_LBMAP_NOR0:
puts ("vBank: 0\n");
break;
case PIXIS_VBOOT_LBMAP_PJET:
puts ("Promjet\n");
break;
case PIXIS_VBOOT_LBMAP_NAND:
puts ("NAND\n");
break;
case PIXIS_VBOOT_LBMAP_NOR1:
puts ("vBank: 1\n");
break;
}
return 0;
}
......
......@@ -47,14 +47,31 @@ phys_size_t fixed_sdram(void);
int checkboard(void)
{
u8 sw7;
u8 *pixis_base = (u8 *)PIXIS_BASE;
puts("Board: P2020DS ");
#ifdef CONFIG_PHYS_64BIT
puts("(36-bit addrmap) ");
#endif
printf("Sys ID: 0x%02x, "
"Sys Ver: 0x%02x, FPGA Ver: 0x%02x\n",
in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
in8(PIXIS_BASE + PIXIS_PVER));
"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
in_8(pixis_base + PIXIS_PVER));
sw7 = in_8(pixis_base + PIXIS_SW(7));
switch ((sw7 & PIXIS_SW7_LBMAP) >> 6) {
case 0:
case 1:
printf ("vBank: %d\n", ((sw7 & PIXIS_SW7_VBANK) >> 4));
break;
case 2:
case 3:
puts ("Promjet\n");
break;
}
return 0;
}
......
......@@ -218,6 +218,13 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
#define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */
#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
#define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */
#define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */
#define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */
#define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */
#define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */
#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
......
......@@ -192,6 +192,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
#define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
#define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
......
......@@ -237,6 +237,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
#define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */
#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
#define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */
#define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */
#define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */
#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
......
......@@ -282,6 +282,11 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
#define PIXIS_VWATCH 0x24 /* Watchdog Register */
#define PIXIS_LED 0x25 /* LED Register */
#define PIXIS_SW(x) 0x20 + (x - 1) * 2
#define PIXIS_EN(x) 0x21 + (x - 1) * 2
#define PIXIS_SW7_LBMAP 0xc0 /* SW7 - cfg_lbmap */
#define PIXIS_SW7_VBANK 0x30 /* SW7 - cfg_vbank */
/* old pixis referenced names */
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment