Commit 6c4a1eba authored by Yao Yuan's avatar Yao Yuan Committed by York Sun
Browse files

armv7/fsl-ls102xa: Workaround for DDR erratum A008514

This is a workaround for hardware erratum.
Write the value of 63b2_0042h to EDDRTQCFG will optimal the
memory controller performance.

The value: 63b2_0042h comes from the hardware team.
Signed-off-by: default avatarYuan Yao <>
Reviewed-by: default avatarYork Sun <>
parent 0b8bc631
......@@ -76,5 +76,15 @@ int arch_soc_init(void)
* Memory controller require a register write before being enabled.
* Affects: DDR
* Register: EDDRTQCFG
* Description: Memory controller performance is not optimal with
* default internal target queue register values.
* Workaround: Write a value of 63b2_0042h to address: 157_020Ch.
out_be32(&scfg->eddrtqcfg, 0x63b20042);
return 0;
......@@ -230,7 +230,7 @@ struct ccsr_scfg {
u32 scfgrevcr;
u32 coresrencr;
u32 pex2pmrdsr;
u32 ddrc1cr;
u32 eddrtqcfg;
u32 ddrc2cr;
u32 ddrc3cr;
u32 ddrc4cr;
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment