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Commit 6d0f6bcf authored by Jean-Christophe PLAGNIOL-VILLARD's avatar Jean-Christophe PLAGNIOL-VILLARD Committed by Wolfgang Denk
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rename CFG_ macros to CONFIG_SYS 


Signed-off-by: default avatarJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
parent 71edc271
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Makefile
View file @ 6d0f6bcf
......@@ -1701,7 +1701,7 @@ ISPAN_config \
ISPAN_REVB_config: unconfig
@mkdir -p $(obj)include
@if [ "$(findstring _REVB_,$@)" ] ; then \
echo "#define CFG_REV_B" > $(obj)include/config.h ; \
echo "#define CONFIG_SYS_REV_B" > $(obj)include/config.h ; \
fi
@$(MKCONFIG) -a ISPAN ppc mpc8260 ispan
......@@ -1728,8 +1728,8 @@ PQ2FADS-ZU_66MHz_lowboot_config \
@mkdir -p $(obj)include
@mkdir -p $(obj)board/freescale/mpc8260ads
$(if $(findstring PQ2FADS,$@), \
@echo "#define CONFIG_ADSTYPE CFG_PQ2FADS" > $(obj)include/config.h, \
@echo "#define CONFIG_ADSTYPE CFG_"$(subst MPC,,$(word 1,$(subst _, ,$@))) > $(obj)include/config.h)
@echo "#define CONFIG_ADSTYPE CONFIG_SYS_PQ2FADS" > $(obj)include/config.h, \
@echo "#define CONFIG_ADSTYPE CONFIG_SYS_"$(subst MPC,,$(word 1,$(subst _, ,$@))) > $(obj)include/config.h)
$(if $(findstring MHz,$@), \
@echo "#define CONFIG_8260_CLKIN" $(subst MHz,,$(word 2,$(subst _, ,$@)))"000000" >> $(obj)include/config.h, \
$(if $(findstring VR,$@), \
......@@ -1981,19 +1981,19 @@ M54451EVB_stmicro_config : unconfig
M54451EVB_stmicro_config) FLASH=STMICRO;; \
esac; \
if [ "$${FLASH}" = "SPANSION" ] ; then \
echo "#define CFG_SPANSION_BOOT" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_SPANSION_BOOT" >> $(obj)include/config.h ; \
echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54451evb/config.tmp ; \
cp $(obj)board/freescale/m54451evb/u-boot.spa $(obj)board/freescale/m54451evb/u-boot.lds ; \
$(XECHO) "... with SPANSION boot..." ; \
fi; \
if [ "$${FLASH}" = "STMICRO" ] ; then \
echo "#define CONFIG_CF_SBF" >> $(obj)include/config.h ; \
echo "#define CFG_STMICRO_BOOT" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_STMICRO_BOOT" >> $(obj)include/config.h ; \
echo "TEXT_BASE = 0x47E00000" > $(obj)board/freescale/m54451evb/config.tmp ; \
cp $(obj)board/freescale/m54451evb/u-boot.stm $(obj)board/freescale/m54451evb/u-boot.lds ; \
$(XECHO) "... with ST Micro boot..." ; \
fi; \
echo "#define CFG_INPUT_CLKSRC 24000000" >> $(obj)include/config.h ;
echo "#define CONFIG_SYS_INPUT_CLKSRC 24000000" >> $(obj)include/config.h ;
@$(MKCONFIG) -a M54451EVB m68k mcf5445x m54451evb freescale
M54455EVB_config \
......@@ -2015,25 +2015,25 @@ M54455EVB_stm33_config : unconfig
M54455EVB_stm33_config) FLASH=STMICRO; FREQ=33333333;; \
esac; \
if [ "$${FLASH}" = "INTEL" ] ; then \
echo "#define CFG_INTEL_BOOT" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_INTEL_BOOT" >> $(obj)include/config.h ; \
echo "TEXT_BASE = 0x00000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
cp $(obj)board/freescale/m54455evb/u-boot.int $(obj)board/freescale/m54455evb/u-boot.lds ; \
$(XECHO) "... with INTEL boot..." ; \
fi; \
if [ "$${FLASH}" = "ATMEL" ] ; then \
echo "#define CFG_ATMEL_BOOT" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_ATMEL_BOOT" >> $(obj)include/config.h ; \
echo "TEXT_BASE = 0x04000000" > $(obj)board/freescale/m54455evb/config.tmp ; \
cp $(obj)board/freescale/m54455evb/u-boot.atm $(obj)board/freescale/m54455evb/u-boot.lds ; \
$(XECHO) "... with ATMEL boot..." ; \
fi; \
if [ "$${FLASH}" = "STMICRO" ] ; then \
echo "#define CONFIG_CF_SBF" >> $(obj)include/config.h ; \
echo "#define CFG_STMICRO_BOOT" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_STMICRO_BOOT" >> $(obj)include/config.h ; \
echo "TEXT_BASE = 0x4FE00000" > $(obj)board/freescale/m54455evb/config.tmp ; \
cp $(obj)board/freescale/m54455evb/u-boot.stm $(obj)board/freescale/m54455evb/u-boot.lds ; \
$(XECHO) "... with ST Micro boot..." ; \
fi; \
echo "#define CFG_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_INPUT_CLKSRC $${FREQ}" >> $(obj)include/config.h ; \
$(XECHO) "... with $${FREQ}Hz input clock"
@$(MKCONFIG) -a M54455EVB m68k mcf5445x m54455evb freescale
......@@ -2053,20 +2053,20 @@ M5475GFE_config : unconfig
M5475FFE_config) BOOT=2;CODE=32;VID=1;USB=1;RAM=64;RAM1=64;; \
M5475GFE_config) BOOT=4;CODE=0;VID=0;USB=0;RAM=64;RAM1=0;; \
esac; \
echo "#define CFG_BUSCLK 133333333" > $(obj)include/config.h ; \
echo "#define CFG_BOOTSZ $${BOOT}" >> $(obj)include/config.h ; \
echo "#define CFG_DRAMSZ $${RAM}" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_BUSCLK 133333333" > $(obj)include/config.h ; \
echo "#define CONFIG_SYS_BOOTSZ $${BOOT}" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_DRAMSZ $${RAM}" >> $(obj)include/config.h ; \
if [ "$${RAM1}" != "0" ] ; then \
echo "#define CFG_DRAMSZ1 $${RAM1}" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_DRAMSZ1 $${RAM1}" >> $(obj)include/config.h ; \
fi; \
if [ "$${CODE}" != "0" ] ; then \
echo "#define CFG_NOR1SZ $${CODE}" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_NOR1SZ $${CODE}" >> $(obj)include/config.h ; \
fi; \
if [ "$${VID}" == "1" ] ; then \
echo "#define CFG_VIDEO" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_VIDEO" >> $(obj)include/config.h ; \
fi; \
if [ "$${USB}" == "1" ] ; then \
echo "#define CFG_USBCTRL" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_USBCTRL" >> $(obj)include/config.h ; \
fi
@$(MKCONFIG) -a M5475EVB m68k mcf547x_8x m547xevb freescale
......@@ -2088,20 +2088,20 @@ M5485HFE_config : unconfig
M5485GFE_config) BOOT=4;CODE=0;VID=0;USB=0;RAM=64;RAM1=0;; \
M5485HFE_config) BOOT=2;CODE=16;VID=1;USB=0;RAM=64;RAM1=0;; \
esac; \
echo "#define CFG_BUSCLK 100000000" > $(obj)include/config.h ; \
echo "#define CFG_BOOTSZ $${BOOT}" >> $(obj)include/config.h ; \
echo "#define CFG_DRAMSZ $${RAM}" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_BUSCLK 100000000" > $(obj)include/config.h ; \
echo "#define CONFIG_SYS_BOOTSZ $${BOOT}" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_DRAMSZ $${RAM}" >> $(obj)include/config.h ; \
if [ "$${RAM1}" != "0" ] ; then \
echo "#define CFG_DRAMSZ1 $${RAM1}" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_DRAMSZ1 $${RAM1}" >> $(obj)include/config.h ; \
fi; \
if [ "$${CODE}" != "0" ] ; then \
echo "#define CFG_NOR1SZ $${CODE}" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_NOR1SZ $${CODE}" >> $(obj)include/config.h ; \
fi; \
if [ "$${VID}" == "1" ] ; then \
echo "#define CFG_VIDEO" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_VIDEO" >> $(obj)include/config.h ; \
fi; \
if [ "$${USB}" == "1" ] ; then \
echo "#define CFG_USBCTRL" >> $(obj)include/config.h ; \
echo "#define CONFIG_SYS_USBCTRL" >> $(obj)include/config.h ; \
fi
@$(MKCONFIG) -a M5485EVB m68k mcf547x_8x m548xevb freescale
......@@ -2120,11 +2120,11 @@ MPC8313ERDB_NAND_66_config: unconfig
@mkdir -p $(obj)board/freescale/mpc8313erdb
@if [ "$(findstring _33_,$@)" ] ; then \
$(XECHO) -n "...33M ..." ; \
echo "#define CFG_33MHZ" >>$(obj)include/config.h ; \
echo "#define CONFIG_SYS_33MHZ" >>$(obj)include/config.h ; \
fi ; \
if [ "$(findstring _66_,$@)" ] ; then \
$(XECHO) -n "...66M..." ; \
echo "#define CFG_66MHZ" >>$(obj)include/config.h ; \
echo "#define CONFIG_SYS_66MHZ" >>$(obj)include/config.h ; \
fi ; \
if [ "$(findstring _NAND_,$@)" ] ; then \
$(XECHO) -n "...NAND..." ; \
......
README
View file @ 6d0f6bcf
This diff is collapsed.
doc/README.nios_CFG_NIOS_CPU → README.nios_CONFIG_SYS_NIOS_CPU
View file @ 6d0f6bcf
......@@ -11,117 +11,117 @@ Symbols beginning with a '[ptf]:' are coming from your SOPC sytem description
C O R E N I O S S D K [1],[7]
-------------------------------------------------------------------------------
CFG_NIOS_CPU_CLK nasys_clock_freq
CFG_NIOS_CPU_ICACHE nasys_icache_size
CFG_NIOS_CPU_DCACHE nasys_dcache_size
CFG_NIOS_CPU_REG_NUMS nasys_nios_num_regs
CFG_NIOS_CPU_MUL __nios_use_multiply__
CFG_NIOS_CPU_MSTEP __nios_use_mstep__
CFG_NIOS_CPU_STACK nasys_stack_top
CFG_NIOS_CPU_VEC_BASE nasys_vector_table
CFG_NIOS_CPU_VEC_SIZE nasys_vector_table_size
CFG_NIOS_CPU_VEC_NUMS
CFG_NIOS_CPU_RST_VECT nasys_reset_address
CFG_NIOS_CPU_DBG_CORE nasys_debug_core
CFG_NIOS_CPU_RAM_BASE na_onchip_ram_64_kbytes
CFG_NIOS_CPU_RAM_SIZE na_onchip_ram_64_kbytes_size
CFG_NIOS_CPU_ROM_BASE na_boot_monitor_rom
CFG_NIOS_CPU_ROM_SIZE na_boot_monitor_rom_size
CFG_NIOS_CPU_OCI_BASE nasys_oci_core
CFG_NIOS_CPU_OCI_SIZE
CFG_NIOS_CPU_SRAM_BASE na_ext_ram nasys_program_mem
CONFIG_SYS_NIOS_CPU_CLK nasys_clock_freq
CONFIG_SYS_NIOS_CPU_ICACHE nasys_icache_size
CONFIG_SYS_NIOS_CPU_DCACHE nasys_dcache_size
CONFIG_SYS_NIOS_CPU_REG_NUMS nasys_nios_num_regs
CONFIG_SYS_NIOS_CPU_MUL __nios_use_multiply__
CONFIG_SYS_NIOS_CPU_MSTEP __nios_use_mstep__
CONFIG_SYS_NIOS_CPU_STACK nasys_stack_top
CONFIG_SYS_NIOS_CPU_VEC_BASE nasys_vector_table
CONFIG_SYS_NIOS_CPU_VEC_SIZE nasys_vector_table_size
CONFIG_SYS_NIOS_CPU_VEC_NUMS
CONFIG_SYS_NIOS_CPU_RST_VECT nasys_reset_address
CONFIG_SYS_NIOS_CPU_DBG_CORE nasys_debug_core
CONFIG_SYS_NIOS_CPU_RAM_BASE na_onchip_ram_64_kbytes
CONFIG_SYS_NIOS_CPU_RAM_SIZE na_onchip_ram_64_kbytes_size
CONFIG_SYS_NIOS_CPU_ROM_BASE na_boot_monitor_rom
CONFIG_SYS_NIOS_CPU_ROM_SIZE na_boot_monitor_rom_size
CONFIG_SYS_NIOS_CPU_OCI_BASE nasys_oci_core
CONFIG_SYS_NIOS_CPU_OCI_SIZE
CONFIG_SYS_NIOS_CPU_SRAM_BASE na_ext_ram nasys_program_mem
nasys_data_mem
CFG_NIOS_CPU_SRAM_SIZE na_ext_ram_size nasys_program_mem_size
CONFIG_SYS_NIOS_CPU_SRAM_SIZE na_ext_ram_size nasys_program_mem_size
nasys_data_mem_size
CFG_NIOS_CPU_SDRAM_BASE na_sdram
CFG_NIOS_CPU_SDRAM_SIZE na_sdram_size
CFG_NIOS_CPU_FLASH_BASE na_ext_flash nasys_main_flash
CONFIG_SYS_NIOS_CPU_SDRAM_BASE na_sdram
CONFIG_SYS_NIOS_CPU_SDRAM_SIZE na_sdram_size
CONFIG_SYS_NIOS_CPU_FLASH_BASE na_ext_flash nasys_main_flash
nasys_am29lv065d_flash_0
nasys_flash_0
CFG_NIOS_CPU_FLASH_SIZE na_ext_flash_size nasys_main_flash_size
CONFIG_SYS_NIOS_CPU_FLASH_SIZE na_ext_flash_size nasys_main_flash_size
T I M E R N I O S S D K [3]
-------------------------------------------------------------------------------
CFG_NIOS_CPU_TIMER_NUMS nasys_timer_count
CFG_NIOS_CPU_TIMER[0-9] nasys_timer_[0-9]
CFG_NIOS_CPU_TIMER[0-9]_IRQ nasys_timer_[0-9]_irq
CFG_NIOS_CPU_TIMER[0-9]_PER [ptf]:period
CONFIG_SYS_NIOS_CPU_TIMER_NUMS nasys_timer_count
CONFIG_SYS_NIOS_CPU_TIMER[0-9] nasys_timer_[0-9]
CONFIG_SYS_NIOS_CPU_TIMER[0-9]_IRQ nasys_timer_[0-9]_irq
CONFIG_SYS_NIOS_CPU_TIMER[0-9]_PER [ptf]:period
[ptf]:period_units
[ptf]:mult
CFG_NIOS_CPU_TIMER[0-9]_AR [ptf]:always_run
CFG_NIOS_CPU_TIMER[0-9]_FP [ptf]:fixed_period
CFG_NIOS_CPU_TIMER[0-9]_SS [ptf]:snapshot
CONFIG_SYS_NIOS_CPU_TIMER[0-9]_AR [ptf]:always_run
CONFIG_SYS_NIOS_CPU_TIMER[0-9]_FP [ptf]:fixed_period
CONFIG_SYS_NIOS_CPU_TIMER[0-9]_SS [ptf]:snapshot
U A R T N I O S S D K [2]
-------------------------------------------------------------------------------
CFG_NIOS_CPU_UART_NUMS nasys_uart_count
CFG_NIOS_CPU_UART[0-9] nasys_uart_[0-9]
CFG_NIOS_CPU_UART[0-9]_IRQ nasys_uart_[0-9]_irq
CFG_NIOS_CPU_UART[0-9]_BR [ptf]:baud
CFG_NIOS_CPU_UART[0-9]_DB [ptf]:data_bits
CFG_NIOS_CPU_UART[0-9]_SB [ptf]:stop_bits
CFG_NIOS_CPU_UART[0-9]_PA [ptf]:parity
CFG_NIOS_CPU_UART[0-9]_HS [ptf]:use_cts_rts
CFG_NIOS_CPU_UART[0-9]_EOP [ptf]:use_eop_register
CONFIG_SYS_NIOS_CPU_UART_NUMS nasys_uart_count
CONFIG_SYS_NIOS_CPU_UART[0-9] nasys_uart_[0-9]
CONFIG_SYS_NIOS_CPU_UART[0-9]_IRQ nasys_uart_[0-9]_irq
CONFIG_SYS_NIOS_CPU_UART[0-9]_BR [ptf]:baud
CONFIG_SYS_NIOS_CPU_UART[0-9]_DB [ptf]:data_bits
CONFIG_SYS_NIOS_CPU_UART[0-9]_SB [ptf]:stop_bits
CONFIG_SYS_NIOS_CPU_UART[0-9]_PA [ptf]:parity
CONFIG_SYS_NIOS_CPU_UART[0-9]_HS [ptf]:use_cts_rts
CONFIG_SYS_NIOS_CPU_UART[0-9]_EOP [ptf]:use_eop_register
P I O N I O S S D K [4]
-------------------------------------------------------------------------------
CFG_NIOS_CPU_PIO_NUMS nasys_pio_count
CFG_NIOS_CPU_PIO[0-9] nasys_pio_[0-9]
CFG_NIOS_CPU_PIO[0-9]_IRQ nasys_pio_[0-9]_irq
CFG_NIOS_CPU_PIO[0-9]_BITS [ptf]:Data_Width
CFG_NIOS_CPU_PIO[0-9]_TYPE [ptf]:has_tri
CONFIG_SYS_NIOS_CPU_PIO_NUMS nasys_pio_count
CONFIG_SYS_NIOS_CPU_PIO[0-9] nasys_pio_[0-9]
CONFIG_SYS_NIOS_CPU_PIO[0-9]_IRQ nasys_pio_[0-9]_irq
CONFIG_SYS_NIOS_CPU_PIO[0-9]_BITS [ptf]:Data_Width
CONFIG_SYS_NIOS_CPU_PIO[0-9]_TYPE [ptf]:has_tri
[ptf]:has_out
[ptf]:has_in
CFG_NIOS_CPU_PIO[0-9]_CAP [ptf]:capture
CFG_NIOS_CPU_PIO[0-9]_EDGE [ptf]:edge_type
CFG_NIOS_CPU_PIO[0-9]_ITYPE [ptf]:irq_type
CONFIG_SYS_NIOS_CPU_PIO[0-9]_CAP [ptf]:capture
CONFIG_SYS_NIOS_CPU_PIO[0-9]_EDGE [ptf]:edge_type
CONFIG_SYS_NIOS_CPU_PIO[0-9]_ITYPE [ptf]:irq_type
S P I N I O S S D K [6]
-------------------------------------------------------------------------------
CFG_NIOS_CPU_SPI_NUMS nasys_spi_count
CFG_NIOS_CPU_SPI[0-9] nasys_spi_[0-9]
CFG_NIOS_CPU_SPI[0-9]_IRQ nasys_spi_[0-9]_irq
CFG_NIOS_CPU_SPI[0-9]_BITS [ptf]:databits
CFG_NIOS_CPU_SPI[0-9]_MA [ptf]:ismaster
CFG_NIOS_CPU_SPI[0-9]_SLN [ptf]:numslaves
CFG_NIOS_CPU_SPI[0-9]_TCLK [ptf]:targetclock
CFG_NIOS_CPU_SPI[0-9]_TDELAY [ptf]:targetdelay
CFG_NIOS_CPU_SPI[0-9]_* [ptf]:*
CONFIG_SYS_NIOS_CPU_SPI_NUMS nasys_spi_count
CONFIG_SYS_NIOS_CPU_SPI[0-9] nasys_spi_[0-9]
CONFIG_SYS_NIOS_CPU_SPI[0-9]_IRQ nasys_spi_[0-9]_irq
CONFIG_SYS_NIOS_CPU_SPI[0-9]_BITS [ptf]:databits
CONFIG_SYS_NIOS_CPU_SPI[0-9]_MA [ptf]:ismaster
CONFIG_SYS_NIOS_CPU_SPI[0-9]_SLN [ptf]:numslaves
CONFIG_SYS_NIOS_CPU_SPI[0-9]_TCLK [ptf]:targetclock
CONFIG_SYS_NIOS_CPU_SPI[0-9]_TDELAY [ptf]:targetdelay
CONFIG_SYS_NIOS_CPU_SPI[0-9]_* [ptf]:*
I D E N I O S S D K
-------------------------------------------------------------------------------
CFG_NIOS_CPU_IDE_NUMS nasys_usersocket_count
CFG_NIOS_CPU_IDE[0-9] nasys_usersocket_[0-9]
CONFIG_SYS_NIOS_CPU_IDE_NUMS nasys_usersocket_count
CONFIG_SYS_NIOS_CPU_IDE[0-9] nasys_usersocket_[0-9]
A S M I N I O S S D K [5]
-------------------------------------------------------------------------------
CFG_NIOS_CPU_ASMI_NUMS nasys_asmi_count
CFG_NIOS_CPU_ASMI[0-9] nasys_asmi_[0-9]
CFG_NIOS_CPU_ASMI[0-9]_IRQ nasys_asmi_[0-9]_irq
CONFIG_SYS_NIOS_CPU_ASMI_NUMS nasys_asmi_count
CONFIG_SYS_NIOS_CPU_ASMI[0-9] nasys_asmi_[0-9]
CONFIG_SYS_NIOS_CPU_ASMI[0-9]_IRQ nasys_asmi_[0-9]_irq
E t h e r n e t ( L A N ) N I O S S D K
-------------------------------------------------------------------------------
CFG_NIOS_CPU_LAN_NUMS
CFG_NIOS_CPU_LAN[0-9]_BASE na_lan91c111
CFG_NIOS_CPU_LAN[0-9]_OFFS LAN91C111_REGISTERS_OFFSET
CFG_NIOS_CPU_LAN[0-9]_IRQ na_lan91c111_irq
CFG_NIOS_CPU_LAN[0-9]_BUSW LAN91C111_DATA_BUS_WIDTH
CFG_NIOS_CPU_LAN[0-9]_TYPE
CONFIG_SYS_NIOS_CPU_LAN_NUMS
CONFIG_SYS_NIOS_CPU_LAN[0-9]_BASE na_lan91c111
CONFIG_SYS_NIOS_CPU_LAN[0-9]_OFFS LAN91C111_REGISTERS_OFFSET
CONFIG_SYS_NIOS_CPU_LAN[0-9]_IRQ na_lan91c111_irq
CONFIG_SYS_NIOS_CPU_LAN[0-9]_BUSW LAN91C111_DATA_BUS_WIDTH
CONFIG_SYS_NIOS_CPU_LAN[0-9]_TYPE
s y s t e m c o m p o s i n g N I O S S D K
-------------------------------------------------------------------------------
CFG_NIOS_CPU_TICK_TIMER (na_low_priority_timer2)
CFG_NIOS_CPU_USER_TIMER (na_timer1)
CFG_NIOS_CPU_BUTTON_PIO (na_button_pio)
CFG_NIOS_CPU_LCD_PIO (na_lcd_pio)
CFG_NIOS_CPU_LED_PIO (na_led_pio)
CFG_NIOS_CPU_SEVENSEG_PIO (na_seven_seg_pio)
CFG_NIOS_CPU_RECONF_PIO (na_reconfig_request_pio)
CFG_NIOS_CPU_CFPRESENT_PIO (na_cf_present_pio)
CFG_NIOS_CPU_CFPOWER_PIO (na_cf_power_pio)
CFG_NIOS_CPU_CFATASEL_PIO (na_cf_ata_select_pio)
CFG_NIOS_CPU_USER_SPI (na_spi)
CONFIG_SYS_NIOS_CPU_TICK_TIMER (na_low_priority_timer2)
CONFIG_SYS_NIOS_CPU_USER_TIMER (na_timer1)
CONFIG_SYS_NIOS_CPU_BUTTON_PIO (na_button_pio)
CONFIG_SYS_NIOS_CPU_LCD_PIO (na_lcd_pio)
CONFIG_SYS_NIOS_CPU_LED_PIO (na_led_pio)
CONFIG_SYS_NIOS_CPU_SEVENSEG_PIO (na_seven_seg_pio)
CONFIG_SYS_NIOS_CPU_RECONF_PIO (na_reconfig_request_pio)
CONFIG_SYS_NIOS_CPU_CFPRESENT_PIO (na_cf_present_pio)
CONFIG_SYS_NIOS_CPU_CFPOWER_PIO (na_cf_power_pio)
CONFIG_SYS_NIOS_CPU_CFATASEL_PIO (na_cf_ata_select_pio)
CONFIG_SYS_NIOS_CPU_USER_SPI (na_spi)
===============================================================================
......
api/api_storage.c
View file @ 6d0f6bcf
......@@ -67,28 +67,28 @@ static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, "" }, };
void dev_stor_init(void)
{
#if defined(CONFIG_CMD_IDE)
specs[ENUM_IDE].max_dev = CFG_IDE_MAXDEVICE;
specs[ENUM_IDE].max_dev = CONFIG_SYS_IDE_MAXDEVICE;
specs[ENUM_IDE].enum_started = 0;
specs[ENUM_IDE].enum_ended = 0;
specs[ENUM_IDE].type = DEV_TYP_STOR | DT_STOR_IDE;
specs[ENUM_IDE].name = "ide";
#endif
#if defined(CONFIG_CMD_MMC)
specs[ENUM_MMC].max_dev = CFG_MMC_MAX_DEVICE;
specs[ENUM_MMC].max_dev = CONFIG_SYS_MMC_MAX_DEVICE;
specs[ENUM_MMC].enum_started = 0;
specs[ENUM_MMC].enum_ended = 0;
specs[ENUM_MMC].type = DEV_TYP_STOR | DT_STOR_MMC;
specs[ENUM_MMC].name = "mmc";
#endif
#if defined(CONFIG_CMD_SATA)
specs[ENUM_SATA].max_dev = CFG_SATA_MAX_DEVICE;
specs[ENUM_SATA].max_dev = CONFIG_SYS_SATA_MAX_DEVICE;
specs[ENUM_SATA].enum_started = 0;
specs[ENUM_SATA].enum_ended = 0;
specs[ENUM_SATA].type = DEV_TYP_STOR | DT_STOR_SATA;
specs[ENUM_SATA].name = "sata";
#endif
#if defined(CONFIG_CMD_SCSI)
specs[ENUM_SCSI].max_dev = CFG_SCSI_MAX_DEVICE;
specs[ENUM_SCSI].max_dev = CONFIG_SYS_SCSI_MAX_DEVICE;
specs[ENUM_SCSI].enum_started = 0;
specs[ENUM_SCSI].enum_ended = 0;
specs[ENUM_SCSI].type = DEV_TYP_STOR | DT_STOR_SCSI;
......
board/AtmarkTechno/suzaku/flash.c
View file @ 6d0f6bcf
......@@ -24,7 +24,7 @@
#include <common.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
unsigned long flash_init(void)
{
......
board/BuS/EB+MCF-EV123/EB+MCF-EV123.c
View file @ 6d0f6bcf
......@@ -32,7 +32,7 @@
int checkboard (void)
{
puts ("Board: MCF-EV1 + MCF-EV23 (BuS Elektronik GmbH & Co. KG)\n");
#if (TEXT_BASE == CFG_INT_FLASH_BASE)
#if (TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
puts (" Boot from Internal FLASH\n");
#endif
......@@ -45,10 +45,10 @@ phys_size_t initdram (int board_type)
size = 0;
MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6
| MCFSDRAMC_DCR_RC ((15 * CFG_CLK) >> 4);
#ifdef CFG_SDRAM_BASE0
| MCFSDRAMC_DCR_RC ((15 * CONFIG_SYS_CLK) >> 4);
#ifdef CONFIG_SYS_SDRAM_BASE0
MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE (CFG_SDRAM_BASE0)
MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE0)
| MCFSDRAMC_DACR_CASL (1)
| MCFSDRAMC_DACR_CBM (3)
| MCFSDRAMC_DACR_PS_16;
......@@ -57,17 +57,17 @@ phys_size_t initdram (int board_type)
MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
*(unsigned short *) (CFG_SDRAM_BASE0) = 0xA5A5;
*(unsigned short *) (CONFIG_SYS_SDRAM_BASE0) = 0xA5A5;
MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
for (i = 0; i < 2000; i++)
asm (" nop");
mbar_writeLong (MCFSDRAMC_DACR0,
mbar_readLong (MCFSDRAMC_DACR0) | MCFSDRAMC_DACR_IMRS);
*(unsigned int *) (CFG_SDRAM_BASE0 + 0x220) = 0xA5A5;
size += CFG_SDRAM_SIZE * 1024 * 1024;
*(unsigned int *) (CONFIG_SYS_SDRAM_BASE0 + 0x220) = 0xA5A5;
size += CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
#endif
#ifdef CFG_SDRAM_BASE1
MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CFG_SDRAM_BASE1)
#ifdef CONFIG_SYS_SDRAM_BASE1
MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE1)
| MCFSDRAMC_DACR_CASL (1)
| MCFSDRAMC_DACR_CBM (3)
| MCFSDRAMC_DACR_PS_16;
......@@ -76,25 +76,25 @@ phys_size_t initdram (int board_type)
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP;
*(unsigned short *) (CFG_SDRAM_BASE1) = 0xA5A5;
*(unsigned short *) (CONFIG_SYS_SDRAM_BASE1) = 0xA5A5;
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE;
for (i = 0; i < 2000; i++)
asm (" nop");
MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS;
*(unsigned int *) (CFG_SDRAM_BASE1 + 0x220) = 0xA5A5;
size += CFG_SDRAM_SIZE1 * 1024 * 1024;
*(unsigned int *) (CONFIG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5;
size += CONFIG_SYS_SDRAM_SIZE1 * 1024 * 1024;
#endif
return size;
}
#if defined(CFG_DRAM_TEST)
#if defined(CONFIG_SYS_DRAM_TEST)
int testdram (void)
{
uint *pstart = (uint *) CFG_MEMTEST_START;
uint *pend = (uint *) CFG_MEMTEST_END;
uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
uint *p;
printf("SDRAM test phase 1:\n");
......
board/BuS/EB+MCF-EV123/VCxK.c
View file @ 6d0f6bcf
......@@ -25,7 +25,7 @@
#include <asm/m5282.h>
#include "VCxK.h"
vu_char *vcxk_bws = (vu_char *)(CFG_CS3_BASE);
vu_char *vcxk_bws = (vu_char *)(CONFIG_SYS_CS3_BASE);
#define VCXK_BWS vcxk_bws
static ulong vcxk_driver;
......
board/BuS/EB+MCF-EV123/cfm_flash.c
View file @ 6d0f6bcf
......@@ -28,14 +28,14 @@
#if defined(CONFIG_M5281) || defined(CONFIG_M5282)
#if (CFG_CLK>20000000)
#define CFM_CLK (((long) CFG_CLK / (400000 * 8) + 1) | 0x40)
#if (CONFIG_SYS_CLK>20000000)
#define CFM_CLK (((long) CONFIG_SYS_CLK / (400000 * 8) + 1) | 0x40)
#else
#define CFM_CLK ((long) CFG_CLK / 400000 + 1)
#define CFM_CLK ((long) CONFIG_SYS_CLK / 400000 + 1)
#endif
#define cmf_backdoor_address(addr) (((addr) & 0x0007FFFF) | 0x04000000 | \
(CFG_MBAR & 0xC0000000))
(CONFIG_SYS_MBAR & 0xC0000000))
void cfm_flash_print_info (flash_info_t * info)
{
......@@ -60,8 +60,8 @@ void cfm_flash_init (flash_info_t * info)
MCFCFM_MCR = 0;
MCFCFM_CLKD = CFM_CLK;
debug ("CFM Clock divider: %ld (%d Hz @ %ld Hz)\n",CFM_CLK,\
CFG_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\
CFG_CLK);
CONFIG_SYS_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\
CONFIG_SYS_CLK);
MCFCFM_SACC = 0;
MCFCFM_DACC = 0;
......@@ -86,7 +86,7 @@ void cfm_flash_init (flash_info_t * info)
{
if (sector == 0)
{
info->start[sector] = CFG_INT_FLASH_BASE;
info->start[sector] = CONFIG_SYS_INT_FLASH_BASE;
}
else
{
......@@ -187,7 +187,7 @@ int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cn
return rc;
}
#ifdef CFG_FLASH_PROTECTION
#ifdef CONFIG_SYS_FLASH_PROTECTION
int cfm_flash_protect(flash_info_t * info,long sector,int prot)
{
......
board/BuS/EB+MCF-EV123/cfm_flash.h
View file @ 6d0f6bcf
......@@ -33,7 +33,7 @@ extern void cfm_flash_print_info (flash_info_t * info);
extern int cfm_flash_erase_sector (flash_info_t * info, int sector);
extern void cfm_flash_init (flash_info_t * info);
extern int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
#ifdef CFG_FLASH_PROTECTION
#ifdef CONFIG_SYS_FLASH_PROTECTION
extern int cfm_flash_protect(flash_info_t * info,long sector,int prot);
#endif
......
board/BuS/EB+MCF-EV123/flash.c
View file @ 6d0f6bcf
......@@ -27,10 +27,10 @@
#include <common.h>
#include "cfm_flash.h"
#define PHYS_FLASH_1 CFG_FLASH_BASE
#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
#define FLASH_BANK_SIZE 0x200000
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
void flash_print_info (flash_info_t * info)
{
......@@ -83,7 +83,7 @@ unsigned long flash_init (void)
int i, j;
ulong size = 0;
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
ulong flashbase = 0;
switch (i)
......@@ -93,8 +93,8 @@ unsigned long flash_init (void)
(AMD_MANUFACT & FLASH_VENDMASK) |
(AMD_ID_LV160B & FLASH_TYPEMASK);
flash_info[i].size = FLASH_BANK_SIZE;
flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
flashbase = PHYS_FLASH_1;
for (j = 0; j < flash_info[i].sector_count; j++) {
if (j == 0) {
......@@ -128,8 +128,8 @@ unsigned long flash_init (void)
}
flash_protect (FLAG_PROTECT_SET,
CFG_FLASH_BASE,
CFG_FLASH_BASE + 0xffff, &flash_info[0]);
CONFIG_SYS_FLASH_BASE,
CONFIG_SYS_FLASH_BASE + 0xffff, &flash_info[0]);
return size;
}
......@@ -177,7 +177,7 @@ int amd_flash_erase_sector(flash_info_t * info, int sector)
result = *addr;
/* check timeout */
if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
state = ERR_TIMOUT;
}
......@@ -303,7 +303,7 @@ volatile static int amd_write_word (flash_info_t * info, ulong dest, u16 data)
result = *addr;
/* check timeout */
if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
state = ERR_TIMOUT;
}
if (!state && ((result & BIT_RDY_MASK) == (data & BIT_RDY_MASK)))
......@@ -390,7 +390,7 @@ int amd_flash_protect(flash_info_t * info,long sector,int prot)
return rc;
}