Commit 6de54203 authored by Wolfgang Denk's avatar Wolfgang Denk
Browse files

Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx

parents 74d1e66d e54ec0f0
......@@ -322,6 +322,7 @@ Stefan Roese <sr@denx.de>
bunbinga PPC405EP
canyonlands PPC460EX
ebony PPC440GP
glacier PPC460GT
haleakala PPC405EXr
katmai PPC440SPe
kilauea PPC405EX
......
......@@ -185,6 +185,7 @@ LIST_4xx=" \
ERIC \
EXBITGEN \
G2000 \
glacier \
haleakala \
haleakala_nand \
hcu4 \
......
......@@ -1172,8 +1172,13 @@ bubinga_config: unconfig
CANBT_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx canbt esd
canyonlands_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc ppc4xx canyonlands amcc
# Canyonlands & Glacier use different U-Boot images
canyonlands_config \
glacier_config: unconfig
@mkdir -p $(obj)include
@echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
tr '[:lower:]' '[:upper:]')" >$(obj)include/config.h
@$(MKCONFIG) -n $@ -a canyonlands ppc ppc4xx canyonlands amcc
canyonlands_nand_config: unconfig
@mkdir -p $(obj)include $(obj)board/amcc/canyonlands
......
......@@ -1929,6 +1929,27 @@ Configuration Settings:
Scratch address used by the alternate memory test
You only need to set this if address zero isn't writeable
- CFG_MEM_TOP_HIDE (PPC only):
If CFG_MEM_TOP_HIDE is defined in the board config header,
this specified memory area will get subtracted from the top
(end) of ram and won't get "touched" at all by U-Boot. By
fixing up gd->ram_size the Linux kernel should gets passed
the now "corrected" memory size and won't touch it either.
This should work for arch/ppc and arch/powerpc. Only Linux
board ports in arch/powerpc with bootwrapper support that
recalculate the memory size from the SDRAM controller setup
will have to get fixed in Linux additionally.
This option can be used as a workaround for the 440EPx/GRx
CHIP 11 errata where the last 256 bytes in SDRAM shouldn't
be touched.
WARNING: Please make sure that this value is a multiple of
the Linux page size (normally 4k). If this is not the case,
then the end address of the Linux memory will be located at a
non page size aligned address and this could cause major
problems.
- CFG_TFTP_LOADADDR:
Default load address for network file downloads
......
......@@ -32,13 +32,20 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
DECLARE_GLOBAL_DATA_PTR;
#define CFG_BCSR3_PCIE 0x10
#define BOARD_CANYONLANDS_PCIE 1
#define BOARD_CANYONLANDS_SATA 2
#define BOARD_GLACIER 3
int board_early_init_f(void)
{
u32 sdr0_cust0;
u32 pvr = get_pvr();
/*------------------------------------------------------------------+
/*
* Setup the interrupt controller polarities, triggers, etc.
*------------------------------------------------------------------*/
*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
......@@ -105,27 +112,69 @@ int board_early_init_f(void)
mtdcr(AHB_TOP, 0x8000004B);
mtdcr(AHB_BOT, 0x8000004B);
/*
* Configure USB-STP pins as alternate and not GPIO
* It seems to be neccessary to configure the STP pins as GPIO
* input at powerup (perhaps while USB reset is asserted). So
* we configure those pins to their "real" function now.
*/
gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA)) {
/*
* Configure USB-STP pins as alternate and not GPIO
* It seems to be neccessary to configure the STP pins as GPIO
* input at powerup (perhaps while USB reset is asserted). So
* we configure those pins to their "real" function now.
*/
gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
}
return 0;
}
int checkboard (void)
static void canyonlands_sata_init(int board_type)
{
u32 reg;
if (board_type == BOARD_CANYONLANDS_SATA) {
/* Put SATA in reset */
SDR_WRITE(SDR0_SRST1, 0x00020001);
/* Set the phy for SATA, not PCI-E port 0 */
reg = SDR_READ(PESDR0_PHY_CTL_RST);
SDR_WRITE(PESDR0_PHY_CTL_RST, (reg & 0xeffffffc) | 0x00000001);
reg = SDR_READ(PESDR0_L0CLK);
SDR_WRITE(PESDR0_L0CLK, (reg & 0xfffffff8) | 0x00000007);
SDR_WRITE(PESDR0_L0CDRCTL, 0x00003111);
SDR_WRITE(PESDR0_L0DRV, 0x00000104);
/* Bring SATA out of reset */
SDR_WRITE(SDR0_SRST1, 0x00000000);
}
}
int checkboard(void)
{
char *s = getenv("serial#");
u32 pvr = get_pvr();
if ((pvr == PVR_460GT_RA) || (pvr == PVR_460GT_SE_RA))
if ((pvr == PVR_460GT_RA) || (pvr == PVR_460GT_SE_RA)) {
printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
else
gd->board_type = BOARD_GLACIER;
} else {
printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
if (in_8((void *)(CFG_BCSR_BASE + 3)) & CFG_BCSR3_PCIE)
gd->board_type = BOARD_CANYONLANDS_PCIE;
else
gd->board_type = BOARD_CANYONLANDS_SATA;
}
switch (gd->board_type) {
case BOARD_CANYONLANDS_PCIE:
case BOARD_GLACIER:
puts(", 2*PCIe");
break;
case BOARD_CANYONLANDS_SATA:
puts(", 1*PCIe/1*SATA");
break;
}
printf(", Rev. %X", in_8((void *)(CFG_BCSR_BASE + 0)));
if (s != NULL) {
puts(", serial# ");
......@@ -133,6 +182,8 @@ int checkboard (void)
}
putc('\n');
canyonlands_sata_init(gd->board_type);
return (0);
}
......@@ -198,37 +249,36 @@ int testdram(void)
}
#endif
/*************************************************************************
/*
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
*/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
/*-------------------------------------------------------------------+
/*
* Disable everything
*-------------------------------------------------------------------*/
*/
out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
/*-------------------------------------------------------------------+
/*
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
* strapping options to not support sizes such as 128/256 MB.
*-------------------------------------------------------------------*/
*/
out_le32((void *)PCIX0_PIM0LAL, CFG_SDRAM_BASE);
out_le32((void *)PCIX0_PIM0LAH, 0);
out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
out_le32((void *)PCIX0_BAR0, 0);
/*-------------------------------------------------------------------+
/*
* Program the board's subsystem id/vendor id
*-------------------------------------------------------------------*/
*/
out_le16((void *)PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
out_le16((void *)PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
......@@ -265,13 +315,24 @@ void pcie_setup_hoses(int busno)
int ret = 0;
char *env;
unsigned int delay;
int start;
/*
* assume we're called after the PCIX hose is initialized, which takes
* bus ID 0 and therefore start numbering PCIe's from 1.
*/
bus = busno;
for (i = 0; i <= 1; i++) {
/*
* Canyonlands with SATA enabled has only one PCIe slot
* (2nd one).
*/
if (gd->board_type == BOARD_CANYONLANDS_SATA)
start = 1;
else
start = 0;
for (i = start; i <= 1; i++) {
if (is_end_point(i))
ret = ppc4xx_init_pcie_endport(i);
......@@ -369,6 +430,7 @@ int misc_init_r(void)
{
u32 sdr0_srst1 = 0;
u32 eth_cfg;
u32 pvr = get_pvr();
/*
* Set EMAC mode/configuration (GMII, SGMII, RGMII...).
......@@ -382,7 +444,10 @@ int misc_init_r(void)
/* Set the for 2 RGMII mode */
/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
if ((pvr == PVR_460EX_RA) || (pvr == PVR_460EX_SE_RA))
eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
else
eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
mtsdr(SDR0_ETH_CFG, eth_cfg);
/*
......@@ -407,7 +472,7 @@ void ft_board_setup(void *blob, bd_t *bd)
/* Fixup NOR mapping */
val[0] = 0; /* chip select number */
val[1] = 0; /* always 0 */
val[2] = gd->bd->bi_flashstart;
val[2] = CFG_FLASH_BASE_PHYS_L; /* we fixed up this address */
val[3] = gd->bd->bi_flashsize;
rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
val, sizeof(val), 1);
......
......@@ -139,8 +139,6 @@ SECTIONS
*(COMMON)
}
ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
_end = . ;
PROVIDE (end = .);
}
......@@ -67,12 +67,12 @@ int board_early_init_f(void)
out_be32((void*)GPIO1_OR, 0x00000000);
out_be32((void*)GPIO1_TCR, 0xc2000000 |
CFG_GPIO1_IORSTN |
CFG_GPIO1_IORST2N |
CFG_GPIO1_LEDUSR1 |
CFG_GPIO1_LEDUSR2 |
CFG_GPIO1_LEDPOST |
CFG_GPIO1_LEDDU);
out_be32((void*)GPIO1_ODR, CFG_GPIO1_LEDDU);
out_be32((void*)GPIO1_OSRL, 0x5c280000);
out_be32((void*)GPIO1_OSRH, 0x00000000);
out_be32((void*)GPIO1_TSRL, 0x0c000000);
......@@ -243,7 +243,8 @@ int misc_init_r(void)
* release IO-RST#
* We have to wait at least 560ms until we may call usbhub_init
*/
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CFG_GPIO1_IORSTN);
out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) |
CFG_GPIO1_IORSTN | CFG_GPIO1_IORST2N);
/*
* flash USR1/2 LEDs (600ms)
......
......@@ -24,6 +24,7 @@
#define CFG_GPIO1_DCF77 (0x80000000 >> (42-32)) /* GPIO1_42 */
#define CFG_GPIO1_IORSTN (0x80000000 >> (55-32)) /* GPIO1_55 */
#define CFG_GPIO1_IORST2N (0x80000000 >> (47-32)) /* GPIO1_47 */
#define CFG_GPIO1_HWVER_MASK 0x000000f0 /* GPIO1_56-59 */
#define CFG_GPIO1_HWVER_SHIFT 4
......
/*
* (C) Copyright 2007
* (C) Copyright 2007-2008
* Matthias Fuchs, esd Gmbh, matthias.fuchs@esd-electronics.com.
*
* See file CREDITS for list of people who contributed to this
......@@ -21,7 +21,6 @@
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <command.h>
#include <asm/io.h>
......@@ -31,7 +30,8 @@
#include "pmc440.h"
int is_monarch(void);
int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, unsigned cnt);
int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
uchar *buffer, unsigned cnt);
int eeprom_write_enable(unsigned dev_addr, int state);
DECLARE_GLOBAL_DATA_PTR;
......@@ -64,7 +64,6 @@ int fpga_interrupt(u32 arg)
return rc;
}
int do_waithci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
......@@ -100,7 +99,6 @@ U_BOOT_CMD(
NULL
);
void dump_fifo(pmc440_fpga_t *fpga, int f, int *n)
{
u32 ctrl;
......@@ -117,7 +115,6 @@ void dump_fifo(pmc440_fpga_t *fpga, int f, int *n)
}
}
int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
......@@ -200,7 +197,8 @@ int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
got_fifoirq = 0;
/* unmask global fifo irq */
FPGA_OUT32(&fpga->hostctrl,
HOSTCTRL_FIFOIE_GATE | HOSTCTRL_FIFOIE_FLAG);
HOSTCTRL_FIFOIE_GATE |
HOSTCTRL_FIFOIE_FLAG);
}
}
......@@ -237,7 +235,8 @@ int do_fifo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
for (i=0; i<n; i++)
FPGA_OUT32(&fpga->fifo[f].data, data);
} else {
printf("writing %d x %08x to fifo port at address %08x\n",
printf("writing %d x %08x to fifo port at "
"address %08x\n",
n, data, f);
for (i=0; i<n; i++)
out32(f, data);
......@@ -263,10 +262,10 @@ U_BOOT_CMD(
" - without arguments: print all fifo's status\n"
" - with 'wait' argument: interrupt driven read from all fifos\n"
" - with 'read' argument: read current contents from all fifos\n"
" - with 'write' argument: write 'data' 'cnt' times to 'fifo' or 'address'\n"
" - with 'write' argument: write 'data' 'cnt' times to "
"'fifo' or 'address'\n"
);
int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
ulong sdsdp[5];
......@@ -301,10 +300,12 @@ int do_setup_bootstrap_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]
sdsdp[2]=0x40082350;
sdsdp[3]=0x0d050000;
} else if (!strcmp(argv[1], "test")) {
/* TODO: this will replace the 667 MHz config above.
/*
* TODO: this will replace the 667 MHz config above.
* But it needs some more testing on a real 667 MHz CPU.
*/
printf("Bootstrapping for test (667MHz PLB=133PLB PLB/PCI=3)\n");
printf("Bootstrapping for test"
" (667MHz PLB=133PLB PLB/PCI=3)\n");
sdsdp[0]=0x8778a256;
sdsdp[1]=0x095fa030;
sdsdp[2]=0x40082350;
......@@ -347,7 +348,6 @@ U_BOOT_CMD(
"<cpufreq:400|533|667> [<console-uart:0|1> [<bringup delay (0..20s)>]]"
);
#if defined(CONFIG_PRAM)
#include <environment.h>
extern env_t *env_ptr;
......@@ -394,7 +394,6 @@ U_BOOT_CMD(
);
#endif /* CONFIG_PRAM */
int do_selfreset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
if (argc > 1) {
......@@ -423,7 +422,6 @@ U_BOOT_CMD(
NULL
);
int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA;
......@@ -444,7 +442,8 @@ int do_resetout(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
/* deassert */
printf("PMC-RESETOUT# deasserted\n");
FPGA_OUT32(&fpga->hostctrl,
HOSTCTRL_PMCRSTOUT_GATE | HOSTCTRL_PMCRSTOUT_FLAG);
HOSTCTRL_PMCRSTOUT_GATE |
HOSTCTRL_PMCRSTOUT_FLAG);
}
} else {
printf("PMC-RESETOUT# is %s\n",
......@@ -460,7 +459,6 @@ U_BOOT_CMD(
NULL
);
int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
if (is_monarch()) {
......@@ -481,7 +479,9 @@ int do_inta(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
in_be32((void*)GPIO1_TCR) & ~GPIO1_INTA_FAKE);
}
} else {
printf("inta# is %s\n", in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ? "active" : "inactive");
printf("inta# is %s\n",
in_be32((void*)GPIO1_TCR) & GPIO1_INTA_FAKE ?
"active" : "inactive");
}
return 0;
}
......@@ -491,7 +491,6 @@ U_BOOT_CMD(
NULL
);
/* test-only */
int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
......@@ -503,11 +502,17 @@ int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
pciaddr &= 0xf0000000;
/* map PCI address at 0xc0000000 in PLB space */
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM1 Mask/Attribute - disabled b4 setting */
out32r(PCIX0_PMM1LA, 0xc0000000); /* PMM1 Local Address */
out32r(PCIX0_PMM1PCILA, pciaddr); /* PMM1 PCI Low Address */
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM1 PCI High Address */
out32r(PCIX0_PMM1MA, 0xf0000001); /* 256MB + No prefetching, and enable region */
/* PMM1 Mask/Attribute - disabled b4 setting */
out32r(PCIX0_PMM1MA, 0x00000000);
/* PMM1 Local Address */
out32r(PCIX0_PMM1LA, 0xc0000000);
/* PMM1 PCI Low Address */
out32r(PCIX0_PMM1PCILA, pciaddr);
/* PMM1 PCI High Address */
out32r(PCIX0_PMM1PCIHA, 0x00000000);
/* 256MB + No prefetching, and enable region */
out32r(PCIX0_PMM1MA, 0xf0000001);
} else {
printf("Usage:\npmm %s\n", cmdtp->help);
}
......
This diff is collapsed.
......@@ -24,14 +24,24 @@
# Korat (PPC440EPx) board
#
TEXT_BASE = 0xFFFA0000
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(emul),1)
PLATFORM_CPPFLAGS += -fno-schedule-insns -fno-schedule-insns2
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8CFF0000
endif
ifeq ($(perm),1)
PLATFORM_CPPFLAGS += -DCONFIG_KORAT_PERMANENT
TEXT_BASE = 0xFFFA0000
else
TEXT_BASE = 0xF7F60000
LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-F7FC.lds
endif
......@@ -43,7 +43,7 @@ tlbtab:
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
* speed up boot process. It is patched after relocation to enable SA_I
*/
tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
tlbentry( 0xF0000000, SZ_256M, 0xF0000000, 1, AC_R|AC_W|AC_X|SA_G )
/*
* TLB entries for SDRAM are not needed on this platform. They are
......@@ -52,24 +52,32 @@ tlbtab:
#ifdef CFG_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0,
AC_R|AC_W|AC_X|SA_G )
#endif
/* TLB-entry for PCI Memory */
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE + 0x00000000, SZ_256M,
CFG_PCI_MEMBASE + 0x00000000, 1, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE + 0x10000000, SZ_256M,
CFG_PCI_MEMBASE + 0x10000000, 1, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE + 0x20000000, SZ_256M,
CFG_PCI_MEMBASE + 0x20000000, 1, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE + 0x30000000, SZ_256M,
CFG_PCI_MEMBASE + 0x30000000, 1, AC_R|AC_W|SA_G|SA_I )
/* TLB-entry for EBC */
tlbentry( CFG_CPLD_BASE, SZ_1K, CFG_CPLD_BASE, 1, AC_R|AC_W|SA_G|SA_I )
/* TLB-entry for Internal Registers & OCM */
/* I wonder why this must be executable -- lrj@acm.org 2007-10-08 */
tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_R|AC_W|AC_X|SA_I )
tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_R|AC_W|AC_X|SA_I )
/*TLB-entry PCI registers*/
tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|SA_G|SA_I )
tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|SA_G|SA_I )
/* TLB-entry for peripherals */
tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|SA_G|SA_I)
......@@ -78,3 +86,10 @@ tlbtab:
tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|SA_G|SA_I)
tlbtab_end
#if defined(CONFIG_KORAT_PERMANENT)
.globl korat_branch_absolute
korat_branch_absolute:
mtlr r3
blr
#endif
......@@ -2,12 +2,12 @@
* (C) Copyright 2007-2008
* Larry Johnson, lrj@acm.org
*
* (C) Copyright 2006-2008
* (C) Copyright 2006-2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2006
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
......@@ -39,12 +39,45 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
ulong flash_get_size(ulong base, int banknum);
#if defined(CONFIG_KORAT_PERMANENT)
void korat_buzzer(int const on)
{
if (on) {
out_8((u8 *) CFG_CPLD_BASE + 0x05,
in_8((u8 *) CFG_CPLD_BASE + 0x05) | 0x80);
} else {
out_8((u8 *) CFG_CPLD_BASE + 0x05,
in_8((u8 *) CFG_CPLD_BASE + 0x05) & ~0x80);
}
}
#endif
int board_early_init_f(void)
{
u32 sdr0_pfc1, sdr0_pfc2;
u32 reg;
uint32_t sdr0_pfc1, sdr0_pfc2;
uint32_t reg;
int eth;
#if defined(CONFIG_KORAT_PERMANENT)
unsigned mscount;
extern void korat_branch_absolute(uint32_t addr);
for (mscount = 0; mscount < CFG_KORAT_MAN_RESET_MS; ++mscount) {
udelay(1000);
if (gpio_read_in_bit(CFG_GPIO_RESET_PRESSED_)) {
/* This call does not return. */