Commit 6dff5529 authored by wdenk's avatar wdenk
Browse files

* Patches by Martin Krause, 14 Jul 2003:

  - add I2C support for s3c2400 systems (trab board)
  - (re-) add "ping" to command table

* Fix handling of "slow" POST routines
parent 8564acf9
......@@ -2,6 +2,12 @@
Changes for U-Boot 0.4.3:
======================================================================
* Patches by Martin Krause, 14 Jul 2003:
- add I2C support for s3c2400 systems (trab board)
- (re-) add "ping" to command table
* Fix handling of "slow" POST routines
* Patches by Yuli Barcohen, 13 Jul 2003:
- Correct flash and JFFS2 support for MPC8260ADS
- fix PVR values and clock generation for PowerQUICC II family
......
......@@ -3048,6 +3048,11 @@ it:
version of diff does not support these options, then get the latest
version of GNU diff.
The current directory when running this command shall be the top
level directory of the U-Boot source tree, or it's parent directory
(i. e. please make sure that your patch includes sufficient
directory information for the affected files).
We accept patches as plain text, MIME attachments or as uuencoded
gzipped text.
......
......@@ -1087,7 +1087,6 @@ int post_hotkeys_pressed(gd_t *gd)
i2c_write (kbd_addr, 0, 0, &val, 1);
i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
return (gd->post_hotkeys_latch =
(compare_magic(kbd_data, CONFIG_POST_KEY_MAGIC) == 0));
return (compare_magic(kbd_data, CONFIG_POST_KEY_MAGIC) == 0);
}
#endif
......@@ -130,6 +130,11 @@ int board_init ()
}
#endif /* CONFIG_MODEM_SUPPORT */
#ifdef CONFIG_DRIVER_S3C24X0_I2C
/* Configure I/O ports PG5 und PG6 for I2C */
gpio->PGCON = (gpio->PGCON & 0x003c00) | 0x003c00;
#endif /* CONFIG_DRIVER_S3C24X0_I2C */
return 0;
}
......
......@@ -210,6 +210,12 @@ int do_ping (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return 0;
}
U_BOOT_CMD(
ping, 2, 1, do_ping,
"ping - send ICMP ECHO_REQUEST to network host\n",
"pingAddress\n"
);
#endif /* CFG_CMD_PING */
#endif /* CFG_CMD_NET */
......@@ -63,7 +63,12 @@ static int GetI2CSDA(void)
{
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
#ifdef CONFIG_S3C2410
return (gpio->GPEDAT & 0x8000) >> 15;
#endif
#ifdef CONFIG_S3C2400
return (gpio->PGDAT & 0x0020) >> 5;
#endif
}
#if 0
......@@ -77,7 +82,12 @@ static void SetI2CSCL(int x)
{
S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
#ifdef CONFIG_S3C2410
gpio->GPEDAT = (gpio->GPEDAT & ~0x4000) | (x&1) << 14;
#endif
#ifdef CONFIG_S3C2400
gpio->PGDAT = (gpio->PGDAT & ~0x0040) | (x&1) << 6;
#endif
}
......@@ -129,11 +139,22 @@ void i2c_init (int speed, int slaveadd)
}
if ((status & I2CSTAT_BSY) || GetI2CSDA() == 0) {
#ifdef CONFIG_S3C2410
ulong old_gpecon = gpio->GPECON;
#endif
#ifdef CONFIG_S3C2400
ulong old_gpecon = gpio->PGCON;
#endif
/* bus still busy probably by (most) previously interrupted transfer */
#ifdef CONFIG_S3C2410
/* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
gpio->GPECON = (gpio->GPECON & ~0xF0000000) | 0x10000000;
#endif
#ifdef CONFIG_S3C2400
/* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */
gpio->PGCON = (gpio->PGCON & ~0x00003c00) | 0x00000c00;
#endif
/* toggle I2CSCL until bus idle */
SetI2CSCL(0); udelay(1000);
......@@ -146,7 +167,12 @@ void i2c_init (int speed, int slaveadd)
SetI2CSCL(1); udelay(1000);
/* restore pin functions */
#ifdef CONFIG_S3C2410
gpio->GPECON = old_gpecon;
#endif
#ifdef CONFIG_S3C2400
gpio->PGCON = old_gpecon;
#endif
}
/* calculate prescaler and divisor values */
......
......@@ -73,7 +73,6 @@ typedef struct global_data {
#ifdef CONFIG_POST
unsigned long post_log_word; /* Record POST activities */
unsigned long post_init_f_time; /* When post_init_f started */
unsigned long post_hotkeys_latch; /* If the post hotkeys pressed */
#endif
#ifdef CONFIG_BOARD_TYPES
unsigned long board_type;
......
......@@ -37,9 +37,9 @@
* (easy to change)
*/
#define CONFIG_ARM920T 1 /* This is an arm920t CPU */
#define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */
#define CONFIG_TRAB 1 /* on a TRAB Board */
#undef CONFIG_TRAB_50MHZ /* run the CPU at 50 MHz */
#define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */
#define CONFIG_TRAB 1 /* on a TRAB Board */
#undef CONFIG_TRAB_50MHZ /* run the CPU at 50 MHz */
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000 /* TRAB has 12 MHz input clock */
......@@ -50,6 +50,23 @@
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
/***********************************************************
* I2C stuff:
* the TRAB is equipped with an ATMEL 24C04 EEPROM at
* address 0x54 with 8bit addressing
***********************************************************/
#define CONFIG_HARD_I2C /* I2C with hardware support */
#define CFG_I2C_SPEED 100000 /* I2C speed */
#define CFG_I2C_SLAVE 0x7F /* I2C slave addr */
#define CFG_I2C_EEPROM_ADDR 0x54 /* EEPROM address */
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* 1 address byte */
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* 8 bytes page write mode on 24C04 */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
/*
* Size of malloc() pool
*/
......@@ -62,13 +79,15 @@
#define CS8900_BASE 0x07000300 /* agrees with WIN CE PA */
#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
#define CONFIG_DRIVER_S3C24X0_I2C 1 /* we use the buildin I2C controller */
#define CONFIG_VFD 1 /* VFD linear frame buffer driver */
#define VFD_TEST_LOGO 1 /* output a test logo to the VFDs */
/*
* select serial console configuration
*/
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on TRAB */
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on TRAB */
#define CONFIG_HWFLOW /* include RTS/CTS flow control support */
......@@ -105,18 +124,30 @@
#define CONFIG_COMMANDS_ADD_VFD 0
#endif
#ifdef CONFIG_DRIVER_S3C24X0_I2C
#define CONFIG_COMMANDS_ADD_EEPROM CFG_CMD_EEPROM
#define CONFIG_COMMANDS_I2C CFG_CMD_I2C
#else
#define CONFIG_COMMANDS_ADD_EEPROM 0
#define CONFIG_COMMANDS_I2C 0
#endif
#ifndef USE_920T_MMU
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & ~CFG_CMD_CACHE) | \
CFG_CMD_BSP | \
CFG_CMD_DATE | \
CONFIG_COMMANDS_ADD_HWFLOW | \
CONFIG_COMMANDS_ADD_VFD )
CONFIG_COMMANDS_ADD_VFD | \
CONFIG_COMMANDS_ADD_EEPROM | \
CONFIG_COMMANDS_I2C )
#else
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_BSP | \
CFG_CMD_DATE | \
CONFIG_COMMANDS_ADD_HWFLOW | \
CONFIG_COMMANDS_ADD_VFD )
CONFIG_COMMANDS_ADD_VFD | \
CONFIG_COMMANDS_ADD_EEPROM | \
CONFIG_COMMANDS_I2C )
#endif
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
......@@ -125,8 +156,8 @@
#define CONFIG_BOOTDELAY 5
#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */
#define CONFIG_PREBOOT "echo;echo *** booting ***;echo"
#define CONFIG_BOOTARGS "console=ttyS0"
#define CONFIG_NETMASK 255.255.0.0
#define CONFIG_BOOTARGS "console=ttyS0"
#define CONFIG_NETMASK 255.255.0.0
#define CONFIG_IPADDR 192.168.3.68
#define CONFIG_HOSTNAME trab
#define CONFIG_SERVERIP 192.168.3.1
......@@ -192,6 +223,11 @@
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "TRAB # " /* Monitor Command Prompt */
/* #define CFG_HUSH_PARSER 1 */ /* use "hush" command parser */
#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
......@@ -200,7 +236,7 @@
#define CFG_MEMTEST_START 0x0c000000 /* memtest works on */
#define CFG_MEMTEST_END 0x0d000000 /* 16 MB in DRAM */
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
#define CFG_LOAD_ADDR 0x0cf00000 /* default load address */
......@@ -235,11 +271,11 @@
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x0c000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x0c000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */
#define CFG_FLASH_BASE 0x00000000 /* Flash Bank #1 */
#define CFG_FLASH_BASE 0x00000000 /* Flash Bank #1 */
/* The following #defines are needed to get flash environment right */
#define CFG_MONITOR_BASE CFG_FLASH_BASE
......
......@@ -418,10 +418,6 @@ void start_i386boot (void)
#ifdef CONFIG_POST
post_run (NULL, POST_RAM | post_bootmode_get(0));
if (post_bootmode_get(0) & POST_SLOWTEST) {
post_bootmode_clear();
board_poweroff();
}
#endif
......
......@@ -526,10 +526,7 @@ void board_init_f (ulong bootflag)
#ifdef CONFIG_POST
post_bootmode_init();
if (post_hotkeys_pressed(gd)) /* Force the long-running tests (memory) */
post_run (NULL, POST_ROM | POST_SLOWTEST);
else
post_run (NULL, POST_ROM | post_bootmode_get(0));
post_run (NULL, POST_ROM | post_bootmode_get(0));
#endif
WATCHDOG_RESET();
......@@ -900,14 +897,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
#endif
#ifdef CONFIG_POST
if (gd->post_hotkeys_latch)
post_run (NULL, POST_RAM | POST_SLOWTEST);
else
post_run (NULL, POST_RAM | post_bootmode_get(0));
if (post_bootmode_get(0) & POST_SLOWTEST) {
post_bootmode_clear();
board_poweroff();
}
post_run (NULL, POST_RAM | post_bootmode_get(0));
#endif
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) && !(CONFIG_COMMANDS & CFG_CMD_IDE)
......
......@@ -65,9 +65,11 @@ void post_bootmode_init (void)
DECLARE_GLOBAL_DATA_PTR;
int bootmode = post_bootmode_get (0);
if (bootmode == 0) {
if (post_hotkeys_pressed(gd) && !(bootmode & POST_POWERTEST)) {
bootmode = POST_SLOWTEST;
} else if (bootmode == 0) {
bootmode = POST_POWERON;
} else if (bootmode == POST_POWERON) {
} else if (bootmode == POST_POWERON || bootmode == POST_SLOWTEST) {
bootmode = POST_NORMAL;
} else {
return;
......@@ -96,11 +98,6 @@ int post_bootmode_get (unsigned int *last_test)
return bootmode;
}
void post_bootmode_clear (void)
{
post_word_store (0);
}
/* POST tests run before relocation only mark status bits .... */
static void post_log_mark_start ( unsigned long testid )
{
......@@ -203,6 +200,12 @@ static void post_get_flags (int *test_flags)
name = s + 1;
}
}
for (j = 0; j < post_list_size; j++) {
if (test_flags[j] & POST_POWERON) {
test_flags[j] |= POST_SLOWTEST;
}
}
}
static int post_run_single (struct post_test *test,
......
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